From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair Francis <alistair.francis@wdc.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v2 01/37] target/riscv: implementation-defined constant parameters Date: Thu, 10 Jun 2021 15:58:32 +0800 [thread overview] Message-ID: <20210610075908.3305506-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> ext_psfoperand is whether to support Zpsfoperand sub-extension. pext_ver is the packed specification version, default value is v0.9.4. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu.h | 6 ++++++ target/riscv/translate.c | 2 ++ 3 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..9d8cf60a1c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,6 +137,11 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +static void set_pext_version(CPURISCVState *env, int pext_ver) +{ + env->pext_ver = pext_ver; +} + static void set_feature(CPURISCVState *env, int feature) { env->features |= (1ULL << feature); @@ -395,6 +400,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) int priv_version = PRIV_VERSION_1_11_0; int bext_version = BEXT_VERSION_0_93_0; int vext_version = VEXT_VERSION_0_07_1; + int pext_version = PEXT_VERSION_0_09_4; target_ulong target_misa = env->misa; Error *local_err = NULL; @@ -420,6 +426,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_priv_version(env, priv_version); set_bext_version(env, bext_version); set_vext_version(env, vext_version); + set_pext_version(env, pext_version); if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); @@ -553,6 +560,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_p) { + target_misa |= RVP; + if (cpu->cfg.pext_spec) { + if (!g_strcmp0(cpu->cfg.pext_spec, "v0.9.4")) { + pext_version = PEXT_VERSION_0_09_4; + } else { + error_setg(errp, + "Unsupported packed spec version '%s'", + cpu->cfg.pext_spec); + return; + } + } else { + qemu_log("packed verison is not specified, " + "use the default value v0.9.4\n"); + } + if (env->misa == RV64) { + if (!cpu->cfg.ext_psfoperand) { + error_setg(errp, "The Zpsfoperand" + "sub-extensions is required for RV64P."); + return; + } + } + set_pext_version(env, pext_version); + } set_misa(env, target_misa); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..4d20afb267 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -63,6 +63,7 @@ #define RVF RV('F') #define RVD RV('D') #define RVV RV('V') +#define RVP RV('P') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -85,6 +86,7 @@ enum { #define BEXT_VERSION_0_93_0 0x00009300 #define VEXT_VERSION_0_07_1 0x00000701 +#define PEXT_VERSION_0_09_4 0x00000904 enum { TRANSLATE_SUCCESS, @@ -135,6 +137,7 @@ struct CPURISCVState { target_ulong priv_ver; target_ulong bext_ver; target_ulong vext_ver; + target_ulong pext_ver; target_ulong misa; target_ulong misa_mask; @@ -293,14 +296,17 @@ struct RISCVCPU { bool ext_u; bool ext_h; bool ext_v; + bool ext_p; bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_psfoperand; char *priv_spec; char *user_spec; char *bext_spec; char *vext_spec; + char *pext_spec; uint16_t vlen; uint16_t elen; bool mmu; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c6e8739614..0e6ede4d71 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,7 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + bool ext_psfoperand; bool hlsx; /* vector extension */ bool vill; @@ -965,6 +966,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->ext_psfoperand = cpu->cfg.ext_psfoperand; ctx->cs = cs; } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PATCH v2 01/37] target/riscv: implementation-defined constant parameters Date: Thu, 10 Jun 2021 15:58:32 +0800 [thread overview] Message-ID: <20210610075908.3305506-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> ext_psfoperand is whether to support Zpsfoperand sub-extension. pext_ver is the packed specification version, default value is v0.9.4. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu.h | 6 ++++++ target/riscv/translate.c | 2 ++ 3 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..9d8cf60a1c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,6 +137,11 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +static void set_pext_version(CPURISCVState *env, int pext_ver) +{ + env->pext_ver = pext_ver; +} + static void set_feature(CPURISCVState *env, int feature) { env->features |= (1ULL << feature); @@ -395,6 +400,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) int priv_version = PRIV_VERSION_1_11_0; int bext_version = BEXT_VERSION_0_93_0; int vext_version = VEXT_VERSION_0_07_1; + int pext_version = PEXT_VERSION_0_09_4; target_ulong target_misa = env->misa; Error *local_err = NULL; @@ -420,6 +426,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_priv_version(env, priv_version); set_bext_version(env, bext_version); set_vext_version(env, vext_version); + set_pext_version(env, pext_version); if (cpu->cfg.mmu) { set_feature(env, RISCV_FEATURE_MMU); @@ -553,6 +560,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_p) { + target_misa |= RVP; + if (cpu->cfg.pext_spec) { + if (!g_strcmp0(cpu->cfg.pext_spec, "v0.9.4")) { + pext_version = PEXT_VERSION_0_09_4; + } else { + error_setg(errp, + "Unsupported packed spec version '%s'", + cpu->cfg.pext_spec); + return; + } + } else { + qemu_log("packed verison is not specified, " + "use the default value v0.9.4\n"); + } + if (env->misa == RV64) { + if (!cpu->cfg.ext_psfoperand) { + error_setg(errp, "The Zpsfoperand" + "sub-extensions is required for RV64P."); + return; + } + } + set_pext_version(env, pext_version); + } set_misa(env, target_misa); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..4d20afb267 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -63,6 +63,7 @@ #define RVF RV('F') #define RVD RV('D') #define RVV RV('V') +#define RVP RV('P') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -85,6 +86,7 @@ enum { #define BEXT_VERSION_0_93_0 0x00009300 #define VEXT_VERSION_0_07_1 0x00000701 +#define PEXT_VERSION_0_09_4 0x00000904 enum { TRANSLATE_SUCCESS, @@ -135,6 +137,7 @@ struct CPURISCVState { target_ulong priv_ver; target_ulong bext_ver; target_ulong vext_ver; + target_ulong pext_ver; target_ulong misa; target_ulong misa_mask; @@ -293,14 +296,17 @@ struct RISCVCPU { bool ext_u; bool ext_h; bool ext_v; + bool ext_p; bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_psfoperand; char *priv_spec; char *user_spec; char *bext_spec; char *vext_spec; + char *pext_spec; uint16_t vlen; uint16_t elen; bool mmu; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c6e8739614..0e6ede4d71 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,7 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + bool ext_psfoperand; bool hlsx; /* vector extension */ bool vill; @@ -965,6 +966,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->ext_psfoperand = cpu->cfg.ext_psfoperand; ctx->cs = cs; } -- 2.25.1
next prev parent reply other threads:[~2021-06-10 8:01 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei [this message] 2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 18:00 ` Richard Henderson 2021-06-10 18:00 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:39 ` Richard Henderson 2021-06-10 19:39 ` Richard Henderson 2021-06-11 4:36 ` LIU Zhiwei 2021-06-11 4:36 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:44 ` Richard Henderson 2021-06-10 19:44 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-14 22:55 ` no-reply
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