From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions Date: Thu, 10 Jun 2021 15:59:07 +0800 [thread overview] Message-ID: <20210610075908.3305506-37-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> Concat two 32-bit elements to form a 64-bit element. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 ++++ target/riscv/packed_helper.c | 41 +++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b998c86abf..bfcf0ff761 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1474,3 +1474,8 @@ DEF_HELPER_3(smdrs32, i64, env, i64, i64) DEF_HELPER_3(smxds32, i64, env, i64, i64) DEF_HELPER_3(sraiw_u, i64, env, i64, i64) + +DEF_HELPER_3(pkbb32, i64, env, i64, i64) +DEF_HELPER_3(pkbt32, i64, env, i64, i64) +DEF_HELPER_3(pktt32, i64, env, i64, i64) +DEF_HELPER_3(pktb32, i64, env, i64, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8e8aca4ea1..65682f70b5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1097,3 +1097,8 @@ smdrs32 0110100 ..... ..... 010 ..... 1110111 @r smxds32 0111100 ..... ..... 010 ..... 1110111 @r sraiw_u 0011010 ..... ..... 001 ..... 1110111 @sh5 + +pkbb32 0000111 ..... ..... 010 ..... 1110111 @r +pkbt32 0001111 ..... ..... 010 ..... 1110111 @r +pktt32 0010111 ..... ..... 010 ..... 1110111 @r +pktb32 0011111 ..... ..... 010 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 68c1ef9f48..7505a0f89b 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1147,3 +1147,9 @@ GEN_RVP64_R_OOL(smxds32); /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */ GEN_RVP64_SHIFTI(sraiw_u, gen_helper_sraiw_u); + +/* (RV64 Only) 32-bit Packing Instructions */ +GEN_RVP64_R_OOL(pkbb32); +GEN_RVP64_R_OOL(pkbt32); +GEN_RVP64_R_OOL(pktt32); +GEN_RVP64_R_OOL(pktb32); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 42f1d96fa5..3f4bc593f9 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3808,3 +3808,44 @@ static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va, } RVPR64_64_64(sraiw_u, 1, 8); + +/* (RV64 Only) 32-bit packing instructions here */ +static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbb32, 2, 4); + +static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbt32, 2, 4); + +static inline void do_pktb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktb32, 2, 4); + +static inline void do_pktt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktt32, 2, 4); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions Date: Thu, 10 Jun 2021 15:59:07 +0800 [thread overview] Message-ID: <20210610075908.3305506-37-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> Concat two 32-bit elements to form a 64-bit element. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 ++++ target/riscv/packed_helper.c | 41 +++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b998c86abf..bfcf0ff761 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1474,3 +1474,8 @@ DEF_HELPER_3(smdrs32, i64, env, i64, i64) DEF_HELPER_3(smxds32, i64, env, i64, i64) DEF_HELPER_3(sraiw_u, i64, env, i64, i64) + +DEF_HELPER_3(pkbb32, i64, env, i64, i64) +DEF_HELPER_3(pkbt32, i64, env, i64, i64) +DEF_HELPER_3(pktt32, i64, env, i64, i64) +DEF_HELPER_3(pktb32, i64, env, i64, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8e8aca4ea1..65682f70b5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1097,3 +1097,8 @@ smdrs32 0110100 ..... ..... 010 ..... 1110111 @r smxds32 0111100 ..... ..... 010 ..... 1110111 @r sraiw_u 0011010 ..... ..... 001 ..... 1110111 @sh5 + +pkbb32 0000111 ..... ..... 010 ..... 1110111 @r +pkbt32 0001111 ..... ..... 010 ..... 1110111 @r +pktt32 0010111 ..... ..... 010 ..... 1110111 @r +pktb32 0011111 ..... ..... 010 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 68c1ef9f48..7505a0f89b 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1147,3 +1147,9 @@ GEN_RVP64_R_OOL(smxds32); /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */ GEN_RVP64_SHIFTI(sraiw_u, gen_helper_sraiw_u); + +/* (RV64 Only) 32-bit Packing Instructions */ +GEN_RVP64_R_OOL(pkbb32); +GEN_RVP64_R_OOL(pkbt32); +GEN_RVP64_R_OOL(pktt32); +GEN_RVP64_R_OOL(pktb32); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 42f1d96fa5..3f4bc593f9 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3808,3 +3808,44 @@ static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va, } RVPR64_64_64(sraiw_u, 1, 8); + +/* (RV64 Only) 32-bit packing instructions here */ +static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbb32, 2, 4); + +static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbt32, 2, 4); + +static inline void do_pktb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktb32, 2, 4); + +static inline void do_pktt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktt32, 2, 4); -- 2.25.1
next prev parent reply other threads:[~2021-06-10 8:25 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 18:00 ` Richard Henderson 2021-06-10 18:00 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:39 ` Richard Henderson 2021-06-10 19:39 ` Richard Henderson 2021-06-11 4:36 ` LIU Zhiwei 2021-06-11 4:36 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:44 ` Richard Henderson 2021-06-10 19:44 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei [this message] 2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-14 22:55 ` no-reply
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