From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair Francis <alistair.francis@wdc.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions Date: Thu, 10 Jun 2021 15:58:50 +0800 [thread overview] Message-ID: <20210610075908.3305506-20-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> 32-bit signed or unsigned clip value. 32-bit leading redundant sign, leading zero, leading one count. Parallel byte sum of absolute difference or parallel byte sum of absolute difference accumulation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 8 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvp.c.inc | 9 +++ target/riscv/packed_helper.c | 75 +++++++++++++++++++++++++ 4 files changed, 100 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a37b023c53..35c8c61b00 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1318,3 +1318,11 @@ DEF_HELPER_4(kmsda, tl, env, tl, tl, tl) DEF_HELPER_4(kmsxda, tl, env, tl, tl, tl) DEF_HELPER_3(smal, i64, env, i64, tl) + +DEF_HELPER_3(sclip32, tl, env, tl, tl) +DEF_HELPER_3(uclip32, tl, env, tl, tl) +DEF_HELPER_2(clrs32, tl, env, tl) +DEF_HELPER_2(clz32, tl, env, tl) +DEF_HELPER_2(clo32, tl, env, tl) +DEF_HELPER_3(pbsad, tl, env, tl, tl) +DEF_HELPER_4(pbsada, tl, env, tl, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 233df941b4..ce8bdee34b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -921,3 +921,11 @@ kmsda 0100110 ..... ..... 001 ..... 1110111 @r kmsxda 0100111 ..... ..... 001 ..... 1110111 @r smal 0101111 ..... ..... 001 ..... 1110111 @r + +sclip32 1110010 ..... ..... 000 ..... 1110111 @sh5 +uclip32 1111010 ..... ..... 000 ..... 1110111 @sh5 +clrs32 1010111 11000 ..... 000 ..... 1110111 @r2 +clz32 1010111 11001 ..... 000 ..... 1110111 @r2 +clo32 1010111 11011 ..... 000 ..... 1110111 @r2 +pbsad 1111110 ..... ..... 000 ..... 1110111 @r +pbsada 1111111 ..... ..... 000 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 8b0728fc5a..43e7e5a75d 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -502,3 +502,12 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ } GEN_RVP_R_D64_S64_OOL(smal); + +/* Partial-SIMD Miscellaneous Instructions */ +GEN_RVP_SHIFTI(sclip32, NULL, gen_helper_sclip32); +GEN_RVP_SHIFTI(uclip32, NULL, gen_helper_uclip32); +GEN_RVP_R2_OOL(clrs32); +GEN_RVP_R2_OOL(clz32); +GEN_RVP_R2_OOL(clo32); +GEN_RVP_R_OOL(pbsad); +GEN_RVP_R_ACC_OOL(pbsada); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 1f9a5d620f..1f2b90c394 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1969,3 +1969,78 @@ uint64_t helper_smal(CPURISCVState *env, uint64_t a, target_ulong b) } return result; } + +/* Partial-SIMD Miscellaneous Instructions */ +static inline void do_sclip32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x1f; + + d[i] = sat64(env, a[i], shift); +} + +RVPR(sclip32, 1, 4); + +static inline void do_uclip32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x1f; + + if (a[i] < 0) { + d[i] = 0; + env->vxsat = 0x1; + } else { + d[i] = satu64(env, a[i], shift); + } +} + +RVPR(uclip32, 1, 4); + +static inline void do_clrs32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + d[i] = clrsb32(a[i]); +} + +RVPR2(clrs32, 1, 4); + +static inline void do_clz32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + d[i] = clz32(a[i]); +} + +RVPR2(clz32, 1, 4); + +static inline void do_clo32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + d[i] = clo32(a[i]); +} + +RVPR2(clo32, 1, 4); + +static inline void do_pbsad(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + target_ulong *d = vd; + uint8_t *a = va, *b = vb; + *d += abs(a[i] - b[i]); +} + +RVPR(pbsad, 1, 1); + +static inline void do_pbsada(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + target_ulong *d = vd, *c = vc; + uint8_t *a = va, *b = vb; + if (i == 0) { + *d += *c; + } + *d += abs(a[i] - b[i]); +} + +RVPR_ACC(pbsada, 1, 1); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions Date: Thu, 10 Jun 2021 15:58:50 +0800 [thread overview] Message-ID: <20210610075908.3305506-20-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> 32-bit signed or unsigned clip value. 32-bit leading redundant sign, leading zero, leading one count. Parallel byte sum of absolute difference or parallel byte sum of absolute difference accumulation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 8 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvp.c.inc | 9 +++ target/riscv/packed_helper.c | 75 +++++++++++++++++++++++++ 4 files changed, 100 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a37b023c53..35c8c61b00 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1318,3 +1318,11 @@ DEF_HELPER_4(kmsda, tl, env, tl, tl, tl) DEF_HELPER_4(kmsxda, tl, env, tl, tl, tl) DEF_HELPER_3(smal, i64, env, i64, tl) + +DEF_HELPER_3(sclip32, tl, env, tl, tl) +DEF_HELPER_3(uclip32, tl, env, tl, tl) +DEF_HELPER_2(clrs32, tl, env, tl) +DEF_HELPER_2(clz32, tl, env, tl) +DEF_HELPER_2(clo32, tl, env, tl) +DEF_HELPER_3(pbsad, tl, env, tl, tl) +DEF_HELPER_4(pbsada, tl, env, tl, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 233df941b4..ce8bdee34b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -921,3 +921,11 @@ kmsda 0100110 ..... ..... 001 ..... 1110111 @r kmsxda 0100111 ..... ..... 001 ..... 1110111 @r smal 0101111 ..... ..... 001 ..... 1110111 @r + +sclip32 1110010 ..... ..... 000 ..... 1110111 @sh5 +uclip32 1111010 ..... ..... 000 ..... 1110111 @sh5 +clrs32 1010111 11000 ..... 000 ..... 1110111 @r2 +clz32 1010111 11001 ..... 000 ..... 1110111 @r2 +clo32 1010111 11011 ..... 000 ..... 1110111 @r2 +pbsad 1111110 ..... ..... 000 ..... 1110111 @r +pbsada 1111111 ..... ..... 000 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 8b0728fc5a..43e7e5a75d 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -502,3 +502,12 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ } GEN_RVP_R_D64_S64_OOL(smal); + +/* Partial-SIMD Miscellaneous Instructions */ +GEN_RVP_SHIFTI(sclip32, NULL, gen_helper_sclip32); +GEN_RVP_SHIFTI(uclip32, NULL, gen_helper_uclip32); +GEN_RVP_R2_OOL(clrs32); +GEN_RVP_R2_OOL(clz32); +GEN_RVP_R2_OOL(clo32); +GEN_RVP_R_OOL(pbsad); +GEN_RVP_R_ACC_OOL(pbsada); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 1f9a5d620f..1f2b90c394 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1969,3 +1969,78 @@ uint64_t helper_smal(CPURISCVState *env, uint64_t a, target_ulong b) } return result; } + +/* Partial-SIMD Miscellaneous Instructions */ +static inline void do_sclip32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x1f; + + d[i] = sat64(env, a[i], shift); +} + +RVPR(sclip32, 1, 4); + +static inline void do_uclip32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x1f; + + if (a[i] < 0) { + d[i] = 0; + env->vxsat = 0x1; + } else { + d[i] = satu64(env, a[i], shift); + } +} + +RVPR(uclip32, 1, 4); + +static inline void do_clrs32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + d[i] = clrsb32(a[i]); +} + +RVPR2(clrs32, 1, 4); + +static inline void do_clz32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + d[i] = clz32(a[i]); +} + +RVPR2(clz32, 1, 4); + +static inline void do_clo32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + d[i] = clo32(a[i]); +} + +RVPR2(clo32, 1, 4); + +static inline void do_pbsad(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + target_ulong *d = vd; + uint8_t *a = va, *b = vb; + *d += abs(a[i] - b[i]); +} + +RVPR(pbsad, 1, 1); + +static inline void do_pbsada(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + target_ulong *d = vd, *c = vc; + uint8_t *a = va, *b = vb; + if (i == 0) { + *d += *c; + } + *d += abs(a[i] - b[i]); +} + +RVPR_ACC(pbsada, 1, 1); -- 2.25.1
next prev parent reply other threads:[~2021-06-10 8:23 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 18:00 ` Richard Henderson 2021-06-10 18:00 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:39 ` Richard Henderson 2021-06-10 19:39 ` Richard Henderson 2021-06-11 4:36 ` LIU Zhiwei 2021-06-11 4:36 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:44 ` Richard Henderson 2021-06-10 19:44 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei [this message] 2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-14 22:55 ` no-reply
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