From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions Date: Thu, 10 Jun 2021 15:58:57 +0800 [thread overview] Message-ID: <20210610075908.3305506-27-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> 32-bit halving addition or subtraction, maximum, minimum, or multiply. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvp.c.inc | 10 +++ target/riscv/packed_helper.c | 92 +++++++++++++++++++++++++ 4 files changed, 120 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b3485f95a2..3063b583f3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1384,3 +1384,12 @@ DEF_HELPER_4(kdmabb, tl, env, tl, tl, tl) DEF_HELPER_4(kdmabt, tl, env, tl, tl, tl) DEF_HELPER_4(kdmatt, tl, env, tl, tl, tl) DEF_HELPER_2(kabsw, tl, env, tl) + +DEF_HELPER_3(raddw, tl, env, tl, tl) +DEF_HELPER_3(uraddw, tl, env, tl, tl) +DEF_HELPER_3(rsubw, tl, env, tl, tl) +DEF_HELPER_3(ursubw, tl, env, tl, tl) +DEF_HELPER_3(maxw, tl, env, tl, tl) +DEF_HELPER_3(minw, tl, env, tl, tl) +DEF_HELPER_3(mulr64, i64, env, tl, tl) +DEF_HELPER_3(mulsr64, i64, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a25294baab..9cfe5570b0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -988,3 +988,12 @@ kdmabb 1101001 ..... ..... 001 ..... 1110111 @r kdmabt 1110001 ..... ..... 001 ..... 1110111 @r kdmatt 1111001 ..... ..... 001 ..... 1110111 @r kabsw 1010110 10100 ..... 000 ..... 1110111 @r2 + +raddw 0010000 ..... ..... 001 ..... 1110111 @r +uraddw 0011000 ..... ..... 001 ..... 1110111 @r +rsubw 0010001 ..... ..... 001 ..... 1110111 @r +ursubw 0011001 ..... ..... 001 ..... 1110111 @r +maxw 1111001 ..... ..... 000 ..... 1110111 @r +minw 1111000 ..... ..... 000 ..... 1110111 @r +mulr64 1111000 ..... ..... 001 ..... 1110111 @r +mulsr64 1110000 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index d2c7ab1440..b720c6e037 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -698,3 +698,13 @@ GEN_RVP_R_ACC_OOL(kdmabb); GEN_RVP_R_ACC_OOL(kdmabt); GEN_RVP_R_ACC_OOL(kdmatt); GEN_RVP_R2_OOL(kabsw); + +/* 32-bit Computation Instructions */ +GEN_RVP_R_OOL(raddw); +GEN_RVP_R_OOL(uraddw); +GEN_RVP_R_OOL(rsubw); +GEN_RVP_R_OOL(ursubw); +GEN_RVP_R_OOL(minw); +GEN_RVP_R_OOL(maxw); +GEN_RVP_R_D64_OOL(mulr64); +GEN_RVP_R_D64_OOL(mulsr64); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 89d203730d..c0e3b6bbdb 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -2818,3 +2818,95 @@ static inline void do_kabsw(CPURISCVState *env, void *vd, void *va, uint8_t i) } RVPR2(kabsw, 2, 4); + +/* 32-bit Computation Instructions */ +static inline void do_raddw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *a = va, *b = vb; + target_long *d = vd; + + *d = hadd32(a[H4(i)], b[H4(i)]); +} + +RVPR(raddw, 2, 4); + +static inline void do_uraddw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *a = va, *b = vb; + target_long *d = vd; + + *d = (int32_t)haddu32(a[H4(i)], b[H4(i)]); +} + +RVPR(uraddw, 2, 4); + +static inline void do_rsubw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *a = va, *b = vb; + target_long *d = vd; + + *d = hsub32(a[H4(i)], b[H4(i)]); +} + +RVPR(rsubw, 2, 4); + +static inline void do_ursubw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *a = va, *b = vb; + target_long *d = vd; + + *d = (int32_t)hsubu64(a[H4(i)], b[H4(i)]); +} + +RVPR(ursubw, 2, 4); + +static inline void do_maxw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + target_long *d = vd; + int32_t *a = va, *b = vb; + + *d = (a[H4(i)] > b[H4(i)]) ? a[H4(i)] : b[H4(i)]; +} + +RVPR(maxw, 2, 4); + +static inline void do_minw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + target_long *d = vd; + int32_t *a = va, *b = vb; + + *d = (a[H4(i)] < b[H4(i)]) ? a[H4(i)] : b[H4(i)]; +} + +RVPR(minw, 2, 4); + +static inline void do_mulr64(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint64_t *d = vd; + uint32_t *a = va, *b = vb; + + *d = (uint64_t)a[H4(0)] * b[H4(0)]; +} + +RVPR64(mulr64); + +static inline void do_mulsr64(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd; + int64_t result; + int32_t *a = va, *b = vb; + + result = (int64_t)a[H4(0)] * b[H4(0)]; + d[H4(1)] = result >> 32; + d[H4(0)] = result & UINT32_MAX; +} + +RVPR64(mulsr64); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions Date: Thu, 10 Jun 2021 15:58:57 +0800 [thread overview] Message-ID: <20210610075908.3305506-27-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> 32-bit halving addition or subtraction, maximum, minimum, or multiply. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvp.c.inc | 10 +++ target/riscv/packed_helper.c | 92 +++++++++++++++++++++++++ 4 files changed, 120 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b3485f95a2..3063b583f3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1384,3 +1384,12 @@ DEF_HELPER_4(kdmabb, tl, env, tl, tl, tl) DEF_HELPER_4(kdmabt, tl, env, tl, tl, tl) DEF_HELPER_4(kdmatt, tl, env, tl, tl, tl) DEF_HELPER_2(kabsw, tl, env, tl) + +DEF_HELPER_3(raddw, tl, env, tl, tl) +DEF_HELPER_3(uraddw, tl, env, tl, tl) +DEF_HELPER_3(rsubw, tl, env, tl, tl) +DEF_HELPER_3(ursubw, tl, env, tl, tl) +DEF_HELPER_3(maxw, tl, env, tl, tl) +DEF_HELPER_3(minw, tl, env, tl, tl) +DEF_HELPER_3(mulr64, i64, env, tl, tl) +DEF_HELPER_3(mulsr64, i64, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a25294baab..9cfe5570b0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -988,3 +988,12 @@ kdmabb 1101001 ..... ..... 001 ..... 1110111 @r kdmabt 1110001 ..... ..... 001 ..... 1110111 @r kdmatt 1111001 ..... ..... 001 ..... 1110111 @r kabsw 1010110 10100 ..... 000 ..... 1110111 @r2 + +raddw 0010000 ..... ..... 001 ..... 1110111 @r +uraddw 0011000 ..... ..... 001 ..... 1110111 @r +rsubw 0010001 ..... ..... 001 ..... 1110111 @r +ursubw 0011001 ..... ..... 001 ..... 1110111 @r +maxw 1111001 ..... ..... 000 ..... 1110111 @r +minw 1111000 ..... ..... 000 ..... 1110111 @r +mulr64 1111000 ..... ..... 001 ..... 1110111 @r +mulsr64 1110000 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index d2c7ab1440..b720c6e037 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -698,3 +698,13 @@ GEN_RVP_R_ACC_OOL(kdmabb); GEN_RVP_R_ACC_OOL(kdmabt); GEN_RVP_R_ACC_OOL(kdmatt); GEN_RVP_R2_OOL(kabsw); + +/* 32-bit Computation Instructions */ +GEN_RVP_R_OOL(raddw); +GEN_RVP_R_OOL(uraddw); +GEN_RVP_R_OOL(rsubw); +GEN_RVP_R_OOL(ursubw); +GEN_RVP_R_OOL(minw); +GEN_RVP_R_OOL(maxw); +GEN_RVP_R_D64_OOL(mulr64); +GEN_RVP_R_D64_OOL(mulsr64); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 89d203730d..c0e3b6bbdb 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -2818,3 +2818,95 @@ static inline void do_kabsw(CPURISCVState *env, void *vd, void *va, uint8_t i) } RVPR2(kabsw, 2, 4); + +/* 32-bit Computation Instructions */ +static inline void do_raddw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *a = va, *b = vb; + target_long *d = vd; + + *d = hadd32(a[H4(i)], b[H4(i)]); +} + +RVPR(raddw, 2, 4); + +static inline void do_uraddw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *a = va, *b = vb; + target_long *d = vd; + + *d = (int32_t)haddu32(a[H4(i)], b[H4(i)]); +} + +RVPR(uraddw, 2, 4); + +static inline void do_rsubw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *a = va, *b = vb; + target_long *d = vd; + + *d = hsub32(a[H4(i)], b[H4(i)]); +} + +RVPR(rsubw, 2, 4); + +static inline void do_ursubw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *a = va, *b = vb; + target_long *d = vd; + + *d = (int32_t)hsubu64(a[H4(i)], b[H4(i)]); +} + +RVPR(ursubw, 2, 4); + +static inline void do_maxw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + target_long *d = vd; + int32_t *a = va, *b = vb; + + *d = (a[H4(i)] > b[H4(i)]) ? a[H4(i)] : b[H4(i)]; +} + +RVPR(maxw, 2, 4); + +static inline void do_minw(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + target_long *d = vd; + int32_t *a = va, *b = vb; + + *d = (a[H4(i)] < b[H4(i)]) ? a[H4(i)] : b[H4(i)]; +} + +RVPR(minw, 2, 4); + +static inline void do_mulr64(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint64_t *d = vd; + uint32_t *a = va, *b = vb; + + *d = (uint64_t)a[H4(0)] * b[H4(0)]; +} + +RVPR64(mulr64); + +static inline void do_mulsr64(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd; + int64_t result; + int32_t *a = va, *b = vb; + + result = (int64_t)a[H4(0)] * b[H4(0)]; + d[H4(1)] = result >> 32; + d[H4(0)] = result & UINT32_MAX; +} + +RVPR64(mulsr64); -- 2.25.1
next prev parent reply other threads:[~2021-06-10 8:14 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 18:00 ` Richard Henderson 2021-06-10 18:00 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:39 ` Richard Henderson 2021-06-10 19:39 ` Richard Henderson 2021-06-11 4:36 ` LIU Zhiwei 2021-06-11 4:36 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-24 6:05 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 19:44 ` Richard Henderson 2021-06-10 19:44 ` Richard Henderson 2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei [this message] 2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-10 7:58 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-10 7:59 ` LIU Zhiwei 2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-14 22:55 ` no-reply
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