From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmerdabbelt@google.com>,
palmer@dabbelt.com, bin.meng@windriver.com,
Alistair.Francis@wdc.com
Subject: Re: [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
Date: Fri, 11 Jun 2021 12:36:40 +0800 [thread overview]
Message-ID: <e2151646-0e97-01db-8ecd-9ed81d92f733@c-sky.com> (raw)
In-Reply-To: <cdb22947-9ca7-9353-b189-a70a94d7c7ab@linaro.org>
On 6/11/21 3:39 AM, Richard Henderson wrote:
> On 6/10/21 12:58 AM, LIU Zhiwei wrote:
>> include/tcg/tcg-op-gvec.h | 6 ++
>> tcg/tcg-op-gvec.c | 47 ++++++++++++++++
>
> Likewise, should be split from the larger patch.
>
OK
>> +static void gen_addv_mask_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b,
>> TCGv_i32 m)
>> +{
>> + TCGv_i32 t1 = tcg_temp_new_i32();
>> + TCGv_i32 t2 = tcg_temp_new_i32();
>> + TCGv_i32 t3 = tcg_temp_new_i32();
>> +
>> + tcg_gen_andc_i32(t1, a, m);
>> + tcg_gen_andc_i32(t2, b, m);
>> + tcg_gen_xor_i32(t3, a, b);
>> + tcg_gen_add_i32(d, t1, t2);
>> + tcg_gen_and_i32(t3, t3, m);
>> + tcg_gen_xor_i32(d, d, t3);
>> +
>> + tcg_temp_free_i32(t1);
>> + tcg_temp_free_i32(t2);
>> + tcg_temp_free_i32(t3);
>> +}
>> +
>> +void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
>> +{
>> + TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80));
>> + gen_addv_mask_i32(d, a, b, m);
>> +}
>
> There will only ever be one use; we might as well merge them.
> The cast is unnecessary.
A little puzzling. Should I still split it?
Zhiwei
>
>
> r~
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
bin.meng@windriver.com, Palmer Dabbelt <palmerdabbelt@google.com>
Subject: Re: [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction
Date: Fri, 11 Jun 2021 12:36:40 +0800 [thread overview]
Message-ID: <e2151646-0e97-01db-8ecd-9ed81d92f733@c-sky.com> (raw)
In-Reply-To: <cdb22947-9ca7-9353-b189-a70a94d7c7ab@linaro.org>
On 6/11/21 3:39 AM, Richard Henderson wrote:
> On 6/10/21 12:58 AM, LIU Zhiwei wrote:
>> include/tcg/tcg-op-gvec.h | 6 ++
>> tcg/tcg-op-gvec.c | 47 ++++++++++++++++
>
> Likewise, should be split from the larger patch.
>
OK
>> +static void gen_addv_mask_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b,
>> TCGv_i32 m)
>> +{
>> + TCGv_i32 t1 = tcg_temp_new_i32();
>> + TCGv_i32 t2 = tcg_temp_new_i32();
>> + TCGv_i32 t3 = tcg_temp_new_i32();
>> +
>> + tcg_gen_andc_i32(t1, a, m);
>> + tcg_gen_andc_i32(t2, b, m);
>> + tcg_gen_xor_i32(t3, a, b);
>> + tcg_gen_add_i32(d, t1, t2);
>> + tcg_gen_and_i32(t3, t3, m);
>> + tcg_gen_xor_i32(d, d, t3);
>> +
>> + tcg_temp_free_i32(t1);
>> + tcg_temp_free_i32(t2);
>> + tcg_temp_free_i32(t3);
>> +}
>> +
>> +void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
>> +{
>> + TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80));
>> + gen_addv_mask_i32(d, a, b, m);
>> +}
>
> There will only ever be one use; we might as well merge them.
> The cast is unnecessary.
A little puzzling. Should I still split it?
Zhiwei
>
>
> r~
next prev parent reply other threads:[~2021-06-11 4:37 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 18:00 ` Richard Henderson
2021-06-10 18:00 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 19:39 ` Richard Henderson
2021-06-10 19:39 ` Richard Henderson
2021-06-11 4:36 ` LIU Zhiwei [this message]
2021-06-11 4:36 ` LIU Zhiwei
2021-06-24 6:05 ` LIU Zhiwei
2021-06-24 6:05 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 19:44 ` Richard Henderson
2021-06-10 19:44 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-06-10 7:59 ` LIU Zhiwei
2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply
2021-06-14 22:55 ` no-reply
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