* [PATCH v3 01/16] pci: Use const for pci_find_device_id() etc.
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
@ 2021-06-27 23:50 ` Simon Glass
2021-06-27 23:50 ` [PATCH v3 02/16] x86: pci: Allow binding of some devices before relocation Simon Glass
` (15 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:50 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
These functions don't modify the device-ID struct that is passed in, so
mark the argument as const, so the data structure can be declared that
way. This allows it to be placed in the rodata section.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
drivers/pci/pci-uclass.c | 6 +++---
include/pci.h | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 22a033e6329..d64fbe0627b 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -162,7 +162,7 @@ int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
}
static int pci_device_matches_ids(struct udevice *dev,
- struct pci_device_id *ids)
+ const struct pci_device_id *ids)
{
struct pci_child_plat *pplat;
int i;
@@ -179,7 +179,7 @@ static int pci_device_matches_ids(struct udevice *dev,
return -EINVAL;
}
-int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
+int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
int *indexp, struct udevice **devp)
{
struct udevice *dev;
@@ -199,7 +199,7 @@ int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
return -ENODEV;
}
-int pci_find_device_id(struct pci_device_id *ids, int index,
+int pci_find_device_id(const struct pci_device_id *ids, int index,
struct udevice **devp)
{
struct udevice *bus;
diff --git a/include/pci.h b/include/pci.h
index 2353cebb2a3..2ee6138324f 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1070,7 +1070,7 @@ int pci_get_ff(enum pci_size_t size);
* @devp: Returns matching device if found
* @return 0 if found, -ENODEV if not
*/
-int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
+int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
int *indexp, struct udevice **devp);
/**
@@ -1082,7 +1082,7 @@ int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
* @devp: Returns matching device if found
* @return 0 if found, -ENODEV if not
*/
-int pci_find_device_id(struct pci_device_id *ids, int index,
+int pci_find_device_id(const struct pci_device_id *ids, int index,
struct udevice **devp);
/**
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 02/16] x86: pci: Allow binding of some devices before relocation
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
2021-06-27 23:50 ` [PATCH v3 01/16] pci: Use const for pci_find_device_id() etc Simon Glass
@ 2021-06-27 23:50 ` Simon Glass
2021-06-27 23:50 ` [PATCH v3 03/16] x86: Allow coreboot serial driver to guess the UART Simon Glass
` (14 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:50 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
At present only bridge devices are bound before relocation, to save space
in pre-relocation memory. In some cases we do actually want to bind a
device, e.g. because it provides the console UART. Add a devicetree
binding to support this.
Use the PCI_VENDEV() macro to encode the cell value. This is present in
U-Boot but not used, so move it to the binding header-file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
doc/device-tree-bindings/pci/x86-pci.txt | 7 ++++-
drivers/pci/pci-uclass.c | 33 +++++++++++++++++++++++-
include/dt-bindings/pci/pci.h | 12 +++++++++
include/pci.h | 1 -
4 files changed, 50 insertions(+), 3 deletions(-)
create mode 100644 include/dt-bindings/pci/pci.h
diff --git a/doc/device-tree-bindings/pci/x86-pci.txt b/doc/device-tree-bindings/pci/x86-pci.txt
index 95e370b3e72..cf4e5ed595a 100644
--- a/doc/device-tree-bindings/pci/x86-pci.txt
+++ b/doc/device-tree-bindings/pci/x86-pci.txt
@@ -20,6 +20,10 @@ For PCI devices the following optional property is available:
output to be lost. This should not generally be used in production code,
although it is often harmless.
+- u-boot,pci-pre-reloc : List of vendor/device IDs to bind before relocation, even
+ if they are not bridges. This is useful if the device is needed (e.g. a
+ UART). The format is 0xvvvvdddd where d is the device ID and v is the
+ vendor ID.
Example:
@@ -32,7 +36,8 @@ pci {
0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
u-boot,skip-auto-config-until-reloc;
-
+ u-boot,pci-pre-reloc = <
+ PCI_VENDEV(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2)>;
serial: serial@18,2 {
reg = <0x0200c210 0 0 0 0>;
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index d64fbe0627b..4b52620d6af 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -19,6 +19,7 @@
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h>
#endif
+#include <dt-bindings/pci/pci.h>
#include <linux/delay.h>
#include "pci_internal.h"
@@ -676,6 +677,34 @@ static bool pci_match_one_id(const struct pci_device_id *id,
return false;
}
+/**
+ * pci_need_device_pre_reloc() - Check if a device should be bound
+ *
+ * This checks a list of vendor/device-ID values indicating devices that should
+ * be bound before relocation.
+ *
+ * @bus: Bus to check
+ * @vendor: Vendor ID to check
+ * @device: Device ID to check
+ * @return true if the vendor/device is in the list, false if not
+ */
+static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
+ uint device)
+{
+ u32 vendev;
+ int index;
+
+ for (index = 0;
+ !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
+ &vendev);
+ index++) {
+ if (vendev == PCI_VENDEV(vendor, device))
+ return true;
+ }
+
+ return false;
+}
+
/**
* pci_find_and_bind_driver() - Find and bind the right PCI driver
*
@@ -764,7 +793,9 @@ static int pci_find_and_bind_driver(struct udevice *parent,
* precious memory space as on some platforms as that space is pretty
* limited (ie: using Cache As RAM).
*/
- if (!(gd->flags & GD_FLG_RELOC) && !bridge)
+ if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
+ !pci_need_device_pre_reloc(parent, find_id->vendor,
+ find_id->device))
return log_msg_ret("notbr", -EPERM);
/* Bind a generic driver so that the device can be used */
diff --git a/include/dt-bindings/pci/pci.h b/include/dt-bindings/pci/pci.h
new file mode 100644
index 00000000000..e7290277b90
--- /dev/null
+++ b/include/dt-bindings/pci/pci.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides common constants for PCI bindings.
+ */
+
+#ifndef _DT_BINDINGS_PCI_PCI_H
+#define _DT_BINDINGS_PCI_PCI_H
+
+/* Encode a vendor and device ID into a single cell */
+#define PCI_VENDEV(v, d) (((v) << 16) | (d))
+
+#endif /* _DT_BINDINGS_PCI_PCI_H */
diff --git a/include/pci.h b/include/pci.h
index 2ee6138324f..9eb28aba049 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -578,7 +578,6 @@ typedef int pci_dev_t;
#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
-#define PCI_VENDEV(v, d) (((v) << 16) | (d))
#define PCI_ANY_ID (~0)
/* Convert from Linux format to U-Boot format */
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 03/16] x86: Allow coreboot serial driver to guess the UART
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
2021-06-27 23:50 ` [PATCH v3 01/16] pci: Use const for pci_find_device_id() etc Simon Glass
2021-06-27 23:50 ` [PATCH v3 02/16] x86: pci: Allow binding of some devices before relocation Simon Glass
@ 2021-06-27 23:50 ` Simon Glass
2021-07-15 11:44 ` Bin Meng
2021-06-27 23:50 ` [PATCH v3 04/16] spi: ich: Don't require the PCH Simon Glass
` (13 subsequent siblings)
16 siblings, 1 reply; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:50 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
At present this driver relies on coreboot to provide information about
the console UART. However if coreboot is not compiled with the UART
enabled, the information is left out. This configuration is quite
common, e.g. with shipping x86-based Chrome OS Chromebooks.
Add a way to determine the UART settings in this case, using a
hard-coded list of PCI IDs.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/serial/serial_coreboot.c | 68 ++++++++++++++++++++++++++++----
include/pci_ids.h | 1 +
2 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c
index de09c8681f5..4b4619432d8 100644
--- a/drivers/serial/serial_coreboot.c
+++ b/drivers/serial/serial_coreboot.c
@@ -11,19 +11,71 @@
#include <serial.h>
#include <asm/cb_sysinfo.h>
+static const struct pci_device_id ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2) },
+ {},
+};
+
+/*
+ * Coreboot only sets up the UART if it uses it and doesn't bother to put the
+ * details in sysinfo if it doesn't. Try to guess in that case, using devices
+ * we know about
+ *
+ * @plat: Platform data to fill in
+ * @return 0 if found, -ve if no UART was found
+ */
+static int guess_uart(struct ns16550_plat *plat)
+{
+ struct udevice *bus, *dev;
+ ulong addr;
+ int index;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PCI, &bus);
+ if (ret)
+ return ret;
+ index = 0;
+ ret = pci_bus_find_devices(bus, ids, &index, &dev);
+ if (ret)
+ return ret;
+ addr = dm_pci_read_bar32(dev, 0);
+ plat->base = addr;
+ plat->reg_shift = 2;
+ plat->reg_width = 4;
+ plat->clock = 1843200;
+ plat->fcr = UART_FCR_DEFVAL;
+ plat->flags = 0;
+
+ return 0;
+}
+
static int coreboot_of_to_plat(struct udevice *dev)
{
struct ns16550_plat *plat = dev_get_plat(dev);
struct cb_serial *cb_info = lib_sysinfo.serial;
- plat->base = cb_info->baseaddr;
- plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
- plat->reg_width = cb_info->regwidth;
- plat->clock = cb_info->input_hertz;
- plat->fcr = UART_FCR_DEFVAL;
- plat->flags = 0;
- if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
- plat->flags |= NS16550_FLAG_IO;
+ if (cb_info) {
+ plat->base = cb_info->baseaddr;
+ plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
+ plat->reg_width = cb_info->regwidth;
+ plat->clock = cb_info->input_hertz;
+ plat->fcr = UART_FCR_DEFVAL;
+ plat->flags = 0;
+ if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
+ plat->flags |= NS16550_FLAG_IO;
+ } else if (CONFIG_IS_ENABLED(PCI)) {
+ int ret;
+
+ ret = guess_uart(plat);
+ if (ret) {
+ /*
+ * Returning an error will cause U-Boot to complain that
+ * there is no UART, which may panic. So stay silent and
+ * pray that the video console will work.
+ */
+ log_debug("Cannot detect UART\n");
+ }
+ }
return 0;
}
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 7ecedc7f04c..d91c1d08f1a 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2987,6 +2987,7 @@
#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
+#define PCI_DEVICE_ID_INTEL_APL_UART2 0x5ac0
#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v3 03/16] x86: Allow coreboot serial driver to guess the UART
2021-06-27 23:50 ` [PATCH v3 03/16] x86: Allow coreboot serial driver to guess the UART Simon Glass
@ 2021-07-15 11:44 ` Bin Meng
2021-07-15 15:18 ` Simon Glass
0 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2021-07-15 11:44 UTC (permalink / raw)
To: Simon Glass, Andy Shevchenko; +Cc: U-Boot Mailing List
Hi Simon,
On Mon, Jun 28, 2021 at 7:51 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present this driver relies on coreboot to provide information about
> the console UART. However if coreboot is not compiled with the UART
> enabled, the information is left out. This configuration is quite
> common, e.g. with shipping x86-based Chrome OS Chromebooks.
>
> Add a way to determine the UART settings in this case, using a
> hard-coded list of PCI IDs.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
> drivers/serial/serial_coreboot.c | 68 ++++++++++++++++++++++++++++----
> include/pci_ids.h | 1 +
> 2 files changed, 61 insertions(+), 8 deletions(-)
>
Based on discussion of the last version, this patch should be dropped.
I will see if I can drop it when applying.
Regards,
Bin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 03/16] x86: Allow coreboot serial driver to guess the UART
2021-07-15 11:44 ` Bin Meng
@ 2021-07-15 15:18 ` Simon Glass
0 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-07-15 15:18 UTC (permalink / raw)
To: Bin Meng; +Cc: Andy Shevchenko, U-Boot Mailing List
Hi Bin,
On Thu, 15 Jul 2021 at 05:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Jun 28, 2021 at 7:51 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present this driver relies on coreboot to provide information about
> > the console UART. However if coreboot is not compiled with the UART
> > enabled, the information is left out. This configuration is quite
> > common, e.g. with shipping x86-based Chrome OS Chromebooks.
> >
> > Add a way to determine the UART settings in this case, using a
> > hard-coded list of PCI IDs.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > (no changes since v1)
> >
> > drivers/serial/serial_coreboot.c | 68 ++++++++++++++++++++++++++++----
> > include/pci_ids.h | 1 +
> > 2 files changed, 61 insertions(+), 8 deletions(-)
> >
>
> Based on discussion of the last version, this patch should be dropped.
> I will see if I can drop it when applying.
OK thanks, I'll see what other ideas I can come up with.
Regards,
Simon
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 04/16] spi: ich: Don't require the PCH
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (2 preceding siblings ...)
2021-06-27 23:50 ` [PATCH v3 03/16] x86: Allow coreboot serial driver to guess the UART Simon Glass
@ 2021-06-27 23:50 ` Simon Glass
2021-06-28 6:19 ` Jagan Teki
2021-06-27 23:51 ` [PATCH v3 05/16] tpm: cr50: Drop unnecessary coral headers Simon Glass
` (12 subsequent siblings)
16 siblings, 1 reply; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:50 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Bin Meng, Jagan Teki, Jagannadha Sutradharudu Teki
When booting from coreboot we may not have a PCH driver available. The
SPI driver can operate without the PCH but currently complains in this
case. Update it to continue to work normally. The only missing feature
is memory-mapping of SPI-flash contents, which is not essential.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
drivers/spi/ich.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 1cd410493b0..3d49c22a9da 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -114,7 +114,7 @@ static bool ich9_can_do_33mhz(struct udevice *dev)
struct ich_spi_priv *priv = dev_get_priv(dev);
u32 fdod, speed;
- if (!CONFIG_IS_ENABLED(PCI))
+ if (!CONFIG_IS_ENABLED(PCI) || !priv->pch)
return false;
/* Observe SPI Descriptor Component Section 0 */
dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
@@ -632,7 +632,7 @@ static int ich_spi_get_basics(struct udevice *bus, bool can_probe,
if (device_get_uclass_id(pch) != UCLASS_PCH) {
uclass_first_device(UCLASS_PCH, &pch);
if (!pch)
- return log_msg_ret("uclass", -EPROTOTYPE);
+ ; /* ignore this error since we don't need it */
}
}
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v3 04/16] spi: ich: Don't require the PCH
2021-06-27 23:50 ` [PATCH v3 04/16] spi: ich: Don't require the PCH Simon Glass
@ 2021-06-28 6:19 ` Jagan Teki
0 siblings, 0 replies; 23+ messages in thread
From: Jagan Teki @ 2021-06-28 6:19 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Bin Meng, Jagannadha Sutradharudu Teki
On Mon, Jun 28, 2021 at 5:21 AM Simon Glass <sjg@chromium.org> wrote:
>
> When booting from coreboot we may not have a PCH driver available. The
> SPI driver can operate without the PCH but currently complains in this
> case. Update it to continue to work normally. The only missing feature
> is memory-mapping of SPI-flash contents, which is not essential.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 05/16] tpm: cr50: Drop unnecessary coral headers
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (3 preceding siblings ...)
2021-06-27 23:50 ` [PATCH v3 04/16] spi: ich: Don't require the PCH Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 06/16] x86: Don't set up MTRRs if previously done Simon Glass
` (11 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
These headers are not actually used. Drop them so that this driver can
be used by other boards, e.g. coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
drivers/tpm/cr50_i2c.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 76432bdec1f..7a2b5a4faa5 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -18,8 +18,6 @@
#include <acpi/acpi_device.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/iomap.h>
-#include <asm/arch/pm.h>
#include <linux/delay.h>
#include <dm/acpi.h>
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 06/16] x86: Don't set up MTRRs if previously done
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (4 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 05/16] tpm: cr50: Drop unnecessary coral headers Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 07/16] x86: Update the MP constants to avoid conflicts Simon Glass
` (10 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
When starting U-Boot from a previous-stage bootloader we presumably don't
need to set up the variable MTRRs. In fact this could be harmful if the
existing settings are not what U-Boot uses.
Skip that step in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
arch/x86/cpu/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index e59215cc20e..c7f6c5a013e 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -423,7 +423,7 @@ static void setup_mtrr(void)
u64 mtrr_cap;
/* Configure fixed range MTRRs for some legacy regions */
- if (!gd->arch.has_mtrr)
+ if (!gd->arch.has_mtrr || !ll_boot_init())
return;
mtrr_cap = native_read_msr(MTRR_CAP_MSR);
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 07/16] x86: Update the MP constants to avoid conflicts
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (5 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 06/16] x86: Don't set up MTRRs if previously done Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 08/16] x86: Do cache set-up by default when booting from coreboot Simon Glass
` (9 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for the first CPU.
Correct this by using a different range for the pre-defined CPU
numbers, above zero and out of the range of possible CPU values. For
now it is safe to assume there are no more than 64K CPUs.
This fixes the 'mtrr' command when CONFIG_SMP is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
arch/x86/include/asm/mp.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h
index 1a3ae8e3950..e48ba051d92 100644
--- a/arch/x86/include/asm/mp.h
+++ b/arch/x86/include/asm/mp.h
@@ -10,18 +10,22 @@
#include <asm/atomic.h>
#include <asm/cache.h>
+#include <linux/bitops.h>
struct udevice;
enum {
- /* Indicates that the function should run on all CPUs */
- MP_SELECT_ALL = -1,
+ /*
+ * Indicates that the function should run on all CPUs. We use a large
+ * number, above the number of real CPUs we expect to find.
+ */
+ MP_SELECT_ALL = BIT(16),
/* Run on boot CPUs */
- MP_SELECT_BSP = -2,
+ MP_SELECT_BSP,
/* Run on non-boot CPUs */
- MP_SELECT_APS = -3,
+ MP_SELECT_APS,
};
typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 08/16] x86: Do cache set-up by default when booting from coreboot
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (6 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 07/16] x86: Update the MP constants to avoid conflicts Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 09/16] x86: coreboot: Show the BIOS date Simon Glass
` (8 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.
If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Add a comment about the cases
arch/x86/lib/init_helpers.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 67401b9ba79..f33194045f9 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -18,10 +18,20 @@ int init_cache_f_r(void)
IS_ENABLED(CONFIG_FSP_VERSION2);
int ret;
- if (!ll_boot_init())
- return 0;
-
- do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
+ /*
+ * Supported configurations:
+ *
+ * booting from slimbootloader - in that case the MTRRs are already set
+ * up
+ * booting with FSPv1 - MTRRs are already set up
+ * booting with FSPv2 - MTRRs must be set here
+ * booting from coreboot - in this case there is no SPL, so we set up
+ * the MTRRs here
+ * Note: if there is an SPL, then it has already set up MTRRs so we
+ * don't need to do that here
+ */
+ do_mtrr &= !IS_ENABLED(CONFIG_SPL) &&
+ !IS_ENABLED(CONFIG_FSP_VERSION1) &&
!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
if (do_mtrr) {
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 09/16] x86: coreboot: Show the BIOS date
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (7 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 08/16] x86: Do cache set-up by default when booting from coreboot Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 10/16] x86: coral: Allow booting from coreboot Simon Glass
` (7 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Bin Meng, Stefan Reinauer, Vadim Bendebury
The BIOS version may not be present, e.g. on a Chrome OS build. Add the
BIOS date as well, so we get some sort of indication of coreboot's
vintage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Reorder declaration and use bios_date for the variable name
board/coreboot/coreboot/coreboot.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index 175d3ce691a..11294d6e870 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -37,6 +37,7 @@ int show_board_info(void)
goto fallback;
const char *bios_ver = smbios_string(bios, t0->bios_ver);
+ const char *bios_date = smbios_string(bios, t0->bios_release_date);
const char *model = smbios_string(system, t1->product_name);
const char *manufacturer = smbios_string(system, t1->manufacturer);
@@ -46,6 +47,8 @@ int show_board_info(void)
printf("Vendor: %s\n", manufacturer);
printf("Model: %s\n", model);
printf("BIOS Version: %s\n", bios_ver);
+ if (bios_date)
+ printf("BIOS date: %s\n", bios_date);
return 0;
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 10/16] x86: coral: Allow booting from coreboot
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (8 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 09/16] x86: coreboot: Show the BIOS date Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 11/16] x86: Add function comments to cb_sysinfo.h Simon Glass
` (6 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
Set up coral so that it can boot from coreboot, even though it is a
bare-metal build. This helps with testing since the same image can be used
in both cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Add missing newline in the error path
- Use (ret) instead of (ret != 0) to fit with U-Boot style
board/google/chromebook_coral/coral.c | 28 +++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 3f9235c903b..85cba50d4e5 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -10,17 +10,21 @@
#include <command.h>
#include <cros_ec.h>
#include <dm.h>
+#include <init.h>
#include <log.h>
#include <sysinfo.h>
#include <acpi/acpigen.h>
#include <asm-generic/gpio.h>
#include <asm/acpi_nhlt.h>
+#include <asm/cb_sysinfo.h>
#include <asm/intel_gnvs.h>
#include <asm/intel_pinctrl.h>
#include <dm/acpi.h>
#include <linux/delay.h>
#include "variant_gpio.h"
+DECLARE_GLOBAL_DATA_PTR;
+
struct cros_gpio_info {
const char *linux_name;
enum cros_gpio_t type;
@@ -28,6 +32,30 @@ struct cros_gpio_info {
int flags;
};
+int misc_init_f(void)
+{
+ if (!ll_boot_init()) {
+ printf("Running as secondary loader");
+ if (gd->arch.coreboot_table) {
+ int ret;
+
+ printf(" (found coreboot table at %lx)",
+ gd->arch.coreboot_table);
+
+ ret = get_coreboot_info(&lib_sysinfo);
+ if (ret) {
+ printf("\nFailed to parse coreboot tables (err=%d)\n",
+ ret);
+ return ret;
+ }
+ }
+
+ printf("\n");
+ }
+
+ return 0;
+}
+
int arch_misc_init(void)
{
return 0;
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 11/16] x86: Add function comments to cb_sysinfo.h
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (9 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 10/16] x86: coral: Allow booting from coreboot Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 12/16] x86: coreboot: Use vendor in the Kconfig Simon Glass
` (5 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
Add a function comment for get_coreboot_info() and a declaration for
cb_get_sysinfo(), since this may be called from elsewhere.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
arch/x86/include/asm/cb_sysinfo.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h
index 675eef6f2c9..75901359f98 100644
--- a/arch/x86/include/asm/cb_sysinfo.h
+++ b/arch/x86/include/asm/cb_sysinfo.h
@@ -215,6 +215,22 @@ struct sysinfo_t {
extern struct sysinfo_t lib_sysinfo;
+/**
+ * get_coreboot_info() - parse the coreboot sysinfo table
+ *
+ * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if
+ * so.
+ *
+ * @info: Place to put the parsed information
+ * @return 0 if OK, -ENOENT if no table found
+ */
int get_coreboot_info(struct sysinfo_t *info);
+/**
+ * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo
+ *
+ * @return pointer to sysinfo, or NULL if not available
+ */
+const struct sysinfo_t *cb_get_sysinfo(void);
+
#endif
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 12/16] x86: coreboot: Use vendor in the Kconfig
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (10 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 11/16] x86: Add function comments to cb_sysinfo.h Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 13/16] x86: coreboot: Document the memory map Simon Glass
` (4 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Bin Meng, Stefan Reinauer, Vadim Bendebury
Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple
coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be
defined TARGET_COREBOOT.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
arch/x86/cpu/coreboot/Kconfig | 2 +-
board/coreboot/coreboot/Kconfig | 12 ++++++++----
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 497d6284ac1..b97c2779041 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_COREBOOT
+if VENDOR_COREBOOT
config SYS_COREBOOT
bool
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index 5bd6465d989..05e9b3b6f75 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_COREBOOT
+if VENDOR_COREBOOT
config SYS_BOARD
default "coreboot"
@@ -9,9 +9,6 @@ config SYS_VENDOR
config SYS_SOC
default "coreboot"
-config SYS_CONFIG_NAME
- default "coreboot"
-
config SYS_TEXT_BASE
default 0x01110000
@@ -31,4 +28,11 @@ config SYS_CAR_SIZE
help
This option specifies the board specific Cache-As-RAM (CAR) size.
+endif # CONFIG_VENDOR_COREBOOT
+
+if TARGET_COREBOOT
+
+config SYS_CONFIG_NAME
+ default "coreboot"
+
endif
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 13/16] x86: coreboot: Document the memory map
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (11 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 12/16] x86: coreboot: Use vendor in the Kconfig Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 14/16] x86: cros: Check ROM exists before building vboot Simon Glass
` (3 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Bin Meng, Stefan Reinauer, Vadim Bendebury
Add information about memory usage when U-Boot is started from coreboot.
This is useful when debugging. Also, since coreboot takes a chunk of
memory in the middle of SDRAM for use by PCI devices, it can help avoid
overwriting this with a loaded kernel by accident.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Convert table to reST format
doc/board/coreboot/coreboot.rst | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 9c44c025a48..3792f9e1c8d 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -50,3 +50,24 @@ works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It
can be useful for running UEFI applications, for example.
This has only been lightly tested.
+
+
+Memory map
+----------
+
+ ========== ==================================================================
+ Address Region at that address
+ ========== ==================================================================
+ ffffffff Top of ROM (and last byte of 32-bit address space)
+ 7a9fd000 Typical top of memory available to U-Boot
+ (use cbsysinfo to see where memory range 'table' starts)
+ 10000000 Memory reserved by coreboot for mapping PCI devices
+ (typical size 2151000, includes framebuffer)
+ 1920000 CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup
+ 1110000 CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc)
+ 110000 CONFIG_BLOBLIST_ADDR (before being relocated)
+ 100000 CONFIG_PRE_CON_BUF_ADDR
+ f0000 ACPI tables set up by U-Boot
+ (typically redirects to 7ab10030 or similar)
+ 500 Location of coreboot sysinfo table, used during startup
+ ========== ==================================================================
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 14/16] x86: cros: Check ROM exists before building vboot
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (12 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 13/16] x86: coreboot: Document the memory map Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 15/16] dtoc: Check that a parent is not missing Simon Glass
` (2 subsequent siblings)
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng, Jaehoon Chung
All the x86 devicetree files are built at once, whichever board is
actually being built. If coreboot is the target build, CONFIG_ROM_SIZE
is not defined and samus cannot build Chromium OS verified boot. Add
this condition to avoid errors about CONFIG_ROM_SIZE being missing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
---
(no changes since v2)
Changes in v2:
- Add 'cros' tag since this not a generic x86 change
arch/x86/dts/chromebook_coral.dts | 2 +-
arch/x86/dts/chromebook_samus.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index c8cb4e21c6d..66c31efb6cd 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -10,7 +10,7 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
-#ifdef CONFIG_CHROMEOS_VBOOT
+#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"
#include "flashmap-x86-ro.dtsi"
#include "flashmap-16mb-rw.dtsi"
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index adaeb1ea355..ad35ab2e3fd 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -11,7 +11,7 @@
#include "smbios.dtsi"
-#ifdef CONFIG_CHROMEOS_VBOOT
+#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"
#include "flashmap-x86-ro.dtsi"
#include "flashmap-8mb-rw.dtsi"
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 15/16] dtoc: Check that a parent is not missing
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (13 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 14/16] x86: cros: Check ROM exists before building vboot Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-06-27 23:51 ` [PATCH v3 16/16] doc: Update documentation for cros-2021.04 release Simon Glass
2021-07-14 15:47 ` [PATCH v3 00/16] misc: Some more misc patches Simon Glass
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass
With of-platdata-inst we want to set up a reference to each devices'
parent device, if there is one. If we find that the device has a parent
(i.e. is not a root node) but it is not in the list of devices being
written, then we cannot create the reference.
Report an error in this case, since it indicates that the parent node
is either missing a compatible string, is disabled, or perhaps does not
have any properties because it was not tagged for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v3:
- Fix comment to menion u-boot,dm-tpl
- Fix 'u-boot,dm-pre-tpl' (it should be u-boot,dm-tpl)
tools/dtoc/dtb_platdata.py | 9 ++++++++
tools/dtoc/test/dtoc_test_noparent.dts | 32 ++++++++++++++++++++++++++
tools/dtoc/test_dtoc.py | 10 ++++++++
3 files changed, 51 insertions(+)
create mode 100644 tools/dtoc/test/dtoc_test_noparent.dts
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 2d42480a9a5..869c92b49bf 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -749,6 +749,15 @@ class DtbPlatdata():
break
if node.parent and node.parent.parent:
+ if node.parent not in self._valid_nodes:
+ # This might indicate that the parent node is not in the
+ # SPL/TPL devicetree but the child is. For example if we are
+ # dealing with of-platdata in TPL, the parent has a
+ # u-boot,dm-tpl tag but the child has u-boot,dm-pre-reloc. In
+ # this case the child node exists in TPL but the parent does
+ # not.
+ raise ValueError("Node '%s' requires parent node '%s' but it is not in the valid list" %
+ (node.path, node.parent.path))
self.buf('\t.parent\t\t= DM_DEVICE_REF(%s),\n' %
node.parent.var_name)
if priv_name:
diff --git a/tools/dtoc/test/dtoc_test_noparent.dts b/tools/dtoc/test/dtoc_test_noparent.dts
new file mode 100644
index 00000000000..e976dd2b8af
--- /dev/null
+++ b/tools/dtoc/test/dtoc_test_noparent.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ i2c@0 {
+ compatible = "sandbox,i2c";
+ u-boot,dm-tpl;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spl-test {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pmic@9 {
+ compatible = "sandbox,pmic";
+ u-boot,dm-pre-reloc;
+ reg = <9>;
+ low-power;
+ };
+ };
+ };
+};
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index 0b2805feed2..863ede90b7a 100755
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -1830,3 +1830,13 @@ U_BOOT_DRVINFO(spl_test2) = {
dtb_file = get_dtb_file('dtoc_test_single_reg.dts')
output = tools.GetOutputFilename('output')
self.run_test(['struct'], dtb_file, output)
+
+ def test_missing_parent(self):
+ """Test detection of a parent node with no properties"""
+ dtb_file = get_dtb_file('dtoc_test_noparent.dts', capture_stderr=True)
+ output = tools.GetOutputFilename('output')
+ with self.assertRaises(ValueError) as exc:
+ self.run_test(['device'], dtb_file, output, instantiate=True)
+ self.assertIn("Node '/i2c@0/spl-test/pmic@9' requires parent node "
+ "'/i2c@0/spl-test' but it is not in the valid list",
+ str(exc.exception))
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v3 16/16] doc: Update documentation for cros-2021.04 release
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (14 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 15/16] dtoc: Check that a parent is not missing Simon Glass
@ 2021-06-27 23:51 ` Simon Glass
2021-07-14 15:47 ` [PATCH v3 00/16] misc: Some more misc patches Simon Glass
16 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-06-27 23:51 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Bin Meng
With the new 2021.04 we have a new version of Chromium OS boot, which
supports sandbox, coral and coral-on-coreboot. Add documentation for
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v2)
Changes in v2:
- Drop unnecessary patch 'Enable the cbsysinfo command'
doc/chromium/run_vboot.rst | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/doc/chromium/run_vboot.rst b/doc/chromium/run_vboot.rst
index 41b4f631835..a9e4408d55f 100644
--- a/doc/chromium/run_vboot.rst
+++ b/doc/chromium/run_vboot.rst
@@ -6,11 +6,15 @@
Running U-Boot with Chromium OS verified boot
=============================================
+Note: Once you use the source below you can obtain extra documentation with
+'make htmldocs'. See the 'Internal Documentation' link, under
+'Chromium OS-specific doc'.
+
To obtain::
git clone https://github.com/sjg20/u-boot.git
cd u-boot
- git checkout cros-master
+ git checkout cros-2021.04
cd ..
git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference
@@ -169,7 +173,8 @@ detect problems that affect the flow or particular vboot features.
U-Boot without Chromium OS verified boot
----------------------------------------
-The following script can be used to boot a Chrome OS image on coral::
+The following script can be used to boot a Chrome OS image on coral. It is
+defined as the boot command in mainline::
# Read the image header and obtain the address of the kernel
# The offset 4f0 is defined by verified boot and may change for other
@@ -195,10 +200,4 @@ The following script can be used to boot a Chrome OS image on coral::
zboot go
-TO DO
------
-
-Get the full ACPI tables working with Coral
-
-
7 October 2018
--
2.32.0.93.g670b81a890-goog
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v3 00/16] misc: Some more misc patches
2021-06-27 23:50 [PATCH v3 00/16] misc: Some more misc patches Simon Glass
` (15 preceding siblings ...)
2021-06-27 23:51 ` [PATCH v3 16/16] doc: Update documentation for cros-2021.04 release Simon Glass
@ 2021-07-14 15:47 ` Simon Glass
2021-07-15 11:51 ` Bin Meng
16 siblings, 1 reply; 23+ messages in thread
From: Simon Glass @ 2021-07-14 15:47 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Bin Meng, Jagan Teki, Jagannadha Sutradharudu Teki,
Stefan Reinauer, Vadim Bendebury
Hi Bin,
On Sun, 27 Jun 2021 at 17:51, Simon Glass <sjg@chromium.org> wrote:
>
> Various issues were discovered in getting Chromium OS verified boot
> running on top of coreboot, booting into U-Boot.
>
> Improvements include:
> - enable serial console if even coreboot doesn't
> - enable cache always
> - show the BIOS date since Chromium OS's coreboot doesn't have a version
> - update docs
> - allow SPI driver to work without a PCH
> - fix mtrr command when multi-processing (CONFIG_MP) is disabled
> - add documentation about the memory map
>
> Changes in v3:
> - Fix comment to menion u-boot,dm-tpl
> - Fix 'u-boot,dm-pre-tpl' (it should be u-boot,dm-tpl)
>
> Changes in v2:
> - Add a comment about the cases
> - Reorder declaration and use bios_date for the variable name
> - Add missing newline in the error path
> - Use (ret) instead of (ret != 0) to fit with U-Boot style
> - Convert table to reST format
> - Add 'cros' tag since this not a generic x86 change
> - Drop unnecessary patch 'Enable the cbsysinfo command'
>
> Simon Glass (16):
> pci: Use const for pci_find_device_id() etc.
> x86: pci: Allow binding of some devices before relocation
> x86: Allow coreboot serial driver to guess the UART
> spi: ich: Don't require the PCH
> tpm: cr50: Drop unnecessary coral headers
> x86: Don't set up MTRRs if previously done
> x86: Update the MP constants to avoid conflicts
> x86: Do cache set-up by default when booting from coreboot
> x86: coreboot: Show the BIOS date
> x86: coral: Allow booting from coreboot
> x86: Add function comments to cb_sysinfo.h
> x86: coreboot: Use vendor in the Kconfig
> x86: coreboot: Document the memory map
> x86: cros: Check ROM exists before building vboot
> dtoc: Check that a parent is not missing
> doc: Update documentation for cros-2021.04 release
>
> arch/x86/cpu/coreboot/Kconfig | 2 +-
> arch/x86/cpu/i386/cpu.c | 2 +-
> arch/x86/dts/chromebook_coral.dts | 2 +-
> arch/x86/dts/chromebook_samus.dts | 2 +-
> arch/x86/include/asm/cb_sysinfo.h | 16 ++++++
> arch/x86/include/asm/mp.h | 12 +++--
> arch/x86/lib/init_helpers.c | 18 +++++--
> board/coreboot/coreboot/Kconfig | 12 +++--
> board/coreboot/coreboot/coreboot.c | 3 ++
> board/google/chromebook_coral/coral.c | 28 ++++++++++
> doc/board/coreboot/coreboot.rst | 21 ++++++++
> doc/chromium/run_vboot.rst | 15 +++---
> doc/device-tree-bindings/pci/x86-pci.txt | 7 ++-
> drivers/pci/pci-uclass.c | 39 ++++++++++++--
> drivers/serial/serial_coreboot.c | 68 +++++++++++++++++++++---
> drivers/spi/ich.c | 4 +-
> drivers/tpm/cr50_i2c.c | 2 -
> include/dt-bindings/pci/pci.h | 12 +++++
> include/pci.h | 5 +-
> include/pci_ids.h | 1 +
> tools/dtoc/dtb_platdata.py | 9 ++++
> tools/dtoc/test/dtoc_test_noparent.dts | 32 +++++++++++
> tools/dtoc/test_dtoc.py | 10 ++++
> 23 files changed, 278 insertions(+), 44 deletions(-)
> create mode 100644 include/dt-bindings/pci/pci.h
> create mode 100644 tools/dtoc/test/dtoc_test_noparent.dts
>
> --
> 2.32.0.93.g670b81a890-goog
>
Do you have any update on this series, please?
Thanks,
Simon
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 00/16] misc: Some more misc patches
2021-07-14 15:47 ` [PATCH v3 00/16] misc: Some more misc patches Simon Glass
@ 2021-07-15 11:51 ` Bin Meng
2021-08-01 22:01 ` Simon Glass
0 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2021-07-15 11:51 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Jagan Teki, Jagannadha Sutradharudu Teki,
Stefan Reinauer, Vadim Bendebury
Hi Simon,
On Wed, Jul 14, 2021 at 11:47 PM Simon Glass <sjg@chromium.org> wrote:
>
> Hi Bin,
>
> On Sun, 27 Jun 2021 at 17:51, Simon Glass <sjg@chromium.org> wrote:
> >
> > Various issues were discovered in getting Chromium OS verified boot
> > running on top of coreboot, booting into U-Boot.
> >
> > Improvements include:
> > - enable serial console if even coreboot doesn't
> > - enable cache always
> > - show the BIOS date since Chromium OS's coreboot doesn't have a version
> > - update docs
> > - allow SPI driver to work without a PCH
> > - fix mtrr command when multi-processing (CONFIG_MP) is disabled
> > - add documentation about the memory map
> >
> > Changes in v3:
> > - Fix comment to menion u-boot,dm-tpl
> > - Fix 'u-boot,dm-pre-tpl' (it should be u-boot,dm-tpl)
> >
> > Changes in v2:
> > - Add a comment about the cases
> > - Reorder declaration and use bios_date for the variable name
> > - Add missing newline in the error path
> > - Use (ret) instead of (ret != 0) to fit with U-Boot style
> > - Convert table to reST format
> > - Add 'cros' tag since this not a generic x86 change
> > - Drop unnecessary patch 'Enable the cbsysinfo command'
> >
> > Simon Glass (16):
> > pci: Use const for pci_find_device_id() etc.
> > x86: pci: Allow binding of some devices before relocation
> > x86: Allow coreboot serial driver to guess the UART
> > spi: ich: Don't require the PCH
> > tpm: cr50: Drop unnecessary coral headers
> > x86: Don't set up MTRRs if previously done
> > x86: Update the MP constants to avoid conflicts
> > x86: Do cache set-up by default when booting from coreboot
> > x86: coreboot: Show the BIOS date
> > x86: coral: Allow booting from coreboot
> > x86: Add function comments to cb_sysinfo.h
> > x86: coreboot: Use vendor in the Kconfig
> > x86: coreboot: Document the memory map
> > x86: cros: Check ROM exists before building vboot
> > dtoc: Check that a parent is not missing
> > doc: Update documentation for cros-2021.04 release
> >
> > arch/x86/cpu/coreboot/Kconfig | 2 +-
> > arch/x86/cpu/i386/cpu.c | 2 +-
> > arch/x86/dts/chromebook_coral.dts | 2 +-
> > arch/x86/dts/chromebook_samus.dts | 2 +-
> > arch/x86/include/asm/cb_sysinfo.h | 16 ++++++
> > arch/x86/include/asm/mp.h | 12 +++--
> > arch/x86/lib/init_helpers.c | 18 +++++--
> > board/coreboot/coreboot/Kconfig | 12 +++--
> > board/coreboot/coreboot/coreboot.c | 3 ++
> > board/google/chromebook_coral/coral.c | 28 ++++++++++
> > doc/board/coreboot/coreboot.rst | 21 ++++++++
> > doc/chromium/run_vboot.rst | 15 +++---
> > doc/device-tree-bindings/pci/x86-pci.txt | 7 ++-
> > drivers/pci/pci-uclass.c | 39 ++++++++++++--
> > drivers/serial/serial_coreboot.c | 68 +++++++++++++++++++++---
> > drivers/spi/ich.c | 4 +-
> > drivers/tpm/cr50_i2c.c | 2 -
> > include/dt-bindings/pci/pci.h | 12 +++++
> > include/pci.h | 5 +-
> > include/pci_ids.h | 1 +
> > tools/dtoc/dtb_platdata.py | 9 ++++
> > tools/dtoc/test/dtoc_test_noparent.dts | 32 +++++++++++
> > tools/dtoc/test_dtoc.py | 10 ++++
> > 23 files changed, 278 insertions(+), 44 deletions(-)
> > create mode 100644 include/dt-bindings/pci/pci.h
> > create mode 100644 tools/dtoc/test/dtoc_test_noparent.dts
> >
> > --
> > 2.32.0.93.g670b81a890-goog
> >
>
> Do you have any update on this series, please?
>
Sorry, I just applied this series.
There are many commits that have a blank line between your SoB tag and
the RB tag which I believe is caused by the patman patchwork
functionality.
I have manually removed the blank lines when applying. Would you
please fix the patman?
Regards,
Bin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 00/16] misc: Some more misc patches
2021-07-15 11:51 ` Bin Meng
@ 2021-08-01 22:01 ` Simon Glass
0 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2021-08-01 22:01 UTC (permalink / raw)
To: Bin Meng
Cc: U-Boot Mailing List, Jagan Teki, Jagannadha Sutradharudu Teki,
Stefan Reinauer, Vadim Bendebury
Hi Bin,
On Thu, 15 Jul 2021 at 05:51, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, Jul 14, 2021 at 11:47 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > Hi Bin,
> >
> > On Sun, 27 Jun 2021 at 17:51, Simon Glass <sjg@chromium.org> wrote:
> > >
> > > Various issues were discovered in getting Chromium OS verified boot
> > > running on top of coreboot, booting into U-Boot.
> > >
> > > Improvements include:
> > > - enable serial console if even coreboot doesn't
> > > - enable cache always
> > > - show the BIOS date since Chromium OS's coreboot doesn't have a version
> > > - update docs
> > > - allow SPI driver to work without a PCH
> > > - fix mtrr command when multi-processing (CONFIG_MP) is disabled
> > > - add documentation about the memory map
> > >
> > > Changes in v3:
> > > - Fix comment to menion u-boot,dm-tpl
> > > - Fix 'u-boot,dm-pre-tpl' (it should be u-boot,dm-tpl)
> > >
> > > Changes in v2:
> > > - Add a comment about the cases
> > > - Reorder declaration and use bios_date for the variable name
> > > - Add missing newline in the error path
> > > - Use (ret) instead of (ret != 0) to fit with U-Boot style
> > > - Convert table to reST format
> > > - Add 'cros' tag since this not a generic x86 change
> > > - Drop unnecessary patch 'Enable the cbsysinfo command'
> > >
> > > Simon Glass (16):
> > > pci: Use const for pci_find_device_id() etc.
> > > x86: pci: Allow binding of some devices before relocation
> > > x86: Allow coreboot serial driver to guess the UART
> > > spi: ich: Don't require the PCH
> > > tpm: cr50: Drop unnecessary coral headers
> > > x86: Don't set up MTRRs if previously done
> > > x86: Update the MP constants to avoid conflicts
> > > x86: Do cache set-up by default when booting from coreboot
> > > x86: coreboot: Show the BIOS date
> > > x86: coral: Allow booting from coreboot
> > > x86: Add function comments to cb_sysinfo.h
> > > x86: coreboot: Use vendor in the Kconfig
> > > x86: coreboot: Document the memory map
> > > x86: cros: Check ROM exists before building vboot
> > > dtoc: Check that a parent is not missing
> > > doc: Update documentation for cros-2021.04 release
> > >
> > > arch/x86/cpu/coreboot/Kconfig | 2 +-
> > > arch/x86/cpu/i386/cpu.c | 2 +-
> > > arch/x86/dts/chromebook_coral.dts | 2 +-
> > > arch/x86/dts/chromebook_samus.dts | 2 +-
> > > arch/x86/include/asm/cb_sysinfo.h | 16 ++++++
> > > arch/x86/include/asm/mp.h | 12 +++--
> > > arch/x86/lib/init_helpers.c | 18 +++++--
> > > board/coreboot/coreboot/Kconfig | 12 +++--
> > > board/coreboot/coreboot/coreboot.c | 3 ++
> > > board/google/chromebook_coral/coral.c | 28 ++++++++++
> > > doc/board/coreboot/coreboot.rst | 21 ++++++++
> > > doc/chromium/run_vboot.rst | 15 +++---
> > > doc/device-tree-bindings/pci/x86-pci.txt | 7 ++-
> > > drivers/pci/pci-uclass.c | 39 ++++++++++++--
> > > drivers/serial/serial_coreboot.c | 68 +++++++++++++++++++++---
> > > drivers/spi/ich.c | 4 +-
> > > drivers/tpm/cr50_i2c.c | 2 -
> > > include/dt-bindings/pci/pci.h | 12 +++++
> > > include/pci.h | 5 +-
> > > include/pci_ids.h | 1 +
> > > tools/dtoc/dtb_platdata.py | 9 ++++
> > > tools/dtoc/test/dtoc_test_noparent.dts | 32 +++++++++++
> > > tools/dtoc/test_dtoc.py | 10 ++++
> > > 23 files changed, 278 insertions(+), 44 deletions(-)
> > > create mode 100644 include/dt-bindings/pci/pci.h
> > > create mode 100644 tools/dtoc/test/dtoc_test_noparent.dts
> > >
> > > --
> > > 2.32.0.93.g670b81a890-goog
> > >
> >
> > Do you have any update on this series, please?
> >
>
> Sorry, I just applied this series.
>
> There are many commits that have a blank line between your SoB tag and
> the RB tag which I believe is caused by the patman patchwork
> functionality.
>
> I have manually removed the blank lines when applying. Would you
> please fix the patman?
I think it might have been due to using an old patman to do that
series. But I'm not sure, so I'll send a possible fix.
Regards,
Simon
^ permalink raw reply [flat|nested] 23+ messages in thread