From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, anshuman.khandual@arm.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Date: Wed, 28 Jul 2021 14:52:11 +0100 [thread overview] Message-ID: <20210728135217.591173-5-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210728135217.591173-1-suzuki.poulose@arm.com> We always set the TRBBASER_EL1 to the base of the virtual ring buffer. We are about to change this for working around an erratum. So, in preparation to that, allow the driver to choose a different base for the TRBBASER_EL1 (which is within the buffer range). Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 0af644331b99..9735d514c5e1 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -59,6 +59,8 @@ struct trbe_buf { * trbe_limit sibling pointers. */ unsigned long trbe_base; + /* The base programmed into the TRBE */ + unsigned long trbe_hw_base; unsigned long trbe_limit; unsigned long trbe_write; int nr_pages; @@ -504,7 +506,7 @@ static void trbe_enable_hw(struct trbe_buf *buf) set_trbe_disabled(); isb(); clr_trbe_status(); - set_trbe_base_pointer(buf->trbe_base); + set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); /* @@ -709,6 +711,8 @@ static int __arm_trbe_enable(struct trbe_buf *buf, trbe_stop_and_truncate_event(handle); return -ENOSPC; } + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base = buf->trbe_base; *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle; trbe_enable_hw(buf); return 0; @@ -808,7 +812,7 @@ static bool is_perf_trbe(struct perf_output_handle *handle) struct trbe_drvdata *drvdata = cpudata->drvdata; int cpu = smp_processor_id(); - WARN_ON(buf->trbe_base != get_trbe_base_pointer()); + WARN_ON(buf->trbe_hw_base != get_trbe_base_pointer()); WARN_ON(buf->trbe_limit != get_trbe_limit_pointer()); if (cpudata->mode != CS_MODE_PERF) -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, anshuman.khandual@arm.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Date: Wed, 28 Jul 2021 14:52:11 +0100 [thread overview] Message-ID: <20210728135217.591173-5-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210728135217.591173-1-suzuki.poulose@arm.com> We always set the TRBBASER_EL1 to the base of the virtual ring buffer. We are about to change this for working around an erratum. So, in preparation to that, allow the driver to choose a different base for the TRBBASER_EL1 (which is within the buffer range). Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 0af644331b99..9735d514c5e1 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -59,6 +59,8 @@ struct trbe_buf { * trbe_limit sibling pointers. */ unsigned long trbe_base; + /* The base programmed into the TRBE */ + unsigned long trbe_hw_base; unsigned long trbe_limit; unsigned long trbe_write; int nr_pages; @@ -504,7 +506,7 @@ static void trbe_enable_hw(struct trbe_buf *buf) set_trbe_disabled(); isb(); clr_trbe_status(); - set_trbe_base_pointer(buf->trbe_base); + set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); /* @@ -709,6 +711,8 @@ static int __arm_trbe_enable(struct trbe_buf *buf, trbe_stop_and_truncate_event(handle); return -ENOSPC; } + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base = buf->trbe_base; *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle; trbe_enable_hw(buf); return 0; @@ -808,7 +812,7 @@ static bool is_perf_trbe(struct perf_output_handle *handle) struct trbe_drvdata *drvdata = cpudata->drvdata; int cpu = smp_processor_id(); - WARN_ON(buf->trbe_base != get_trbe_base_pointer()); + WARN_ON(buf->trbe_hw_base != get_trbe_base_pointer()); WARN_ON(buf->trbe_limit != get_trbe_limit_pointer()); if (cpudata->mode != CS_MODE_PERF) -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-28 13:53 UTC|newest] Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-02 6:43 ` Anshuman Khandual 2021-08-02 6:43 ` Anshuman Khandual 2021-09-07 9:04 ` Suzuki K Poulose 2021-09-07 9:04 ` Suzuki K Poulose 2021-09-09 2:55 ` Anshuman Khandual 2021-09-09 2:55 ` Anshuman Khandual 2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 10:01 ` Anshuman Khandual 2021-07-30 10:01 ` Anshuman Khandual 2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 10:05 ` Anshuman Khandual 2021-07-30 10:05 ` Anshuman Khandual 2021-07-28 13:52 ` Suzuki K Poulose [this message] 2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-07-30 10:53 ` Anshuman Khandual 2021-07-30 10:53 ` Anshuman Khandual 2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 11:02 ` Anshuman Khandual 2021-07-30 11:02 ` Anshuman Khandual 2021-07-30 14:29 ` Suzuki K Poulose 2021-07-30 14:29 ` Suzuki K Poulose 2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 11:26 ` Anshuman Khandual 2021-07-30 11:26 ` Anshuman Khandual 2021-07-30 14:31 ` Suzuki K Poulose 2021-07-30 14:31 ` Suzuki K Poulose 2021-08-02 11:21 ` Catalin Marinas 2021-08-02 11:21 ` Catalin Marinas 2021-08-02 11:21 ` Catalin Marinas 2021-08-02 11:21 ` Catalin Marinas 2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-02 7:44 ` Anshuman Khandual 2021-08-02 7:44 ` Anshuman Khandual 2021-08-02 11:22 ` Catalin Marinas 2021-08-02 11:22 ` Catalin Marinas 2021-08-06 12:44 ` Linu Cherian 2021-08-06 12:44 ` Linu Cherian 2021-09-07 9:10 ` Suzuki K Poulose 2021-09-07 9:10 ` Suzuki K Poulose 2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-03 10:25 ` Anshuman Khandual 2021-08-03 10:25 ` Anshuman Khandual 2021-09-07 9:58 ` Suzuki K Poulose 2021-09-07 9:58 ` Suzuki K Poulose 2021-09-09 4:21 ` Anshuman Khandual 2021-09-09 4:21 ` Anshuman Khandual 2021-09-09 8:37 ` Suzuki K Poulose 2021-09-09 8:37 ` Suzuki K Poulose 2021-08-06 16:09 ` Linu Cherian 2021-08-06 16:09 ` Linu Cherian 2021-09-07 9:18 ` Suzuki K Poulose 2021-09-07 9:18 ` Suzuki K Poulose 2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-02 9:34 ` Anshuman Khandual 2021-08-02 9:34 ` Anshuman Khandual 2021-08-02 11:24 ` Catalin Marinas 2021-08-02 11:24 ` Catalin Marinas 2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-29 9:55 ` Marc Zyngier 2021-07-29 9:55 ` Marc Zyngier 2021-07-29 10:41 ` Suzuki K Poulose 2021-07-29 10:41 ` Suzuki K Poulose 2021-08-02 9:12 ` Anshuman Khandual 2021-08-02 9:12 ` Anshuman Khandual 2021-08-02 9:35 ` Marc Zyngier 2021-08-02 9:35 ` Marc Zyngier 2021-08-03 3:51 ` Anshuman Khandual 2021-08-03 3:51 ` Anshuman Khandual 2021-09-08 13:39 ` Suzuki K Poulose 2021-09-08 13:39 ` Suzuki K Poulose 2021-08-02 11:27 ` Catalin Marinas 2021-08-02 11:27 ` Catalin Marinas
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