From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, anshuman.khandual@arm.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Date: Wed, 28 Jul 2021 14:52:13 +0100 [thread overview] Message-ID: <20210728135217.591173-7-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210728135217.591173-1-suzuki.poulose@arm.com> Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 6231e1f0abe7..b71bd6c176c2 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,8 @@ #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define APM_CPU_PART_POTENZA 0x000 @@ -112,6 +114,8 @@ #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) +#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, anshuman.khandual@arm.com, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Date: Wed, 28 Jul 2021 14:52:13 +0100 [thread overview] Message-ID: <20210728135217.591173-7-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210728135217.591173-1-suzuki.poulose@arm.com> Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 6231e1f0abe7..b71bd6c176c2 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,8 @@ #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define APM_CPU_PART_POTENZA 0x000 @@ -112,6 +114,8 @@ #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) +#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-28 13:54 UTC|newest] Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-02 6:43 ` Anshuman Khandual 2021-08-02 6:43 ` Anshuman Khandual 2021-09-07 9:04 ` Suzuki K Poulose 2021-09-07 9:04 ` Suzuki K Poulose 2021-09-09 2:55 ` Anshuman Khandual 2021-09-09 2:55 ` Anshuman Khandual 2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 10:01 ` Anshuman Khandual 2021-07-30 10:01 ` Anshuman Khandual 2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 10:05 ` Anshuman Khandual 2021-07-30 10:05 ` Anshuman Khandual 2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 10:53 ` Anshuman Khandual 2021-07-30 10:53 ` Anshuman Khandual 2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-30 11:02 ` Anshuman Khandual 2021-07-30 11:02 ` Anshuman Khandual 2021-07-30 14:29 ` Suzuki K Poulose 2021-07-30 14:29 ` Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose [this message] 2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-07-30 11:26 ` Anshuman Khandual 2021-07-30 11:26 ` Anshuman Khandual 2021-07-30 14:31 ` Suzuki K Poulose 2021-07-30 14:31 ` Suzuki K Poulose 2021-08-02 11:21 ` Catalin Marinas 2021-08-02 11:21 ` Catalin Marinas 2021-08-02 11:21 ` Catalin Marinas 2021-08-02 11:21 ` Catalin Marinas 2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-02 7:44 ` Anshuman Khandual 2021-08-02 7:44 ` Anshuman Khandual 2021-08-02 11:22 ` Catalin Marinas 2021-08-02 11:22 ` Catalin Marinas 2021-08-06 12:44 ` Linu Cherian 2021-08-06 12:44 ` Linu Cherian 2021-09-07 9:10 ` Suzuki K Poulose 2021-09-07 9:10 ` Suzuki K Poulose 2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-03 10:25 ` Anshuman Khandual 2021-08-03 10:25 ` Anshuman Khandual 2021-09-07 9:58 ` Suzuki K Poulose 2021-09-07 9:58 ` Suzuki K Poulose 2021-09-09 4:21 ` Anshuman Khandual 2021-09-09 4:21 ` Anshuman Khandual 2021-09-09 8:37 ` Suzuki K Poulose 2021-09-09 8:37 ` Suzuki K Poulose 2021-08-06 16:09 ` Linu Cherian 2021-08-06 16:09 ` Linu Cherian 2021-09-07 9:18 ` Suzuki K Poulose 2021-09-07 9:18 ` Suzuki K Poulose 2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-08-02 9:34 ` Anshuman Khandual 2021-08-02 9:34 ` Anshuman Khandual 2021-08-02 11:24 ` Catalin Marinas 2021-08-02 11:24 ` Catalin Marinas 2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-07-28 13:52 ` Suzuki K Poulose 2021-07-29 9:55 ` Marc Zyngier 2021-07-29 9:55 ` Marc Zyngier 2021-07-29 10:41 ` Suzuki K Poulose 2021-07-29 10:41 ` Suzuki K Poulose 2021-08-02 9:12 ` Anshuman Khandual 2021-08-02 9:12 ` Anshuman Khandual 2021-08-02 9:35 ` Marc Zyngier 2021-08-02 9:35 ` Marc Zyngier 2021-08-03 3:51 ` Anshuman Khandual 2021-08-03 3:51 ` Anshuman Khandual 2021-09-08 13:39 ` Suzuki K Poulose 2021-09-08 13:39 ` Suzuki K Poulose 2021-08-02 11:27 ` Catalin Marinas 2021-08-02 11:27 ` Catalin Marinas
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