From: Catalin Marinas <catalin.marinas@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
anshuman.khandual@arm.com, will@kernel.org, james.morse@arm.com,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures
Date: Mon, 2 Aug 2021 12:27:12 +0100 [thread overview]
Message-ID: <20210802112712.GE18685@arm.com> (raw)
In-Reply-To: <20210728135217.591173-11-suzuki.poulose@arm.com>
On Wed, Jul 28, 2021 at 02:52:17PM +0100, Suzuki K Poulose wrote:
> Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers
> from errata, where a TSB (trace synchronization barrier)
> fails to flush the trace data completely, when executed from
> a trace prohibited region. In Linux we always execute it
> after we have moved the PE to trace prohibited region. So,
> we can apply the workaround everytime a TSB is executed.
>
> The work around is to issue two TSB consecutively.
>
> NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying
> that a late CPU could be blocked from booting if it is the
> first CPU that requires the workaround. This is because we
> do not allow setting a cpu_hwcaps after the SMP boot. The
> other alternative is to use "this_cpu_has_cap()" instead
> of the faster system wide check, which may be a bit of an
> overhead, given we may have to do this in nvhe KVM host
> before a guest entry.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
With Marc's comments addressed:
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
anshuman.khandual@arm.com, will@kernel.org, james.morse@arm.com,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures
Date: Mon, 2 Aug 2021 12:27:12 +0100 [thread overview]
Message-ID: <20210802112712.GE18685@arm.com> (raw)
In-Reply-To: <20210728135217.591173-11-suzuki.poulose@arm.com>
On Wed, Jul 28, 2021 at 02:52:17PM +0100, Suzuki K Poulose wrote:
> Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers
> from errata, where a TSB (trace synchronization barrier)
> fails to flush the trace data completely, when executed from
> a trace prohibited region. In Linux we always execute it
> after we have moved the PE to trace prohibited region. So,
> we can apply the workaround everytime a TSB is executed.
>
> The work around is to issue two TSB consecutively.
>
> NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying
> that a late CPU could be blocked from booting if it is the
> first CPU that requires the workaround. This is because we
> do not allow setting a cpu_hwcaps after the SMP boot. The
> other alternative is to use "this_cpu_has_cap()" instead
> of the faster system wide check, which may be a bit of an
> overhead, given we may have to do this in nvhe KVM host
> before a guest entry.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
With Marc's comments addressed:
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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next prev parent reply other threads:[~2021-08-02 11:27 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-08-02 6:43 ` Anshuman Khandual
2021-08-02 6:43 ` Anshuman Khandual
2021-09-07 9:04 ` Suzuki K Poulose
2021-09-07 9:04 ` Suzuki K Poulose
2021-09-09 2:55 ` Anshuman Khandual
2021-09-09 2:55 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-30 10:01 ` Anshuman Khandual
2021-07-30 10:01 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-30 10:05 ` Anshuman Khandual
2021-07-30 10:05 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-30 10:53 ` Anshuman Khandual
2021-07-30 10:53 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-30 11:02 ` Anshuman Khandual
2021-07-30 11:02 ` Anshuman Khandual
2021-07-30 14:29 ` Suzuki K Poulose
2021-07-30 14:29 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-30 11:26 ` Anshuman Khandual
2021-07-30 11:26 ` Anshuman Khandual
2021-07-30 14:31 ` Suzuki K Poulose
2021-07-30 14:31 ` Suzuki K Poulose
2021-08-02 11:21 ` Catalin Marinas
2021-08-02 11:21 ` Catalin Marinas
2021-08-02 11:21 ` Catalin Marinas
2021-08-02 11:21 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-08-02 7:44 ` Anshuman Khandual
2021-08-02 7:44 ` Anshuman Khandual
2021-08-02 11:22 ` Catalin Marinas
2021-08-02 11:22 ` Catalin Marinas
2021-08-06 12:44 ` Linu Cherian
2021-08-06 12:44 ` Linu Cherian
2021-09-07 9:10 ` Suzuki K Poulose
2021-09-07 9:10 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-08-03 10:25 ` Anshuman Khandual
2021-08-03 10:25 ` Anshuman Khandual
2021-09-07 9:58 ` Suzuki K Poulose
2021-09-07 9:58 ` Suzuki K Poulose
2021-09-09 4:21 ` Anshuman Khandual
2021-09-09 4:21 ` Anshuman Khandual
2021-09-09 8:37 ` Suzuki K Poulose
2021-09-09 8:37 ` Suzuki K Poulose
2021-08-06 16:09 ` Linu Cherian
2021-08-06 16:09 ` Linu Cherian
2021-09-07 9:18 ` Suzuki K Poulose
2021-09-07 9:18 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-08-02 9:34 ` Anshuman Khandual
2021-08-02 9:34 ` Anshuman Khandual
2021-08-02 11:24 ` Catalin Marinas
2021-08-02 11:24 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-29 9:55 ` Marc Zyngier
2021-07-29 9:55 ` Marc Zyngier
2021-07-29 10:41 ` Suzuki K Poulose
2021-07-29 10:41 ` Suzuki K Poulose
2021-08-02 9:12 ` Anshuman Khandual
2021-08-02 9:12 ` Anshuman Khandual
2021-08-02 9:35 ` Marc Zyngier
2021-08-02 9:35 ` Marc Zyngier
2021-08-03 3:51 ` Anshuman Khandual
2021-08-03 3:51 ` Anshuman Khandual
2021-09-08 13:39 ` Suzuki K Poulose
2021-09-08 13:39 ` Suzuki K Poulose
2021-08-02 11:27 ` Catalin Marinas [this message]
2021-08-02 11:27 ` Catalin Marinas
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