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From: Marc Zyngier <maz@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	leo.yan@linaro.org, mark.rutland@arm.com
Subject: Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures
Date: Mon, 02 Aug 2021 10:35:12 +0100	[thread overview]
Message-ID: <32f719c8f9f61b244b3fc29137f76a19@kernel.org> (raw)
In-Reply-To: <477c4943-7c35-8502-0291-4c0ed3a03905@arm.com>

On 2021-08-02 10:12, Anshuman Khandual wrote:
> On 7/29/21 4:11 PM, Suzuki K Poulose wrote:
>> On 29/07/2021 10:55, Marc Zyngier wrote:
>>> On Wed, 28 Jul 2021 14:52:17 +0100,
>>> Suzuki K Poulose <suzuki.poulose@arm.com>

[...]

>>>> +            __tsb_csync();                        \
>>>> +            __tsb_csync();                        \
>>>> +        } else {                            \
>>>> +            __tsb_csync();                        \
>>>> +        }                                \
>>> 
>>> nit: You could keep one unconditional __tsb_csync().
>> 
>> I thought about that, I was worried if the CPU expects them back to 
>> back
>> without any other instructions in between them. Thinking about it a 
>> bit
>> more, it doesn't look like that is the case. I will confirm this and
>> change it accordingly.
> But its a very subtle change which might be difficult to debug and 
> blame
> later on, if indeed both the instructions need to be back to back. 
> Seems
> like just better to leave this unchanged.

Is that an actual requirement? Sounds like you want to find out
from the errata document.

And if they actually need to be back to back, what ensures that
this is always called with interrupt disabled?

You would also need to have them in the same asm block to avoid
the compiler reordering stuff.

         M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	leo.yan@linaro.org, mark.rutland@arm.com
Subject: Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures
Date: Mon, 02 Aug 2021 10:35:12 +0100	[thread overview]
Message-ID: <32f719c8f9f61b244b3fc29137f76a19@kernel.org> (raw)
In-Reply-To: <477c4943-7c35-8502-0291-4c0ed3a03905@arm.com>

On 2021-08-02 10:12, Anshuman Khandual wrote:
> On 7/29/21 4:11 PM, Suzuki K Poulose wrote:
>> On 29/07/2021 10:55, Marc Zyngier wrote:
>>> On Wed, 28 Jul 2021 14:52:17 +0100,
>>> Suzuki K Poulose <suzuki.poulose@arm.com>

[...]

>>>> +            __tsb_csync();                        \
>>>> +            __tsb_csync();                        \
>>>> +        } else {                            \
>>>> +            __tsb_csync();                        \
>>>> +        }                                \
>>> 
>>> nit: You could keep one unconditional __tsb_csync().
>> 
>> I thought about that, I was worried if the CPU expects them back to 
>> back
>> without any other instructions in between them. Thinking about it a 
>> bit
>> more, it doesn't look like that is the case. I will confirm this and
>> change it accordingly.
> But its a very subtle change which might be difficult to debug and 
> blame
> later on, if indeed both the instructions need to be back to back. 
> Seems
> like just better to leave this unchanged.

Is that an actual requirement? Sounds like you want to find out
from the errata document.

And if they actually need to be back to back, what ensures that
this is always called with interrupt disabled?

You would also need to have them in the same asm block to avoid
the compiler reordering stuff.

         M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-08-02  9:35 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-02  6:43   ` Anshuman Khandual
2021-08-02  6:43     ` Anshuman Khandual
2021-09-07  9:04     ` Suzuki K Poulose
2021-09-07  9:04       ` Suzuki K Poulose
2021-09-09  2:55       ` Anshuman Khandual
2021-09-09  2:55         ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 10:01   ` Anshuman Khandual
2021-07-30 10:01     ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 10:05   ` Anshuman Khandual
2021-07-30 10:05     ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 10:53   ` Anshuman Khandual
2021-07-30 10:53     ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 11:02   ` Anshuman Khandual
2021-07-30 11:02     ` Anshuman Khandual
2021-07-30 14:29     ` Suzuki K Poulose
2021-07-30 14:29       ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-30 11:26   ` Anshuman Khandual
2021-07-30 11:26     ` Anshuman Khandual
2021-07-30 14:31     ` Suzuki K Poulose
2021-07-30 14:31       ` Suzuki K Poulose
2021-08-02 11:21   ` Catalin Marinas
2021-08-02 11:21     ` Catalin Marinas
2021-08-02 11:21   ` Catalin Marinas
2021-08-02 11:21     ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-02  7:44   ` Anshuman Khandual
2021-08-02  7:44     ` Anshuman Khandual
2021-08-02 11:22   ` Catalin Marinas
2021-08-02 11:22     ` Catalin Marinas
2021-08-06 12:44   ` Linu Cherian
2021-08-06 12:44     ` Linu Cherian
2021-09-07  9:10     ` Suzuki K Poulose
2021-09-07  9:10       ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-03 10:25   ` Anshuman Khandual
2021-08-03 10:25     ` Anshuman Khandual
2021-09-07  9:58     ` Suzuki K Poulose
2021-09-07  9:58       ` Suzuki K Poulose
2021-09-09  4:21       ` Anshuman Khandual
2021-09-09  4:21         ` Anshuman Khandual
2021-09-09  8:37         ` Suzuki K Poulose
2021-09-09  8:37           ` Suzuki K Poulose
2021-08-06 16:09   ` Linu Cherian
2021-08-06 16:09     ` Linu Cherian
2021-09-07  9:18     ` Suzuki K Poulose
2021-09-07  9:18       ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-08-02  9:34   ` Anshuman Khandual
2021-08-02  9:34     ` Anshuman Khandual
2021-08-02 11:24   ` Catalin Marinas
2021-08-02 11:24     ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-07-28 13:52   ` Suzuki K Poulose
2021-07-29  9:55   ` Marc Zyngier
2021-07-29  9:55     ` Marc Zyngier
2021-07-29 10:41     ` Suzuki K Poulose
2021-07-29 10:41       ` Suzuki K Poulose
2021-08-02  9:12       ` Anshuman Khandual
2021-08-02  9:12         ` Anshuman Khandual
2021-08-02  9:35         ` Marc Zyngier [this message]
2021-08-02  9:35           ` Marc Zyngier
2021-08-03  3:51           ` Anshuman Khandual
2021-08-03  3:51             ` Anshuman Khandual
2021-09-08 13:39             ` Suzuki K Poulose
2021-09-08 13:39               ` Suzuki K Poulose
2021-08-02 11:27   ` Catalin Marinas
2021-08-02 11:27     ` Catalin Marinas

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