From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 12/13] target/riscv: Don't save pc when exception return Date: Mon, 1 Nov 2021 18:01:42 +0800 [thread overview] Message-ID: <20211101100143.44356-13-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20211101100143.44356-1-zhiwei_liu@c-sky.com> As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- target/riscv/op_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9b379d7232..34c57a6083 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_2(sret, tl, env, tl) -DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(sret, tl, env) +DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(switch_context_xl, void, env) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 6e39632f83..cf6dc98888 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - if (has_ext(ctx, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + gen_helper_sret(cpu_pc, cpu_env); gen_helper_switch_context_xl(cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; @@ -93,8 +91,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + gen_helper_mret(cpu_pc, cpu_env); gen_helper_switch_context_xl(cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 20cf8ad883..3ce2767ccf 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -97,7 +97,7 @@ void helper_switch_context_xl(CPURISCVState *env) } } -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; target_ulong prev_priv, prev_virt; @@ -158,7 +158,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) return retpc; } -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_mret(CPURISCVState *env) { if (!(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 12/13] target/riscv: Don't save pc when exception return Date: Mon, 1 Nov 2021 18:01:42 +0800 [thread overview] Message-ID: <20211101100143.44356-13-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20211101100143.44356-1-zhiwei_liu@c-sky.com> As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 4 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- target/riscv/op_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9b379d7232..34c57a6083 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) DEF_HELPER_4(csrrw, tl, env, int, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_2(sret, tl, env, tl) -DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(sret, tl, env) +DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(switch_context_xl, void, env) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 6e39632f83..cf6dc98888 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - if (has_ext(ctx, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + gen_helper_sret(cpu_pc, cpu_env); gen_helper_switch_context_xl(cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; @@ -93,8 +91,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + gen_helper_mret(cpu_pc, cpu_env); gen_helper_switch_context_xl(cpu_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 20cf8ad883..3ce2767ccf 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -97,7 +97,7 @@ void helper_switch_context_xl(CPURISCVState *env) } } -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; target_ulong prev_priv, prev_virt; @@ -158,7 +158,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) return retpc; } -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) +target_ulong helper_mret(CPURISCVState *env) { if (!(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); -- 2.25.1
next prev parent reply other threads:[~2021-11-01 10:21 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:29 ` Richard Henderson 2021-11-01 10:29 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:33 ` Richard Henderson 2021-11-01 10:33 ` Richard Henderson 2021-11-02 1:48 ` LIU Zhiwei 2021-11-02 1:48 ` LIU Zhiwei 2021-11-02 10:18 ` Richard Henderson 2021-11-02 10:18 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:35 ` Richard Henderson 2021-11-01 10:35 ` Richard Henderson 2021-11-02 10:20 ` Richard Henderson 2021-11-02 10:20 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:40 ` Richard Henderson 2021-11-01 10:40 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:46 ` Richard Henderson 2021-11-01 10:46 ` Richard Henderson 2021-11-01 15:56 ` LIU Zhiwei 2021-11-01 15:56 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:53 ` Richard Henderson 2021-11-01 10:53 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:55 ` Richard Henderson 2021-11-01 10:55 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 13:41 ` Richard Henderson 2021-11-01 13:41 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 11:35 ` Richard Henderson 2021-11-01 11:35 ` Richard Henderson 2021-11-08 9:28 ` LIU Zhiwei 2021-11-08 9:28 ` LIU Zhiwei 2021-11-09 6:37 ` Richard Henderson 2021-11-09 6:37 ` Richard Henderson 2021-11-09 8:04 ` LIU Zhiwei 2021-11-09 8:04 ` LIU Zhiwei 2021-11-09 8:18 ` Richard Henderson 2021-11-09 8:18 ` Richard Henderson 2021-11-09 8:39 ` LIU Zhiwei 2021-11-09 8:39 ` LIU Zhiwei 2021-11-09 9:05 ` LIU Zhiwei 2021-11-09 9:05 ` LIU Zhiwei 2021-11-09 9:25 ` Richard Henderson 2021-11-09 9:25 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:33 ` Richard Henderson 2021-11-01 16:33 ` Richard Henderson 2021-11-08 9:38 ` LIU Zhiwei 2021-11-08 9:38 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:43 ` Richard Henderson 2021-11-01 16:43 ` Richard Henderson 2021-11-08 11:23 ` LIU Zhiwei 2021-11-08 11:23 ` LIU Zhiwei 2021-11-09 6:38 ` LIU Zhiwei 2021-11-09 6:38 ` LIU Zhiwei 2021-11-09 6:51 ` LIU Zhiwei 2021-11-09 6:51 ` LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei [this message] 2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei 2021-11-01 16:49 ` Richard Henderson 2021-11-01 16:49 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 17:01 ` Richard Henderson 2021-11-01 17:01 ` Richard Henderson 2021-11-08 12:10 ` LIU Zhiwei 2021-11-08 12:10 ` LIU Zhiwei 2021-11-10 3:01 ` LIU Zhiwei 2021-11-10 3:01 ` LIU Zhiwei
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