From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN Date: Mon, 1 Nov 2021 18:01:33 +0800 [thread overview] Message-ID: <20211101100143.44356-4-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20211101100143.44356-1-zhiwei_liu@c-sky.com> The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7d0aee6769..eb425d74d2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,7 +71,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, { uint32_t flags = 0; - *pc = env->pc; + *pc = cpu_get_xl(env) == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; if (riscv_has_ext(env, RVV)) { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN Date: Mon, 1 Nov 2021 18:01:33 +0800 [thread overview] Message-ID: <20211101100143.44356-4-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20211101100143.44356-1-zhiwei_liu@c-sky.com> The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7d0aee6769..eb425d74d2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,7 +71,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, { uint32_t flags = 0; - *pc = env->pc; + *pc = cpu_get_xl(env) == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; if (riscv_has_ext(env, RVV)) { -- 2.25.1
next prev parent reply other threads:[~2021-11-01 10:08 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:29 ` Richard Henderson 2021-11-01 10:29 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:33 ` Richard Henderson 2021-11-01 10:33 ` Richard Henderson 2021-11-02 1:48 ` LIU Zhiwei 2021-11-02 1:48 ` LIU Zhiwei 2021-11-02 10:18 ` Richard Henderson 2021-11-02 10:18 ` Richard Henderson 2021-11-01 10:01 ` LIU Zhiwei [this message] 2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2021-11-01 10:35 ` Richard Henderson 2021-11-01 10:35 ` Richard Henderson 2021-11-02 10:20 ` Richard Henderson 2021-11-02 10:20 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:40 ` Richard Henderson 2021-11-01 10:40 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:46 ` Richard Henderson 2021-11-01 10:46 ` Richard Henderson 2021-11-01 15:56 ` LIU Zhiwei 2021-11-01 15:56 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:53 ` Richard Henderson 2021-11-01 10:53 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:55 ` Richard Henderson 2021-11-01 10:55 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 13:41 ` Richard Henderson 2021-11-01 13:41 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 11:35 ` Richard Henderson 2021-11-01 11:35 ` Richard Henderson 2021-11-08 9:28 ` LIU Zhiwei 2021-11-08 9:28 ` LIU Zhiwei 2021-11-09 6:37 ` Richard Henderson 2021-11-09 6:37 ` Richard Henderson 2021-11-09 8:04 ` LIU Zhiwei 2021-11-09 8:04 ` LIU Zhiwei 2021-11-09 8:18 ` Richard Henderson 2021-11-09 8:18 ` Richard Henderson 2021-11-09 8:39 ` LIU Zhiwei 2021-11-09 8:39 ` LIU Zhiwei 2021-11-09 9:05 ` LIU Zhiwei 2021-11-09 9:05 ` LIU Zhiwei 2021-11-09 9:25 ` Richard Henderson 2021-11-09 9:25 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:33 ` Richard Henderson 2021-11-01 16:33 ` Richard Henderson 2021-11-08 9:38 ` LIU Zhiwei 2021-11-08 9:38 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:43 ` Richard Henderson 2021-11-01 16:43 ` Richard Henderson 2021-11-08 11:23 ` LIU Zhiwei 2021-11-08 11:23 ` LIU Zhiwei 2021-11-09 6:38 ` LIU Zhiwei 2021-11-09 6:38 ` LIU Zhiwei 2021-11-09 6:51 ` LIU Zhiwei 2021-11-09 6:51 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:49 ` Richard Henderson 2021-11-01 16:49 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 17:01 ` Richard Henderson 2021-11-01 17:01 ` Richard Henderson 2021-11-08 12:10 ` LIU Zhiwei 2021-11-08 12:10 ` LIU Zhiwei 2021-11-10 3:01 ` LIU Zhiwei 2021-11-10 3:01 ` LIU Zhiwei
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20211101100143.44356-4-zhiwei_liu@c-sky.com \ --to=zhiwei_liu@c-sky.com \ --cc=Alistair.Francis@wdc.com \ --cc=bin.meng@windriver.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.