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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN
Date: Mon, 1 Nov 2021 06:35:45 -0400	[thread overview]
Message-ID: <5c98ffca-202d-2c16-fcae-201003c05849@linaro.org> (raw)
In-Reply-To: <20211101100143.44356-4-zhiwei_liu@c-sky.com>

On 11/1/21 6:01 AM, LIU Zhiwei wrote:
> The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
> 
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
>   target/riscv/cpu_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Could perhaps be sorted to patch 2, then riscv_cpu_synchronize_from_tb and 
restore_state_to_opc could assert that the pc is properly extended.


r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com
Subject: Re: [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN
Date: Mon, 1 Nov 2021 06:35:45 -0400	[thread overview]
Message-ID: <5c98ffca-202d-2c16-fcae-201003c05849@linaro.org> (raw)
In-Reply-To: <20211101100143.44356-4-zhiwei_liu@c-sky.com>

On 11/1/21 6:01 AM, LIU Zhiwei wrote:
> The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
> 
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
>   target/riscv/cpu_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Could perhaps be sorted to patch 2, then riscv_cpu_synchronize_from_tb and 
restore_state_to_opc could assert that the pc is properly extended.


r~


  reply	other threads:[~2021-11-01 10:40 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 10:29   ` Richard Henderson
2021-11-01 10:29     ` Richard Henderson
2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 10:33   ` Richard Henderson
2021-11-01 10:33     ` Richard Henderson
2021-11-02  1:48     ` LIU Zhiwei
2021-11-02  1:48       ` LIU Zhiwei
2021-11-02 10:18       ` Richard Henderson
2021-11-02 10:18         ` Richard Henderson
2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 10:35   ` Richard Henderson [this message]
2021-11-01 10:35     ` Richard Henderson
2021-11-02 10:20   ` Richard Henderson
2021-11-02 10:20     ` Richard Henderson
2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 10:40   ` Richard Henderson
2021-11-01 10:40     ` Richard Henderson
2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 10:46   ` Richard Henderson
2021-11-01 10:46     ` Richard Henderson
2021-11-01 15:56     ` LIU Zhiwei
2021-11-01 15:56       ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 10:53   ` Richard Henderson
2021-11-01 10:53     ` Richard Henderson
2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 10:55   ` Richard Henderson
2021-11-01 10:55     ` Richard Henderson
2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 13:41   ` Richard Henderson
2021-11-01 13:41     ` Richard Henderson
2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 11:35   ` Richard Henderson
2021-11-01 11:35     ` Richard Henderson
2021-11-08  9:28     ` LIU Zhiwei
2021-11-08  9:28       ` LIU Zhiwei
2021-11-09  6:37       ` Richard Henderson
2021-11-09  6:37         ` Richard Henderson
2021-11-09  8:04         ` LIU Zhiwei
2021-11-09  8:04           ` LIU Zhiwei
2021-11-09  8:18           ` Richard Henderson
2021-11-09  8:18             ` Richard Henderson
2021-11-09  8:39             ` LIU Zhiwei
2021-11-09  8:39               ` LIU Zhiwei
2021-11-09  9:05               ` LIU Zhiwei
2021-11-09  9:05                 ` LIU Zhiwei
2021-11-09  9:25                 ` Richard Henderson
2021-11-09  9:25                   ` Richard Henderson
2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 16:33   ` Richard Henderson
2021-11-01 16:33     ` Richard Henderson
2021-11-08  9:38     ` LIU Zhiwei
2021-11-08  9:38       ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 16:43   ` Richard Henderson
2021-11-01 16:43     ` Richard Henderson
2021-11-08 11:23     ` LIU Zhiwei
2021-11-08 11:23       ` LIU Zhiwei
2021-11-09  6:38       ` LIU Zhiwei
2021-11-09  6:38         ` LIU Zhiwei
2021-11-09  6:51       ` LIU Zhiwei
2021-11-09  6:51         ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 16:49   ` Richard Henderson
2021-11-01 16:49     ` Richard Henderson
2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-01 10:01   ` LIU Zhiwei
2021-11-01 17:01   ` Richard Henderson
2021-11-01 17:01     ` Richard Henderson
2021-11-08 12:10     ` LIU Zhiwei
2021-11-08 12:10       ` LIU Zhiwei
2021-11-10  3:01     ` LIU Zhiwei
2021-11-10  3:01       ` LIU Zhiwei

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