From: Richard Henderson <richard.henderson@linaro.org> To: LIU Zhiwei <zhiwei_liu@c-sky.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com Subject: Re: [PATCH 08/13] target/riscv: Fix check range for first fault only Date: Mon, 1 Nov 2021 09:41:12 -0400 [thread overview] Message-ID: <c5f00da2-f022-bbb5-801d-ca69c7288927@linaro.org> (raw) In-Reply-To: <20211101100143.44356-9-zhiwei_liu@c-sky.com> On 11/1/21 6:01 AM, LIU Zhiwei wrote: > Only check the range that has passed the address translation. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/vector_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > @@ -638,12 +638,12 @@ vext_ldff(void *vd, void *v0, target_ulong base, > cpu_mmu_index(env, false)); > if (host) { > #ifdef CONFIG_USER_ONLY > - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { > + if (page_check_range(addr, offset, PAGE_READ) < 0) { > vl = i; > goto ProbeSuccess; > } > #else > - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); > + probe_pages(env, addr, offset, ra, MMU_DATA_LOAD); > #endif It looks like we could lose the ifdef here and always use probe_pages. But that of course is a different change. r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: LIU Zhiwei <zhiwei_liu@c-sky.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com Subject: Re: [PATCH 08/13] target/riscv: Fix check range for first fault only Date: Mon, 1 Nov 2021 09:41:12 -0400 [thread overview] Message-ID: <c5f00da2-f022-bbb5-801d-ca69c7288927@linaro.org> (raw) In-Reply-To: <20211101100143.44356-9-zhiwei_liu@c-sky.com> On 11/1/21 6:01 AM, LIU Zhiwei wrote: > Only check the range that has passed the address translation. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > --- > target/riscv/vector_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > @@ -638,12 +638,12 @@ vext_ldff(void *vd, void *v0, target_ulong base, > cpu_mmu_index(env, false)); > if (host) { > #ifdef CONFIG_USER_ONLY > - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { > + if (page_check_range(addr, offset, PAGE_READ) < 0) { > vl = i; > goto ProbeSuccess; > } > #else > - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); > + probe_pages(env, addr, offset, ra, MMU_DATA_LOAD); > #endif It looks like we could lose the ifdef here and always use probe_pages. But that of course is a different change. r~
next prev parent reply other threads:[~2021-11-01 13:42 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:29 ` Richard Henderson 2021-11-01 10:29 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:33 ` Richard Henderson 2021-11-01 10:33 ` Richard Henderson 2021-11-02 1:48 ` LIU Zhiwei 2021-11-02 1:48 ` LIU Zhiwei 2021-11-02 10:18 ` Richard Henderson 2021-11-02 10:18 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:35 ` Richard Henderson 2021-11-01 10:35 ` Richard Henderson 2021-11-02 10:20 ` Richard Henderson 2021-11-02 10:20 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:40 ` Richard Henderson 2021-11-01 10:40 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:46 ` Richard Henderson 2021-11-01 10:46 ` Richard Henderson 2021-11-01 15:56 ` LIU Zhiwei 2021-11-01 15:56 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:53 ` Richard Henderson 2021-11-01 10:53 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 10:55 ` Richard Henderson 2021-11-01 10:55 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 13:41 ` Richard Henderson [this message] 2021-11-01 13:41 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 11:35 ` Richard Henderson 2021-11-01 11:35 ` Richard Henderson 2021-11-08 9:28 ` LIU Zhiwei 2021-11-08 9:28 ` LIU Zhiwei 2021-11-09 6:37 ` Richard Henderson 2021-11-09 6:37 ` Richard Henderson 2021-11-09 8:04 ` LIU Zhiwei 2021-11-09 8:04 ` LIU Zhiwei 2021-11-09 8:18 ` Richard Henderson 2021-11-09 8:18 ` Richard Henderson 2021-11-09 8:39 ` LIU Zhiwei 2021-11-09 8:39 ` LIU Zhiwei 2021-11-09 9:05 ` LIU Zhiwei 2021-11-09 9:05 ` LIU Zhiwei 2021-11-09 9:25 ` Richard Henderson 2021-11-09 9:25 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:33 ` Richard Henderson 2021-11-01 16:33 ` Richard Henderson 2021-11-08 9:38 ` LIU Zhiwei 2021-11-08 9:38 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:43 ` Richard Henderson 2021-11-01 16:43 ` Richard Henderson 2021-11-08 11:23 ` LIU Zhiwei 2021-11-08 11:23 ` LIU Zhiwei 2021-11-09 6:38 ` LIU Zhiwei 2021-11-09 6:38 ` LIU Zhiwei 2021-11-09 6:51 ` LIU Zhiwei 2021-11-09 6:51 ` LIU Zhiwei 2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 16:49 ` Richard Henderson 2021-11-01 16:49 ` Richard Henderson 2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei 2021-11-01 10:01 ` LIU Zhiwei 2021-11-01 17:01 ` Richard Henderson 2021-11-01 17:01 ` Richard Henderson 2021-11-08 12:10 ` LIU Zhiwei 2021-11-08 12:10 ` LIU Zhiwei 2021-11-10 3:01 ` LIU Zhiwei 2021-11-10 3:01 ` LIU Zhiwei
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