From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol
Date: Mon, 1 Nov 2021 12:33:05 -0400 [thread overview]
Message-ID: <3c57a3d2-f47d-a0d8-c209-48f002b3c91e@linaro.org> (raw)
In-Reply-To: <20211101100143.44356-11-zhiwei_liu@c-sky.com>
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
> @@ -2677,6 +2677,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> /* This instruction ignores LMUL and vector register groups */
> int maxsz = s->vlen >> 3;
> TCGv_i64 t1;
> + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
> TCGLabel *over = gen_new_label();
>
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> @@ -2686,7 +2687,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> }
>
> t1 = tcg_temp_new_i64();
> - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
> + tcg_gen_extu_tl_i64(t1, src1);
> vec_element_storei(s, a->rd, 0, t1);
> tcg_temp_free_i64(t1);
> done:
This isn't actually correct. Or, may have been correct for the 0.7.1 revision, but the
rvv 1.0 revision has a sign-extend here.
This probably shouldn't be touched until the rvv 1.0 patch set comes in.
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 451688c328..5bdbbf7c71 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4763,6 +4763,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t mlen = vext_mlen(desc); \
> uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
> uint32_t vm = vext_vm(desc); \
> + uint32_t olen = 16 << vext_ol(desc); \
> uint32_t vl = env->vl; \
> uint32_t i; \
> \
> @@ -4771,7 +4772,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> continue; \
> } \
> if (i == 0) { \
> - *((ETYPE *)vd + H(i)) = s1; \
> + *((ETYPE *)vd + H(i)) = adjust_addr(s1, olen); \
> } else { \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
> } \
> @@ -4792,6 +4793,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t mlen = vext_mlen(desc); \
> uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
> uint32_t vm = vext_vm(desc); \
> + uint32_t olen = 16 << vext_ol(desc); \
> uint32_t vl = env->vl; \
> uint32_t i; \
> \
> @@ -4800,7 +4802,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> continue; \
> } \
> if (i == vl - 1) { \
> - *((ETYPE *)vd + H(i)) = s1; \
> + *((ETYPE *)vd + H(i)) = adjust_addr(s1, olen); \
> } else { \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
> } \
What in the world is this? S1 is not an address, it's just a value from X[RS1].
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com
Subject: Re: [PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol
Date: Mon, 1 Nov 2021 12:33:05 -0400 [thread overview]
Message-ID: <3c57a3d2-f47d-a0d8-c209-48f002b3c91e@linaro.org> (raw)
In-Reply-To: <20211101100143.44356-11-zhiwei_liu@c-sky.com>
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
> @@ -2677,6 +2677,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> /* This instruction ignores LMUL and vector register groups */
> int maxsz = s->vlen >> 3;
> TCGv_i64 t1;
> + TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
> TCGLabel *over = gen_new_label();
>
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> @@ -2686,7 +2687,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
> }
>
> t1 = tcg_temp_new_i64();
> - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
> + tcg_gen_extu_tl_i64(t1, src1);
> vec_element_storei(s, a->rd, 0, t1);
> tcg_temp_free_i64(t1);
> done:
This isn't actually correct. Or, may have been correct for the 0.7.1 revision, but the
rvv 1.0 revision has a sign-extend here.
This probably shouldn't be touched until the rvv 1.0 patch set comes in.
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 451688c328..5bdbbf7c71 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4763,6 +4763,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t mlen = vext_mlen(desc); \
> uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
> uint32_t vm = vext_vm(desc); \
> + uint32_t olen = 16 << vext_ol(desc); \
> uint32_t vl = env->vl; \
> uint32_t i; \
> \
> @@ -4771,7 +4772,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> continue; \
> } \
> if (i == 0) { \
> - *((ETYPE *)vd + H(i)) = s1; \
> + *((ETYPE *)vd + H(i)) = adjust_addr(s1, olen); \
> } else { \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
> } \
> @@ -4792,6 +4793,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> uint32_t mlen = vext_mlen(desc); \
> uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
> uint32_t vm = vext_vm(desc); \
> + uint32_t olen = 16 << vext_ol(desc); \
> uint32_t vl = env->vl; \
> uint32_t i; \
> \
> @@ -4800,7 +4802,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
> continue; \
> } \
> if (i == vl - 1) { \
> - *((ETYPE *)vd + H(i)) = s1; \
> + *((ETYPE *)vd + H(i)) = adjust_addr(s1, olen); \
> } else { \
> *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
> } \
What in the world is this? S1 is not an address, it's just a value from X[RS1].
r~
next prev parent reply other threads:[~2021-11-01 16:34 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:29 ` Richard Henderson
2021-11-01 10:29 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:33 ` Richard Henderson
2021-11-01 10:33 ` Richard Henderson
2021-11-02 1:48 ` LIU Zhiwei
2021-11-02 1:48 ` LIU Zhiwei
2021-11-02 10:18 ` Richard Henderson
2021-11-02 10:18 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:35 ` Richard Henderson
2021-11-01 10:35 ` Richard Henderson
2021-11-02 10:20 ` Richard Henderson
2021-11-02 10:20 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:40 ` Richard Henderson
2021-11-01 10:40 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:46 ` Richard Henderson
2021-11-01 10:46 ` Richard Henderson
2021-11-01 15:56 ` LIU Zhiwei
2021-11-01 15:56 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:53 ` Richard Henderson
2021-11-01 10:53 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 10:55 ` Richard Henderson
2021-11-01 10:55 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 13:41 ` Richard Henderson
2021-11-01 13:41 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 11:35 ` Richard Henderson
2021-11-01 11:35 ` Richard Henderson
2021-11-08 9:28 ` LIU Zhiwei
2021-11-08 9:28 ` LIU Zhiwei
2021-11-09 6:37 ` Richard Henderson
2021-11-09 6:37 ` Richard Henderson
2021-11-09 8:04 ` LIU Zhiwei
2021-11-09 8:04 ` LIU Zhiwei
2021-11-09 8:18 ` Richard Henderson
2021-11-09 8:18 ` Richard Henderson
2021-11-09 8:39 ` LIU Zhiwei
2021-11-09 8:39 ` LIU Zhiwei
2021-11-09 9:05 ` LIU Zhiwei
2021-11-09 9:05 ` LIU Zhiwei
2021-11-09 9:25 ` Richard Henderson
2021-11-09 9:25 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 16:33 ` Richard Henderson [this message]
2021-11-01 16:33 ` Richard Henderson
2021-11-08 9:38 ` LIU Zhiwei
2021-11-08 9:38 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 16:43 ` Richard Henderson
2021-11-01 16:43 ` Richard Henderson
2021-11-08 11:23 ` LIU Zhiwei
2021-11-08 11:23 ` LIU Zhiwei
2021-11-09 6:38 ` LIU Zhiwei
2021-11-09 6:38 ` LIU Zhiwei
2021-11-09 6:51 ` LIU Zhiwei
2021-11-09 6:51 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 16:49 ` Richard Henderson
2021-11-01 16:49 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei
2021-11-01 17:01 ` Richard Henderson
2021-11-01 17:01 ` Richard Henderson
2021-11-08 12:10 ` LIU Zhiwei
2021-11-08 12:10 ` LIU Zhiwei
2021-11-10 3:01 ` LIU Zhiwei
2021-11-10 3:01 ` LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3c57a3d2-f47d-a0d8-c209-48f002b3c91e@linaro.org \
--to=richard.henderson@linaro.org \
--cc=Alistair.Francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@c-sky.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.