From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v4 00/20] Support UXL filed in xstatus Date: Thu, 11 Nov 2021 23:51:29 +0800 [thread overview] Message-ID: <20211111155149.58172-1-zhiwei_liu@c-sky.com> (raw) In this patch set, we process the pc reigsters writes, gdb reads and writes, and address calculation under different UXLEN settings. The patch set v4 mainly address Richard comments on v3. Patch 8, 18, 19, 20 have not been reviewed. Others have been reviewed or acked. v4: Support SSTATUS64_UXL write Bump vmstate version for vill split v3: Merge gen_pm_adjust_address into a canonical address function Adjust address for RVA with XLEN Split pm_enabled into pm_mask_enabled and pm_base_enabled Replace array of pm tcg globals with one scalar tcg global Split and change patch sequence v2: Split out vill from vtype Remove context switch when xlen changes at exception Use XL instead of OL in many places Use pointer masking and XLEN for vector address Define an common fuction to calculate address for ldst LIU Zhiwei (20): target/riscv: Don't save pc when exception return target/riscv: Sign extend pc for different XLEN target/riscv: Ignore the pc bits above XLEN target/riscv: Extend pc for runtime pc write target/riscv: Use gdb xml according to max mxlen target/riscv: Relax debug check for pm write target/riscv: Adjust csr write mask with XLEN target/riscv: Create current pm fields in env target/riscv: Alloc tcg global for cur_pm[mask|base] target/riscv: Calculate address according to XLEN target/riscv: Split pm_enabled into mask and base target/riscv: Split out the vill from vtype target/riscv: Fix RESERVED field length in VTYPE target/riscv: Adjust vsetvl according to XLEN target/riscv: Remove VILL field in VTYPE target/riscv: Ajdust vector atomic check with XLEN target/riscv: Fix check range for first fault only target/riscv: Adjust vector address with mask target/riscv: Adjust scalar reg in vector with XLEN target/riscv: Enable uxl field write target/riscv/cpu.c | 23 +++++- target/riscv/cpu.h | 13 +++- target/riscv/cpu_bits.h | 2 + target/riscv/cpu_helper.c | 66 ++++++++++++---- target/riscv/csr.c | 43 ++++++++++- target/riscv/gdbstub.c | 71 ++++++++++++----- target/riscv/helper.h | 6 +- .../riscv/insn_trans/trans_privileged.c.inc | 7 +- target/riscv/insn_trans/trans_rva.c.inc | 9 +-- target/riscv/insn_trans/trans_rvd.c.inc | 19 +---- target/riscv/insn_trans/trans_rvf.c.inc | 19 +---- target/riscv/insn_trans/trans_rvi.c.inc | 22 +----- target/riscv/insn_trans/trans_rvv.c.inc | 51 ++++++++---- target/riscv/machine.c | 15 +++- target/riscv/op_helper.c | 7 +- target/riscv/translate.c | 77 +++++++++---------- target/riscv/vector_helper.c | 38 +++++---- 17 files changed, 300 insertions(+), 188 deletions(-) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v4 00/20] Support UXL filed in xstatus Date: Thu, 11 Nov 2021 23:51:29 +0800 [thread overview] Message-ID: <20211111155149.58172-1-zhiwei_liu@c-sky.com> (raw) In this patch set, we process the pc reigsters writes, gdb reads and writes, and address calculation under different UXLEN settings. The patch set v4 mainly address Richard comments on v3. Patch 8, 18, 19, 20 have not been reviewed. Others have been reviewed or acked. v4: Support SSTATUS64_UXL write Bump vmstate version for vill split v3: Merge gen_pm_adjust_address into a canonical address function Adjust address for RVA with XLEN Split pm_enabled into pm_mask_enabled and pm_base_enabled Replace array of pm tcg globals with one scalar tcg global Split and change patch sequence v2: Split out vill from vtype Remove context switch when xlen changes at exception Use XL instead of OL in many places Use pointer masking and XLEN for vector address Define an common fuction to calculate address for ldst LIU Zhiwei (20): target/riscv: Don't save pc when exception return target/riscv: Sign extend pc for different XLEN target/riscv: Ignore the pc bits above XLEN target/riscv: Extend pc for runtime pc write target/riscv: Use gdb xml according to max mxlen target/riscv: Relax debug check for pm write target/riscv: Adjust csr write mask with XLEN target/riscv: Create current pm fields in env target/riscv: Alloc tcg global for cur_pm[mask|base] target/riscv: Calculate address according to XLEN target/riscv: Split pm_enabled into mask and base target/riscv: Split out the vill from vtype target/riscv: Fix RESERVED field length in VTYPE target/riscv: Adjust vsetvl according to XLEN target/riscv: Remove VILL field in VTYPE target/riscv: Ajdust vector atomic check with XLEN target/riscv: Fix check range for first fault only target/riscv: Adjust vector address with mask target/riscv: Adjust scalar reg in vector with XLEN target/riscv: Enable uxl field write target/riscv/cpu.c | 23 +++++- target/riscv/cpu.h | 13 +++- target/riscv/cpu_bits.h | 2 + target/riscv/cpu_helper.c | 66 ++++++++++++---- target/riscv/csr.c | 43 ++++++++++- target/riscv/gdbstub.c | 71 ++++++++++++----- target/riscv/helper.h | 6 +- .../riscv/insn_trans/trans_privileged.c.inc | 7 +- target/riscv/insn_trans/trans_rva.c.inc | 9 +-- target/riscv/insn_trans/trans_rvd.c.inc | 19 +---- target/riscv/insn_trans/trans_rvf.c.inc | 19 +---- target/riscv/insn_trans/trans_rvi.c.inc | 22 +----- target/riscv/insn_trans/trans_rvv.c.inc | 51 ++++++++---- target/riscv/machine.c | 15 +++- target/riscv/op_helper.c | 7 +- target/riscv/translate.c | 77 +++++++++---------- target/riscv/vector_helper.c | 38 +++++---- 17 files changed, 300 insertions(+), 188 deletions(-) -- 2.25.1
next reply other threads:[~2021-11-11 15:53 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-11 15:51 LIU Zhiwei [this message] 2021-11-11 15:51 ` [PATCH v4 00/20] Support UXL filed in xstatus LIU Zhiwei 2021-11-11 15:51 ` [PATCH v4 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:25 ` Alistair Francis 2021-11-15 4:25 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:26 ` Alistair Francis 2021-11-15 4:26 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:27 ` Alistair Francis 2021-11-15 4:27 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 0:08 ` Alistair Francis 2021-11-16 0:08 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:12 ` Alistair Francis 2021-11-16 3:12 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:13 ` Alistair Francis 2021-11-16 3:13 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:14 ` Alistair Francis 2021-11-16 3:14 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 08/20] target/riscv: Create current pm fields in env LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:22 ` Alistair Francis 2021-11-19 4:22 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:29 ` Alistair Francis 2021-11-19 4:29 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:32 ` Alistair Francis 2021-11-19 4:32 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:51 ` Alistair Francis 2021-11-19 4:51 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:55 ` Alistair Francis 2021-11-19 4:55 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:56 ` Alistair Francis 2021-11-19 4:56 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:40 ` Alistair Francis 2021-11-19 12:40 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:33 ` Alistair Francis 2021-11-19 12:33 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:34 ` Alistair Francis 2021-11-19 12:34 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:42 ` Alistair Francis 2021-11-19 12:42 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:46 ` Alistair Francis 2021-11-19 12:46 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 15:51 ` [PATCH v4 20/20] target/riscv: Enable uxl field write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 18:23 ` Richard Henderson 2021-11-11 18:23 ` Richard Henderson 2021-11-19 12:55 ` Alistair Francis 2021-11-19 12:55 ` Alistair Francis 2021-11-19 12:57 ` [PATCH v4 00/20] Support UXL filed in xstatus Alistair Francis 2021-11-19 12:57 ` Alistair Francis 2021-11-19 13:44 ` LIU Zhiwei 2021-11-19 13:44 ` LIU Zhiwei
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