Re: [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN

[Alistair Francis <alistair23@gmail.com>]

On Fri, Nov 12, 2021 at 2:14 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/helper.h                   | 2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
>  target/riscv/vector_helper.c            | 8 +++++---
>  3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index c5098380dd..f2910f5f30 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
>  #endif
>
>  /* Vector functions */
> -DEF_HELPER_3(vsetvl, tl, env, tl, tl)
> +DEF_HELPER_4(vsetvl, tl, env, tl, tl, i32)
>  DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
>  DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
>  DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 17ee3babef..6fa673f4b2 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
>      } else {
>          s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
>      }
> -    gen_helper_vsetvl(dst, cpu_env, s1, s2);
> +    gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_i32(get_xlen(ctx)));
>      gen_set_gpr(ctx, a->rd, dst);
>
>      tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> @@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
>      } else {
>          s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
>      }
> -    gen_helper_vsetvl(dst, cpu_env, s1, s2);
> +    gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_i32(get_xlen(ctx)));
>      gen_set_gpr(ctx, a->rd, dst);
>
>      gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index b02ccefa4d..e49b431610 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -27,14 +27,16 @@
>  #include <math.h>
>
>  target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> -                            target_ulong s2)
> +                            target_ulong s2, uint32_t xlen)
>  {
>      int vlmax, vl;
>      RISCVCPU *cpu = env_archcpu(env);
>      uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
>      uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
> -    bool vill = FIELD_EX64(s2, VTYPE, VILL);
> -    target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
> +    bool vill = (s2 >> (xlen - 1)) & 0x1;
> +    target_ulong reserved = s2 &
> +                            MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> +                                            xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>
>      if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
>          /* only set vill bit. */
> --
> 2.25.1
>
>