From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com> Subject: Re: [PATCH v4 01/20] target/riscv: Don't save pc when exception return Date: Mon, 15 Nov 2021 14:25:22 +1000 [thread overview] Message-ID: <CAKmqyKO7P4aA23veee-WRQQQebDS76jURV8JiAXgPvDaXAJhQQ@mail.gmail.com> (raw) In-Reply-To: <20211111155149.58172-2-zhiwei_liu@c-sky.com> On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > As pc will be written by the xepc in exception return, just ignore > pc in translation. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/helper.h | 4 ++-- > target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- > target/riscv/op_helper.c | 4 ++-- > 3 files changed, 6 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index c7a5376227..c5098380dd 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int) > DEF_HELPER_3(csrw, void, env, int, tl) > DEF_HELPER_4(csrrw, tl, env, int, tl, tl) > #ifndef CONFIG_USER_ONLY > -DEF_HELPER_2(sret, tl, env, tl) > -DEF_HELPER_2(mret, tl, env, tl) > +DEF_HELPER_1(sret, tl, env) > +DEF_HELPER_1(mret, tl, env) > DEF_HELPER_1(wfi, void, env) > DEF_HELPER_1(tlb_flush, void, env) > #endif > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc > index 75c6ef80a6..6077bbbf11 100644 > --- a/target/riscv/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) > static bool trans_sret(DisasContext *ctx, arg_sret *a) > { > #ifndef CONFIG_USER_ONLY > - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); > - > if (has_ext(ctx, RVS)) { > - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); > + gen_helper_sret(cpu_pc, cpu_env); > tcg_gen_exit_tb(NULL, 0); /* no chaining */ > ctx->base.is_jmp = DISAS_NORETURN; > } else { > @@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) > static bool trans_mret(DisasContext *ctx, arg_mret *a) > { > #ifndef CONFIG_USER_ONLY > - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); > - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); > + gen_helper_mret(cpu_pc, cpu_env); > tcg_gen_exit_tb(NULL, 0); /* no chaining */ > ctx->base.is_jmp = DISAS_NORETURN; > return true; > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index ee7c24efe7..095d39671b 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, > > #ifndef CONFIG_USER_ONLY > > -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) > +target_ulong helper_sret(CPURISCVState *env) > { > uint64_t mstatus; > target_ulong prev_priv, prev_virt; > @@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) > return retpc; > } > > -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) > +target_ulong helper_mret(CPURISCVState *env) > { > if (!(env->priv >= PRV_M)) { > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > -- > 2.25.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Richard Henderson <richard.henderson@linaro.org>, Bin Meng <bin.meng@windriver.com>, Alistair Francis <Alistair.Francis@wdc.com> Subject: Re: [PATCH v4 01/20] target/riscv: Don't save pc when exception return Date: Mon, 15 Nov 2021 14:25:22 +1000 [thread overview] Message-ID: <CAKmqyKO7P4aA23veee-WRQQQebDS76jURV8JiAXgPvDaXAJhQQ@mail.gmail.com> (raw) In-Reply-To: <20211111155149.58172-2-zhiwei_liu@c-sky.com> On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > As pc will be written by the xepc in exception return, just ignore > pc in translation. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/helper.h | 4 ++-- > target/riscv/insn_trans/trans_privileged.c.inc | 7 ++----- > target/riscv/op_helper.c | 4 ++-- > 3 files changed, 6 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index c7a5376227..c5098380dd 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int) > DEF_HELPER_3(csrw, void, env, int, tl) > DEF_HELPER_4(csrrw, tl, env, int, tl, tl) > #ifndef CONFIG_USER_ONLY > -DEF_HELPER_2(sret, tl, env, tl) > -DEF_HELPER_2(mret, tl, env, tl) > +DEF_HELPER_1(sret, tl, env) > +DEF_HELPER_1(mret, tl, env) > DEF_HELPER_1(wfi, void, env) > DEF_HELPER_1(tlb_flush, void, env) > #endif > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc > index 75c6ef80a6..6077bbbf11 100644 > --- a/target/riscv/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a) > static bool trans_sret(DisasContext *ctx, arg_sret *a) > { > #ifndef CONFIG_USER_ONLY > - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); > - > if (has_ext(ctx, RVS)) { > - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); > + gen_helper_sret(cpu_pc, cpu_env); > tcg_gen_exit_tb(NULL, 0); /* no chaining */ > ctx->base.is_jmp = DISAS_NORETURN; > } else { > @@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) > static bool trans_mret(DisasContext *ctx, arg_mret *a) > { > #ifndef CONFIG_USER_ONLY > - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); > - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); > + gen_helper_mret(cpu_pc, cpu_env); > tcg_gen_exit_tb(NULL, 0); /* no chaining */ > ctx->base.is_jmp = DISAS_NORETURN; > return true; > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index ee7c24efe7..095d39671b 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, > > #ifndef CONFIG_USER_ONLY > > -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) > +target_ulong helper_sret(CPURISCVState *env) > { > uint64_t mstatus; > target_ulong prev_priv, prev_virt; > @@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) > return retpc; > } > > -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) > +target_ulong helper_mret(CPURISCVState *env) > { > if (!(env->priv >= PRV_M)) { > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > -- > 2.25.1 > >
next prev parent reply other threads:[~2021-11-15 4:27 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-11 15:51 [PATCH v4 00/20] Support UXL filed in xstatus LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 15:51 ` [PATCH v4 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:25 ` Alistair Francis [this message] 2021-11-15 4:25 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:26 ` Alistair Francis 2021-11-15 4:26 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:27 ` Alistair Francis 2021-11-15 4:27 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 0:08 ` Alistair Francis 2021-11-16 0:08 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:12 ` Alistair Francis 2021-11-16 3:12 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:13 ` Alistair Francis 2021-11-16 3:13 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:14 ` Alistair Francis 2021-11-16 3:14 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 08/20] target/riscv: Create current pm fields in env LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:22 ` Alistair Francis 2021-11-19 4:22 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:29 ` Alistair Francis 2021-11-19 4:29 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:32 ` Alistair Francis 2021-11-19 4:32 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:51 ` Alistair Francis 2021-11-19 4:51 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:55 ` Alistair Francis 2021-11-19 4:55 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:56 ` Alistair Francis 2021-11-19 4:56 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:40 ` Alistair Francis 2021-11-19 12:40 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:33 ` Alistair Francis 2021-11-19 12:33 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:34 ` Alistair Francis 2021-11-19 12:34 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:42 ` Alistair Francis 2021-11-19 12:42 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:46 ` Alistair Francis 2021-11-19 12:46 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 15:51 ` [PATCH v4 20/20] target/riscv: Enable uxl field write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 18:23 ` Richard Henderson 2021-11-11 18:23 ` Richard Henderson 2021-11-19 12:55 ` Alistair Francis 2021-11-19 12:55 ` Alistair Francis 2021-11-19 12:57 ` [PATCH v4 00/20] Support UXL filed in xstatus Alistair Francis 2021-11-19 12:57 ` Alistair Francis 2021-11-19 13:44 ` LIU Zhiwei 2021-11-19 13:44 ` LIU Zhiwei
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