From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com> Subject: Re: [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen Date: Tue, 16 Nov 2021 13:12:41 +1000 [thread overview] Message-ID: <CAKmqyKPD4pBHK6G+Y-YRN-msPV1g_rj_-qPHwMLpJcQc_42JSw@mail.gmail.com> (raw) In-Reply-To: <20211111155149.58172-6-zhiwei_liu@c-sky.com> On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++----------- > 1 file changed, 52 insertions(+), 19 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index 23429179e2..8d0f9139d7 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -24,11 +24,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > { > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > + target_ulong tmp; > > if (n < 32) { > - return gdb_get_regl(mem_buf, env->gpr[n]); > + tmp = env->gpr[n]; > } else if (n == 32) { > - return gdb_get_regl(mem_buf, env->pc); > + tmp = env->pc; > + } else { > + return 0; > + } > + > + switch (env->misa_mxl_max) { > + case MXL_RV32: > + return gdb_get_reg32(mem_buf, tmp); > + case MXL_RV64: > + return gdb_get_reg64(mem_buf, tmp); > + default: > + g_assert_not_reached(); > } > return 0; > } > @@ -37,18 +49,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > { > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > - > - if (n == 0) { > - /* discard writes to x0 */ > - return sizeof(target_ulong); > - } else if (n < 32) { > - env->gpr[n] = ldtul_p(mem_buf); > - return sizeof(target_ulong); > + int length = 0; > + target_ulong tmp; > + > + switch (env->misa_mxl_max) { > + case MXL_RV32: > + tmp = (int32_t)ldl_p(mem_buf); > + length = 4; > + break; > + case MXL_RV64: > + if (cpu_get_xl(env) < MXL_RV64) { > + tmp = (int32_t)ldq_p(mem_buf); > + } else { > + tmp = ldq_p(mem_buf); > + } > + length = 8; > + break; > + default: > + g_assert_not_reached(); > + } > + if (n > 0 && n < 32) { > + env->gpr[n] = tmp; > } else if (n == 32) { > - env->pc = ldtul_p(mem_buf); > - return sizeof(target_ulong); > + env->pc = tmp; > } > - return 0; > + > + return length; > } > > static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) > @@ -198,13 +224,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, > 36, "riscv-32bit-fpu.xml", 0); > } > -#if defined(TARGET_RISCV32) > - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, > - 1, "riscv-32bit-virtual.xml", 0); > -#elif defined(TARGET_RISCV64) > - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, > - 1, "riscv-64bit-virtual.xml", 0); > -#endif > + switch (env->misa_mxl_max) { > + case MXL_RV32: > + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > + riscv_gdb_set_virtual, > + 1, "riscv-32bit-virtual.xml", 0); > + break; > + case MXL_RV64: > + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > + riscv_gdb_set_virtual, > + 1, "riscv-64bit-virtual.xml", 0); > + break; > + default: > + g_assert_not_reached(); > + } > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs), > -- > 2.25.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: LIU Zhiwei <zhiwei_liu@c-sky.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Palmer Dabbelt <palmer@dabbelt.com>, Richard Henderson <richard.henderson@linaro.org>, Bin Meng <bin.meng@windriver.com>, Alistair Francis <Alistair.Francis@wdc.com> Subject: Re: [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen Date: Tue, 16 Nov 2021 13:12:41 +1000 [thread overview] Message-ID: <CAKmqyKPD4pBHK6G+Y-YRN-msPV1g_rj_-qPHwMLpJcQc_42JSw@mail.gmail.com> (raw) In-Reply-To: <20211111155149.58172-6-zhiwei_liu@c-sky.com> On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/gdbstub.c | 71 +++++++++++++++++++++++++++++++----------- > 1 file changed, 52 insertions(+), 19 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index 23429179e2..8d0f9139d7 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -24,11 +24,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) > { > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > + target_ulong tmp; > > if (n < 32) { > - return gdb_get_regl(mem_buf, env->gpr[n]); > + tmp = env->gpr[n]; > } else if (n == 32) { > - return gdb_get_regl(mem_buf, env->pc); > + tmp = env->pc; > + } else { > + return 0; > + } > + > + switch (env->misa_mxl_max) { > + case MXL_RV32: > + return gdb_get_reg32(mem_buf, tmp); > + case MXL_RV64: > + return gdb_get_reg64(mem_buf, tmp); > + default: > + g_assert_not_reached(); > } > return 0; > } > @@ -37,18 +49,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > { > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > - > - if (n == 0) { > - /* discard writes to x0 */ > - return sizeof(target_ulong); > - } else if (n < 32) { > - env->gpr[n] = ldtul_p(mem_buf); > - return sizeof(target_ulong); > + int length = 0; > + target_ulong tmp; > + > + switch (env->misa_mxl_max) { > + case MXL_RV32: > + tmp = (int32_t)ldl_p(mem_buf); > + length = 4; > + break; > + case MXL_RV64: > + if (cpu_get_xl(env) < MXL_RV64) { > + tmp = (int32_t)ldq_p(mem_buf); > + } else { > + tmp = ldq_p(mem_buf); > + } > + length = 8; > + break; > + default: > + g_assert_not_reached(); > + } > + if (n > 0 && n < 32) { > + env->gpr[n] = tmp; > } else if (n == 32) { > - env->pc = ldtul_p(mem_buf); > - return sizeof(target_ulong); > + env->pc = tmp; > } > - return 0; > + > + return length; > } > > static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) > @@ -198,13 +224,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, > 36, "riscv-32bit-fpu.xml", 0); > } > -#if defined(TARGET_RISCV32) > - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, > - 1, "riscv-32bit-virtual.xml", 0); > -#elif defined(TARGET_RISCV64) > - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, > - 1, "riscv-64bit-virtual.xml", 0); > -#endif > + switch (env->misa_mxl_max) { > + case MXL_RV32: > + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > + riscv_gdb_set_virtual, > + 1, "riscv-32bit-virtual.xml", 0); > + break; > + case MXL_RV64: > + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, > + riscv_gdb_set_virtual, > + 1, "riscv-64bit-virtual.xml", 0); > + break; > + default: > + g_assert_not_reached(); > + } > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs), > -- > 2.25.1 > >
next prev parent reply other threads:[~2021-11-16 3:13 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-11 15:51 [PATCH v4 00/20] Support UXL filed in xstatus LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 15:51 ` [PATCH v4 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:25 ` Alistair Francis 2021-11-15 4:25 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:26 ` Alistair Francis 2021-11-15 4:26 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-15 4:27 ` Alistair Francis 2021-11-15 4:27 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 0:08 ` Alistair Francis 2021-11-16 0:08 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:12 ` Alistair Francis [this message] 2021-11-16 3:12 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:13 ` Alistair Francis 2021-11-16 3:13 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-16 3:14 ` Alistair Francis 2021-11-16 3:14 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 08/20] target/riscv: Create current pm fields in env LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:22 ` Alistair Francis 2021-11-19 4:22 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:29 ` Alistair Francis 2021-11-19 4:29 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:32 ` Alistair Francis 2021-11-19 4:32 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:51 ` Alistair Francis 2021-11-19 4:51 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:55 ` Alistair Francis 2021-11-19 4:55 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 4:56 ` Alistair Francis 2021-11-19 4:56 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:40 ` Alistair Francis 2021-11-19 12:40 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:33 ` Alistair Francis 2021-11-19 12:33 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:34 ` Alistair Francis 2021-11-19 12:34 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:42 ` Alistair Francis 2021-11-19 12:42 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-19 12:46 ` Alistair Francis 2021-11-19 12:46 ` Alistair Francis 2021-11-11 15:51 ` [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 15:51 ` [PATCH v4 20/20] target/riscv: Enable uxl field write LIU Zhiwei 2021-11-11 15:51 ` LIU Zhiwei 2021-11-11 18:23 ` Richard Henderson 2021-11-11 18:23 ` Richard Henderson 2021-11-19 12:55 ` Alistair Francis 2021-11-19 12:55 ` Alistair Francis 2021-11-19 12:57 ` [PATCH v4 00/20] Support UXL filed in xstatus Alistair Francis 2021-11-19 12:57 ` Alistair Francis 2021-11-19 13:44 ` LIU Zhiwei 2021-11-19 13:44 ` LIU Zhiwei
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