All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN
Date: Mon, 15 Nov 2021 14:27:43 +1000	[thread overview]
Message-ID: <CAKmqyKOyV6R1YFTDsQGDTbU9ggBijGDgyD_2z-CC2jR44Cao-g@mail.gmail.com> (raw)
In-Reply-To: <20211111155149.58172-4-zhiwei_liu@c-sky.com>

On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 9eeed38c7e..4c048cc266 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>                            target_ulong *cs_base, uint32_t *pflags)
>  {
>      uint32_t flags = 0;
> +    RISCVMXL xl = cpu_get_xl(env);
>
> -    *pc = env->pc;
> +    *pc = xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
>      *cs_base = 0;
>
>      if (riscv_has_ext(env, RVV)) {
> @@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>      }
>  #endif
>
> -    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
> +    flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
>
>      *pflags = flags;
>  }
> --
> 2.25.1
>
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	 Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN
Date: Mon, 15 Nov 2021 14:27:43 +1000	[thread overview]
Message-ID: <CAKmqyKOyV6R1YFTDsQGDTbU9ggBijGDgyD_2z-CC2jR44Cao-g@mail.gmail.com> (raw)
In-Reply-To: <20211111155149.58172-4-zhiwei_liu@c-sky.com>

On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 9eeed38c7e..4c048cc266 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>                            target_ulong *cs_base, uint32_t *pflags)
>  {
>      uint32_t flags = 0;
> +    RISCVMXL xl = cpu_get_xl(env);
>
> -    *pc = env->pc;
> +    *pc = xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
>      *cs_base = 0;
>
>      if (riscv_has_ext(env, RVV)) {
> @@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>      }
>  #endif
>
> -    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
> +    flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
>
>      *pflags = flags;
>  }
> --
> 2.25.1
>
>


  reply	other threads:[~2021-11-15  4:29 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-11 15:51 [PATCH v4 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 15:51 ` LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-15  4:25   ` Alistair Francis
2021-11-15  4:25     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-15  4:26   ` Alistair Francis
2021-11-15  4:26     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-15  4:27   ` Alistair Francis [this message]
2021-11-15  4:27     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-16  0:08   ` Alistair Francis
2021-11-16  0:08     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-16  3:12   ` Alistair Francis
2021-11-16  3:12     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-16  3:13   ` Alistair Francis
2021-11-16  3:13     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-16  3:14   ` Alistair Francis
2021-11-16  3:14     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19  4:22   ` Alistair Francis
2021-11-19  4:22     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19  4:29   ` Alistair Francis
2021-11-19  4:29     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19  4:32   ` Alistair Francis
2021-11-19  4:32     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19  4:51   ` Alistair Francis
2021-11-19  4:51     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19  4:55   ` Alistair Francis
2021-11-19  4:55     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19  4:56   ` Alistair Francis
2021-11-19  4:56     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19 12:40   ` Alistair Francis
2021-11-19 12:40     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19 12:33   ` Alistair Francis
2021-11-19 12:33     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19 12:34   ` Alistair Francis
2021-11-19 12:34     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19 12:42   ` Alistair Francis
2021-11-19 12:42     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-19 12:46   ` Alistair Francis
2021-11-19 12:46     ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 15:51   ` LIU Zhiwei
2021-11-11 18:23   ` Richard Henderson
2021-11-11 18:23     ` Richard Henderson
2021-11-19 12:55   ` Alistair Francis
2021-11-19 12:55     ` Alistair Francis
2021-11-19 12:57 ` [PATCH v4 00/20] Support UXL filed in xstatus Alistair Francis
2021-11-19 12:57   ` Alistair Francis
2021-11-19 13:44   ` LIU Zhiwei
2021-11-19 13:44     ` LIU Zhiwei

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKmqyKOyV6R1YFTDsQGDTbU9ggBijGDgyD_2z-CC2jR44Cao-g@mail.gmail.com \
    --to=alistair23@gmail.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=zhiwei_liu@c-sky.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.