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From: kernel test robot <lkp@intel.com>
To: Greentime Hu <greentime.hu@sifive.com>,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	aou@eecs.berkeley.edu
Cc: kbuild-all@lists.01.org
Subject: Re: [PATCH v9 05/17] riscv: Add vector feature to compile
Date: Fri, 12 Nov 2021 08:54:56 +0800	[thread overview]
Message-ID: <202111120819.DVre82zZ-lkp@intel.com> (raw)
In-Reply-To: <2684ea9e25a63c7a88faf46680a26e560027e444.1636362169.git.greentime.hu@sifive.com>

[-- Attachment #1: Type: text/plain, Size: 2725 bytes --]

Hi Greentime,

I love your patch! Yet something to improve:

[auto build test ERROR on v5.15]
[cannot apply to linus/master next-20211111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20211109-175222
base:   DEBUG invalid remote for branch v5.15 8bb7eca972ad531c9b149c0a51ab43a417385813
config: riscv-allyesconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/b164ca135b641a96cea32346baec67e96bf468a2
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20211109-175222
        git checkout b164ca135b641a96cea32346baec67e96bf468a2
        # save the attached .config to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv prepare

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   scripts/genksyms/parse.y: warning: 9 shift/reduce conflicts [-Wconflicts-sr]
   scripts/genksyms/parse.y: warning: 5 reduce/reduce conflicts [-Wconflicts-rr]
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/rt_sigreturn.o] Error 1
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/getcpu.o] Error 1
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/note.o] Error 1
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/flush_icache.o] Error 1
   make[2]: Target 'include/generated/vdso-offsets.h' not remade because of errors.
   make[1]: *** [arch/riscv/Makefile:121: vdso_prepare] Error 2
   make[1]: Target 'prepare' not remade because of errors.
   make: *** [Makefile:219: __sub-make] Error 2
   make: Target 'prepare' not remade because of errors.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: Greentime Hu <greentime.hu@sifive.com>,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	aou@eecs.berkeley.edu
Cc: kbuild-all@lists.01.org
Subject: Re: [PATCH v9 05/17] riscv: Add vector feature to compile
Date: Fri, 12 Nov 2021 08:54:56 +0800	[thread overview]
Message-ID: <202111120819.DVre82zZ-lkp@intel.com> (raw)
In-Reply-To: <2684ea9e25a63c7a88faf46680a26e560027e444.1636362169.git.greentime.hu@sifive.com>

[-- Attachment #1: Type: text/plain, Size: 2725 bytes --]

Hi Greentime,

I love your patch! Yet something to improve:

[auto build test ERROR on v5.15]
[cannot apply to linus/master next-20211111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20211109-175222
base:   DEBUG invalid remote for branch v5.15 8bb7eca972ad531c9b149c0a51ab43a417385813
config: riscv-allyesconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/b164ca135b641a96cea32346baec67e96bf468a2
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20211109-175222
        git checkout b164ca135b641a96cea32346baec67e96bf468a2
        # save the attached .config to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv prepare

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   scripts/genksyms/parse.y: warning: 9 shift/reduce conflicts [-Wconflicts-sr]
   scripts/genksyms/parse.y: warning: 5 reduce/reduce conflicts [-Wconflicts-rr]
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/rt_sigreturn.o] Error 1
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/getcpu.o] Error 1
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/note.o] Error 1
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/flush_icache.o] Error 1
   make[2]: Target 'include/generated/vdso-offsets.h' not remade because of errors.
   make[1]: *** [arch/riscv/Makefile:121: vdso_prepare] Error 2
   make[1]: Target 'prepare' not remade because of errors.
   make: *** [Makefile:219: __sub-make] Error 2
   make: Target 'prepare' not remade because of errors.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH v9 05/17] riscv: Add vector feature to compile
Date: Fri, 12 Nov 2021 08:54:56 +0800	[thread overview]
Message-ID: <202111120819.DVre82zZ-lkp@intel.com> (raw)
In-Reply-To: <2684ea9e25a63c7a88faf46680a26e560027e444.1636362169.git.greentime.hu@sifive.com>

[-- Attachment #1: Type: text/plain, Size: 2780 bytes --]

Hi Greentime,

I love your patch! Yet something to improve:

[auto build test ERROR on v5.15]
[cannot apply to linus/master next-20211111]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20211109-175222
base:   DEBUG invalid remote for branch v5.15 8bb7eca972ad531c9b149c0a51ab43a417385813
config: riscv-allyesconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/b164ca135b641a96cea32346baec67e96bf468a2
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20211109-175222
        git checkout b164ca135b641a96cea32346baec67e96bf468a2
        # save the attached .config to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv prepare

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   scripts/genksyms/parse.y: warning: 9 shift/reduce conflicts [-Wconflicts-sr]
   scripts/genksyms/parse.y: warning: 5 reduce/reduce conflicts [-Wconflicts-rr]
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/rt_sigreturn.o] Error 1
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/getcpu.o] Error 1
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/note.o] Error 1
   Assembler messages:
>> Error: cannot find default versions of the ISA extension `v'
   make[2]: *** [scripts/Makefile.build:379: arch/riscv/kernel/vdso/flush_icache.o] Error 1
   make[2]: Target 'include/generated/vdso-offsets.h' not remade because of errors.
   make[1]: *** [arch/riscv/Makefile:121: vdso_prepare] Error 2
   make[1]: Target 'prepare' not remade because of errors.
   make: *** [Makefile:219: __sub-make] Error 2
   make: Target 'prepare' not remade because of errors.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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  reply	other threads:[~2021-11-12  0:55 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09  9:48 [PATCH v9 00/17] riscv: Add vector ISA support Greentime Hu
2021-11-09  9:48 ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 01/17] riscv: Separate patch for cflags and aflags Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 02/17] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 04/17] riscv: Add new csr defines related to vector extension Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 05/17] riscv: Add vector feature to compile Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-12  0:54   ` kernel test robot [this message]
2021-11-12  0:54     ` kernel test robot
2021-11-12  0:54     ` kernel test robot
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 07/17] riscv: Reset vector register Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2022-01-04  6:02     ` Greentime Hu
2022-01-04  6:02       ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 08/17] riscv: Add vector struct and assembler definitions Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2022-01-07 13:28     ` Greentime Hu
2022-01-07 13:28       ` Greentime Hu
2022-01-07 13:53       ` Jessica Clarke
2022-01-07 13:53         ` Jessica Clarke
2021-11-09  9:48 ` [PATCH v9 09/17] riscv: Add task switch support for vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-11 13:49   ` kernel test robot
2021-11-11 13:49     ` kernel test robot
2021-11-11 13:49     ` kernel test robot
2021-11-11 19:16   ` kernel test robot
2021-11-11 19:16     ` kernel test robot
2021-11-11 19:16     ` kernel test robot
2021-12-15 18:38   ` Palmer Dabbelt
2021-12-15 18:38     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 10/17] riscv: Add ptrace vector support Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 11/17] riscv: Add sigcontext save/restore for vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 12/17] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 13/17] riscv: Add support for kernel mode vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 14/17] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 15/17] riscv: Add vector extension XOR implementation Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-10 10:38   ` Ben Dooks
2021-11-10 10:38     ` Ben Dooks
2021-11-16 13:14     ` Greentime Hu
2021-11-16 13:14       ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 17/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Greentime Hu
2021-11-09  9:48   ` Greentime Hu

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