From: Greentime Hu <greentime.hu@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v9 04/17] riscv: Add new csr defines related to vector extension Date: Tue, 9 Nov 2021 17:48:16 +0800 [thread overview] Message-ID: <6013bd0c309cecf244a151b54ee73c0ebd391663.1636362169.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1636362169.git.greentime.hu@sifive.com> Follow the riscv vector spec to add new csr numbers. [guoren@linux.alibaba.com: first porting for new vector related csr] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Acked-by: Guo Ren <guoren@kernel.org> Co-developed-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 87ac65696871..069743102fac 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -24,6 +24,12 @@ #define SR_FS_CLEAN _AC(0x00004000, UL) #define SR_FS_DIRTY _AC(0x00006000, UL) +#define SR_VS _AC(0x00000600, UL) /* Vector Status */ +#define SR_VS_OFF _AC(0x00000000, UL) +#define SR_VS_INITIAL _AC(0x00000200, UL) +#define SR_VS_CLEAN _AC(0x00000400, UL) +#define SR_VS_DIRTY _AC(0x00000600, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) @@ -31,9 +37,9 @@ #define SR_XS_DIRTY _AC(0x00018000, UL) #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ #endif /* SATP flags */ @@ -120,6 +126,12 @@ #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_VSTART 0x8 +#define CSR_VCSR 0xf +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com> To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v9 04/17] riscv: Add new csr defines related to vector extension Date: Tue, 9 Nov 2021 17:48:16 +0800 [thread overview] Message-ID: <6013bd0c309cecf244a151b54ee73c0ebd391663.1636362169.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1636362169.git.greentime.hu@sifive.com> Follow the riscv vector spec to add new csr numbers. [guoren@linux.alibaba.com: first porting for new vector related csr] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Acked-by: Guo Ren <guoren@kernel.org> Co-developed-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 87ac65696871..069743102fac 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -24,6 +24,12 @@ #define SR_FS_CLEAN _AC(0x00004000, UL) #define SR_FS_DIRTY _AC(0x00006000, UL) +#define SR_VS _AC(0x00000600, UL) /* Vector Status */ +#define SR_VS_OFF _AC(0x00000000, UL) +#define SR_VS_INITIAL _AC(0x00000200, UL) +#define SR_VS_CLEAN _AC(0x00000400, UL) +#define SR_VS_DIRTY _AC(0x00000600, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) @@ -31,9 +37,9 @@ #define SR_XS_DIRTY _AC(0x00018000, UL) #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ #endif /* SATP flags */ @@ -120,6 +126,12 @@ #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_VSTART 0x8 +#define CSR_VCSR 0xf +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE -- 2.31.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-11-09 9:50 UTC|newest] Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-09 9:48 [PATCH v9 00/17] riscv: Add vector ISA support Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 01/17] riscv: Separate patch for cflags and aflags Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 02/17] riscv: Rename __switch_to_aux -> fpu Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` Greentime Hu [this message] 2021-11-09 9:48 ` [PATCH v9 04/17] riscv: Add new csr defines related to vector extension Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 05/17] riscv: Add vector feature to compile Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-12 0:54 ` kernel test robot 2021-11-12 0:54 ` kernel test robot 2021-11-12 0:54 ` kernel test robot 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 07/17] riscv: Reset vector register Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2022-01-04 6:02 ` Greentime Hu 2022-01-04 6:02 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 08/17] riscv: Add vector struct and assembler definitions Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2022-01-07 13:28 ` Greentime Hu 2022-01-07 13:28 ` Greentime Hu 2022-01-07 13:53 ` Jessica Clarke 2022-01-07 13:53 ` Jessica Clarke 2021-11-09 9:48 ` [PATCH v9 09/17] riscv: Add task switch support for vector Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-11 13:49 ` kernel test robot 2021-11-11 13:49 ` kernel test robot 2021-11-11 13:49 ` kernel test robot 2021-11-11 19:16 ` kernel test robot 2021-11-11 19:16 ` kernel test robot 2021-11-11 19:16 ` kernel test robot 2021-12-15 18:38 ` Palmer Dabbelt 2021-12-15 18:38 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 10/17] riscv: Add ptrace vector support Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 11/17] riscv: Add sigcontext save/restore for vector Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 12/17] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 13/17] riscv: Add support for kernel mode vector Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 14/17] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 15/17] riscv: Add vector extension XOR implementation Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-10 10:38 ` Ben Dooks 2021-11-10 10:38 ` Ben Dooks 2021-11-16 13:14 ` Greentime Hu 2021-11-16 13:14 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 17/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Greentime Hu 2021-11-09 9:48 ` Greentime Hu
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