From: Greentime Hu <greentime.hu@sifive.com> To: Ben Dooks <ben.dooks@codethink.co.uk> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Albert Ou <aou@eecs.berkeley.edu> Subject: Re: [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Date: Tue, 16 Nov 2021 21:14:29 +0800 [thread overview] Message-ID: <CAHCEehLnX6hAr6uRYy4BxzuBhTp64wn0yCVGJ85+0aS88OeKtA@mail.gmail.com> (raw) In-Reply-To: <2d08f105-64fd-a43a-1dea-24870ff7c5b0@codethink.co.uk> Ben Dooks <ben.dooks@codethink.co.uk> 於 2021年11月10日 週三 下午6:38寫道: > > On 09/11/2021 09:48, Greentime Hu wrote: > > It triggered an illegal instruction exception when accessing vlenb CSR > > without enable vector first. To fix this issue, we should enable vector > > before using it and disable vector after using it. > > > > Co-developed-by: Vincent Chen <vincent.chen@sifive.com> > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > > --- > > arch/riscv/include/asm/vector.h | 2 ++ > > arch/riscv/kernel/cpufeature.c | 2 ++ > > arch/riscv/kernel/kernel_mode_vector.c | 6 ++++-- > > 3 files changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h > > index 5d7f14453f68..ca063c8f47f2 100644 > > --- a/arch/riscv/include/asm/vector.h > > +++ b/arch/riscv/include/asm/vector.h > > @@ -8,6 +8,8 @@ > > > > #include <linux/types.h> > > > > +void rvv_enable(void); > > +void rvv_disable(void); > > void kernel_rvv_begin(void); > > void kernel_rvv_end(void); > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 8e7557980faf..0139ec20adce 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -159,7 +159,9 @@ void __init riscv_fill_hwcap(void) > > if (elf_hwcap & COMPAT_HWCAP_ISA_V) { > > static_branch_enable(&cpu_hwcap_vector); > > /* There are 32 vector registers with vlenb length. */ > > + rvv_enable(); > > riscv_vsize = csr_read(CSR_VLENB) * 32; > > + rvv_disable(); > > } > > #endif > > Would it be better to enable this here, and then restore the original > state instead of calling rvv_disable? If it was enabled then maybe > something else is going to rely on that state? > > Maybe something like: > > prev = rvv_enable() > riscv_vsize = csr_read(CSR_VLENB) * 32; > rvv_restore(prev); > > Hi Ben, Thank you for reviewing this. The rvv won't be enabled here because we disable it in head.S at beginning and this stage is still doing some initialization work for rvv to set riscv_vsize, so we can assume that kernel mode vector should not be allowed to use vector yet. > > } > > diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c > > index 8d2e53ea25c1..1ecb6ec5c56d 100644 > > --- a/arch/riscv/kernel/kernel_mode_vector.c > > +++ b/arch/riscv/kernel/kernel_mode_vector.c > > @@ -71,15 +71,17 @@ static void put_cpu_vector_context(void) > > preempt_enable(); > > } > > > > -static void rvv_enable(void) > > +void rvv_enable(void) > > { > > csr_set(CSR_STATUS, SR_VS); > > } > > +EXPORT_SYMBOL(rvv_enable); > > > > -static void rvv_disable(void) > > +void rvv_disable(void) > > { > > csr_clear(CSR_STATUS, SR_VS); > > } > > +EXPORT_SYMBOL(rvv_disable); > > > > /* > > * kernel_rvv_begin(): obtain the CPU vector registers for use by the calling > > > > > -- > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius > > https://www.codethink.co.uk/privacy.html
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com> To: Ben Dooks <ben.dooks@codethink.co.uk> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Albert Ou <aou@eecs.berkeley.edu> Subject: Re: [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Date: Tue, 16 Nov 2021 21:14:29 +0800 [thread overview] Message-ID: <CAHCEehLnX6hAr6uRYy4BxzuBhTp64wn0yCVGJ85+0aS88OeKtA@mail.gmail.com> (raw) In-Reply-To: <2d08f105-64fd-a43a-1dea-24870ff7c5b0@codethink.co.uk> Ben Dooks <ben.dooks@codethink.co.uk> 於 2021年11月10日 週三 下午6:38寫道: > > On 09/11/2021 09:48, Greentime Hu wrote: > > It triggered an illegal instruction exception when accessing vlenb CSR > > without enable vector first. To fix this issue, we should enable vector > > before using it and disable vector after using it. > > > > Co-developed-by: Vincent Chen <vincent.chen@sifive.com> > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > > --- > > arch/riscv/include/asm/vector.h | 2 ++ > > arch/riscv/kernel/cpufeature.c | 2 ++ > > arch/riscv/kernel/kernel_mode_vector.c | 6 ++++-- > > 3 files changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h > > index 5d7f14453f68..ca063c8f47f2 100644 > > --- a/arch/riscv/include/asm/vector.h > > +++ b/arch/riscv/include/asm/vector.h > > @@ -8,6 +8,8 @@ > > > > #include <linux/types.h> > > > > +void rvv_enable(void); > > +void rvv_disable(void); > > void kernel_rvv_begin(void); > > void kernel_rvv_end(void); > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 8e7557980faf..0139ec20adce 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -159,7 +159,9 @@ void __init riscv_fill_hwcap(void) > > if (elf_hwcap & COMPAT_HWCAP_ISA_V) { > > static_branch_enable(&cpu_hwcap_vector); > > /* There are 32 vector registers with vlenb length. */ > > + rvv_enable(); > > riscv_vsize = csr_read(CSR_VLENB) * 32; > > + rvv_disable(); > > } > > #endif > > Would it be better to enable this here, and then restore the original > state instead of calling rvv_disable? If it was enabled then maybe > something else is going to rely on that state? > > Maybe something like: > > prev = rvv_enable() > riscv_vsize = csr_read(CSR_VLENB) * 32; > rvv_restore(prev); > > Hi Ben, Thank you for reviewing this. The rvv won't be enabled here because we disable it in head.S at beginning and this stage is still doing some initialization work for rvv to set riscv_vsize, so we can assume that kernel mode vector should not be allowed to use vector yet. > > } > > diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c > > index 8d2e53ea25c1..1ecb6ec5c56d 100644 > > --- a/arch/riscv/kernel/kernel_mode_vector.c > > +++ b/arch/riscv/kernel/kernel_mode_vector.c > > @@ -71,15 +71,17 @@ static void put_cpu_vector_context(void) > > preempt_enable(); > > } > > > > -static void rvv_enable(void) > > +void rvv_enable(void) > > { > > csr_set(CSR_STATUS, SR_VS); > > } > > +EXPORT_SYMBOL(rvv_enable); > > > > -static void rvv_disable(void) > > +void rvv_disable(void) > > { > > csr_clear(CSR_STATUS, SR_VS); > > } > > +EXPORT_SYMBOL(rvv_disable); > > > > /* > > * kernel_rvv_begin(): obtain the CPU vector registers for use by the calling > > > > > -- > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius > > https://www.codethink.co.uk/privacy.html _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-11-16 13:14 UTC|newest] Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-09 9:48 [PATCH v9 00/17] riscv: Add vector ISA support Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 01/17] riscv: Separate patch for cflags and aflags Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 02/17] riscv: Rename __switch_to_aux -> fpu Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 04/17] riscv: Add new csr defines related to vector extension Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 05/17] riscv: Add vector feature to compile Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-12 0:54 ` kernel test robot 2021-11-12 0:54 ` kernel test robot 2021-11-12 0:54 ` kernel test robot 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 07/17] riscv: Reset vector register Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2022-01-04 6:02 ` Greentime Hu 2022-01-04 6:02 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 08/17] riscv: Add vector struct and assembler definitions Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-12-14 16:29 ` Palmer Dabbelt 2021-12-14 16:29 ` Palmer Dabbelt 2022-01-07 13:28 ` Greentime Hu 2022-01-07 13:28 ` Greentime Hu 2022-01-07 13:53 ` Jessica Clarke 2022-01-07 13:53 ` Jessica Clarke 2021-11-09 9:48 ` [PATCH v9 09/17] riscv: Add task switch support for vector Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-11 13:49 ` kernel test robot 2021-11-11 13:49 ` kernel test robot 2021-11-11 13:49 ` kernel test robot 2021-11-11 19:16 ` kernel test robot 2021-11-11 19:16 ` kernel test robot 2021-11-11 19:16 ` kernel test robot 2021-12-15 18:38 ` Palmer Dabbelt 2021-12-15 18:38 ` Palmer Dabbelt 2021-11-09 9:48 ` [PATCH v9 10/17] riscv: Add ptrace vector support Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 11/17] riscv: Add sigcontext save/restore for vector Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 12/17] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 13/17] riscv: Add support for kernel mode vector Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 14/17] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 15/17] riscv: Add vector extension XOR implementation Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu 2021-11-09 9:48 ` Greentime Hu 2021-11-10 10:38 ` Ben Dooks 2021-11-10 10:38 ` Ben Dooks 2021-11-16 13:14 ` Greentime Hu [this message] 2021-11-16 13:14 ` Greentime Hu 2021-11-09 9:48 ` [PATCH v9 17/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Greentime Hu 2021-11-09 9:48 ` Greentime Hu
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