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From: Greentime Hu <greentime.hu@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	aou@eecs.berkeley.edu
Subject: [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Tue,  9 Nov 2021 17:48:18 +0800	[thread overview]
Message-ID: <8652c476f08626d52f0412ca1a8427cfe7b4104f.1636362169.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1636362169.git.greentime.hu@sifive.com>

This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.

[guoren@linux.alibaba.com: add has_vector checking]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
---
 arch/riscv/kernel/cpufeature.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 7069e55335d0..8e7557980faf 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -21,6 +21,11 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 #ifdef CONFIG_FPU
 __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
 #endif
+#ifdef CONFIG_VECTOR
+#include <asm/vector.h>
+__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector);
+unsigned long riscv_vsize __read_mostly;
+#endif
 
 /**
  * riscv_isa_extension_base() - Get base extension word
@@ -149,4 +154,12 @@ void __init riscv_fill_hwcap(void)
 	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
 		static_branch_enable(&cpu_hwcap_fpu);
 #endif
+
+#ifdef CONFIG_VECTOR
+	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+		static_branch_enable(&cpu_hwcap_vector);
+		/* There are 32 vector registers with vlenb length. */
+		riscv_vsize = csr_read(CSR_VLENB) * 32;
+	}
+#endif
 }
-- 
2.31.1


WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	aou@eecs.berkeley.edu
Subject: [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Tue,  9 Nov 2021 17:48:18 +0800	[thread overview]
Message-ID: <8652c476f08626d52f0412ca1a8427cfe7b4104f.1636362169.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1636362169.git.greentime.hu@sifive.com>

This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.

[guoren@linux.alibaba.com: add has_vector checking]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
---
 arch/riscv/kernel/cpufeature.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 7069e55335d0..8e7557980faf 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -21,6 +21,11 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 #ifdef CONFIG_FPU
 __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
 #endif
+#ifdef CONFIG_VECTOR
+#include <asm/vector.h>
+__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector);
+unsigned long riscv_vsize __read_mostly;
+#endif
 
 /**
  * riscv_isa_extension_base() - Get base extension word
@@ -149,4 +154,12 @@ void __init riscv_fill_hwcap(void)
 	if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
 		static_branch_enable(&cpu_hwcap_fpu);
 #endif
+
+#ifdef CONFIG_VECTOR
+	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+		static_branch_enable(&cpu_hwcap_vector);
+		/* There are 32 vector registers with vlenb length. */
+		riscv_vsize = csr_read(CSR_VLENB) * 32;
+	}
+#endif
 }
-- 
2.31.1


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  parent reply	other threads:[~2021-11-09  9:50 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09  9:48 [PATCH v9 00/17] riscv: Add vector ISA support Greentime Hu
2021-11-09  9:48 ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 01/17] riscv: Separate patch for cflags and aflags Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 02/17] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 04/17] riscv: Add new csr defines related to vector extension Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 05/17] riscv: Add vector feature to compile Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-12  0:54   ` kernel test robot
2021-11-12  0:54     ` kernel test robot
2021-11-12  0:54     ` kernel test robot
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` Greentime Hu [this message]
2021-11-09  9:48   ` [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 07/17] riscv: Reset vector register Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2022-01-04  6:02     ` Greentime Hu
2022-01-04  6:02       ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 08/17] riscv: Add vector struct and assembler definitions Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2022-01-07 13:28     ` Greentime Hu
2022-01-07 13:28       ` Greentime Hu
2022-01-07 13:53       ` Jessica Clarke
2022-01-07 13:53         ` Jessica Clarke
2021-11-09  9:48 ` [PATCH v9 09/17] riscv: Add task switch support for vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-11 13:49   ` kernel test robot
2021-11-11 13:49     ` kernel test robot
2021-11-11 13:49     ` kernel test robot
2021-11-11 19:16   ` kernel test robot
2021-11-11 19:16     ` kernel test robot
2021-11-11 19:16     ` kernel test robot
2021-12-15 18:38   ` Palmer Dabbelt
2021-12-15 18:38     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 10/17] riscv: Add ptrace vector support Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 11/17] riscv: Add sigcontext save/restore for vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 12/17] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 13/17] riscv: Add support for kernel mode vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 14/17] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 15/17] riscv: Add vector extension XOR implementation Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-10 10:38   ` Ben Dooks
2021-11-10 10:38     ` Ben Dooks
2021-11-16 13:14     ` Greentime Hu
2021-11-16 13:14       ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 17/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Greentime Hu
2021-11-09  9:48   ` Greentime Hu

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