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From: Greentime Hu <greentime.hu@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	aou@eecs.berkeley.edu
Subject: [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension
Date: Tue,  9 Nov 2021 17:48:15 +0800	[thread overview]
Message-ID: <802edef897b4bd40f3ebc2cb47c02b8e2f61a666.1636362169.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1636362169.git.greentime.hu@sifive.com>

From: Guo Ren <ren_guo@c-sky.com>

Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/include/uapi/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index 46dc3f5ee99f..c52bb7bbbabe 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
 #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
 #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
 #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
 
 #endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d959d207a40d..7069e55335d0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -73,6 +73,7 @@ void __init riscv_fill_hwcap(void)
 	isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
 	isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+	isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
 
 	elf_hwcap = 0;
 
-- 
2.31.1


WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	aou@eecs.berkeley.edu
Subject: [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension
Date: Tue,  9 Nov 2021 17:48:15 +0800	[thread overview]
Message-ID: <802edef897b4bd40f3ebc2cb47c02b8e2f61a666.1636362169.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1636362169.git.greentime.hu@sifive.com>

From: Guo Ren <ren_guo@c-sky.com>

Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/include/uapi/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index 46dc3f5ee99f..c52bb7bbbabe 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
 #define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))
 #define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))
 #define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))
 
 #endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d959d207a40d..7069e55335d0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -73,6 +73,7 @@ void __init riscv_fill_hwcap(void)
 	isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
 	isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
 	isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+	isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
 
 	elf_hwcap = 0;
 
-- 
2.31.1


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  parent reply	other threads:[~2021-11-09  9:50 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09  9:48 [PATCH v9 00/17] riscv: Add vector ISA support Greentime Hu
2021-11-09  9:48 ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 01/17] riscv: Separate patch for cflags and aflags Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 02/17] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` Greentime Hu [this message]
2021-11-09  9:48   ` [PATCH v9 03/17] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 04/17] riscv: Add new csr defines related to vector extension Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 05/17] riscv: Add vector feature to compile Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-12  0:54   ` kernel test robot
2021-11-12  0:54     ` kernel test robot
2021-11-12  0:54     ` kernel test robot
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 06/17] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 07/17] riscv: Reset vector register Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2022-01-04  6:02     ` Greentime Hu
2022-01-04  6:02       ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 08/17] riscv: Add vector struct and assembler definitions Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-12-14 16:29   ` Palmer Dabbelt
2021-12-14 16:29     ` Palmer Dabbelt
2022-01-07 13:28     ` Greentime Hu
2022-01-07 13:28       ` Greentime Hu
2022-01-07 13:53       ` Jessica Clarke
2022-01-07 13:53         ` Jessica Clarke
2021-11-09  9:48 ` [PATCH v9 09/17] riscv: Add task switch support for vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-11 13:49   ` kernel test robot
2021-11-11 13:49     ` kernel test robot
2021-11-11 13:49     ` kernel test robot
2021-11-11 19:16   ` kernel test robot
2021-11-11 19:16     ` kernel test robot
2021-11-11 19:16     ` kernel test robot
2021-12-15 18:38   ` Palmer Dabbelt
2021-12-15 18:38     ` Palmer Dabbelt
2021-11-09  9:48 ` [PATCH v9 10/17] riscv: Add ptrace vector support Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 11/17] riscv: Add sigcontext save/restore for vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 12/17] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 13/17] riscv: Add support for kernel mode vector Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 14/17] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 15/17] riscv: Add vector extension XOR implementation Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2021-11-09  9:48   ` Greentime Hu
2021-11-10 10:38   ` Ben Dooks
2021-11-10 10:38     ` Ben Dooks
2021-11-16 13:14     ` Greentime Hu
2021-11-16 13:14       ` Greentime Hu
2021-11-09  9:48 ` [PATCH v9 17/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Greentime Hu
2021-11-09  9:48   ` Greentime Hu

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