From: Conor Dooley <conor.dooley@microchip.com> To: <mturquette@baylibre.com>, <sboyd@kernel.org>, <aou@eecs.berkeley.edu>, <paul.walmsley@sifive.com>, <palmer@rivosinc.com>, <a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>, <robh+dt@kernel.org>, <krzk+dt@kernel.org> Cc: <daire.mcnamara@microchip.com>, <linux-rtc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Conor Dooley <conor.dooley@microchip.com>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Subject: [PATCH v3 4/9] dt-bindings: clk: mpfs document msspll dri registers Date: Wed, 13 Apr 2022 08:58:31 +0100 [thread overview] Message-ID: <20220413075835.3354193-5-conor.dooley@microchip.com> (raw) In-Reply-To: <20220413075835.3354193-1-conor.dooley@microchip.com> As there are two sections of registers that are responsible for clock configuration on the PolarFire SoC: add the dynamic reconfiguration interface section to the binding & describe what each of the sections are used for. Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/clock/microchip,mpfs.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 0c15afa2214c..016a4f378b9b 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -22,7 +22,16 @@ properties: const: microchip,mpfs-clkcfg reg: - maxItems: 1 + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -51,7 +60,7 @@ examples: #size-cells = <2>; clkcfg: clock-controller@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&ref>; #clock-cells = <1>; }; -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: <mturquette@baylibre.com>, <sboyd@kernel.org>, <aou@eecs.berkeley.edu>, <paul.walmsley@sifive.com>, <palmer@rivosinc.com>, <a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>, <robh+dt@kernel.org>, <krzk+dt@kernel.org> Cc: <daire.mcnamara@microchip.com>, <linux-rtc@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Conor Dooley <conor.dooley@microchip.com>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Subject: [PATCH v3 4/9] dt-bindings: clk: mpfs document msspll dri registers Date: Wed, 13 Apr 2022 08:58:31 +0100 [thread overview] Message-ID: <20220413075835.3354193-5-conor.dooley@microchip.com> (raw) In-Reply-To: <20220413075835.3354193-1-conor.dooley@microchip.com> As there are two sections of registers that are responsible for clock configuration on the PolarFire SoC: add the dynamic reconfiguration interface section to the binding & describe what each of the sections are used for. Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/clock/microchip,mpfs.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 0c15afa2214c..016a4f378b9b 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -22,7 +22,16 @@ properties: const: microchip,mpfs-clkcfg reg: - maxItems: 1 + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -51,7 +60,7 @@ examples: #size-cells = <2>; clkcfg: clock-controller@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&ref>; #clock-cells = <1>; }; -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-04-13 8:02 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-13 7:58 [PATCH v3 0/9] More PolarFire SoC Fixes for 5.18 Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-13 7:58 ` [PATCH v3 1/9] clk: microchip: mpfs: fix parents for FIC clocks Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 17:58 ` Conor Dooley 2022-04-23 17:58 ` Conor Dooley 2022-04-13 7:58 ` [PATCH v3 2/9] clk: microchip: mpfs: mark CLK_ATHENA as critical Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 1:41 ` Stephen Boyd 2022-04-13 7:58 ` [PATCH v3 3/9] riscv: dts: microchip: fix usage of fic clocks on mpfs Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 1:41 ` Stephen Boyd 2022-04-13 7:58 ` Conor Dooley [this message] 2022-04-13 7:58 ` [PATCH v3 4/9] dt-bindings: clk: mpfs document msspll dri registers Conor Dooley 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 1:41 ` Stephen Boyd 2022-04-13 7:58 ` [PATCH v3 5/9] dt-bindings: clk: mpfs: add defines for two new clocks Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-19 11:59 ` Krzysztof Kozlowski 2022-04-19 11:59 ` Krzysztof Kozlowski 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 1:41 ` Stephen Boyd 2022-04-13 7:58 ` [PATCH v3 6/9] dt-bindings: rtc: add refclk to mpfs-rtc Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 1:41 ` Stephen Boyd 2022-04-13 7:58 ` [PATCH v3 7/9] clk: microchip: mpfs: re-parent the configurable clocks Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-23 1:41 ` Stephen Boyd 2022-04-23 1:41 ` Stephen Boyd 2022-04-13 7:58 ` [PATCH v3 8/9] clk: microchip: mpfs: add RTCREF clock control Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-23 1:42 ` Stephen Boyd 2022-04-23 1:42 ` Stephen Boyd 2022-04-13 7:58 ` [PATCH v3 9/9] riscv: dts: microchip: reparent mpfs clocks Conor Dooley 2022-04-13 7:58 ` Conor Dooley 2022-04-23 1:42 ` Stephen Boyd 2022-04-23 1:42 ` Stephen Boyd 2022-04-22 19:39 ` [PATCH v3 0/9] More PolarFire SoC Fixes for 5.18 Palmer Dabbelt 2022-04-22 19:39 ` Palmer Dabbelt 2022-04-22 19:59 ` Conor Dooley 2022-04-22 19:59 ` Conor Dooley 2022-04-22 21:00 ` Stephen Boyd 2022-04-22 21:00 ` Stephen Boyd 2022-04-22 21:10 ` Conor Dooley 2022-04-22 21:10 ` Conor Dooley 2022-04-22 21:40 ` Palmer Dabbelt 2022-04-22 21:40 ` Palmer Dabbelt 2022-04-22 21:52 ` Rob Herring 2022-04-22 21:52 ` Rob Herring 2022-04-22 22:32 ` Conor Dooley 2022-04-22 22:32 ` Conor Dooley
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