[PULL v2 00/31] riscv-to-apply queue

* [PULL v2 00/31] riscv-to-apply queue
@ 2022-04-22  0:36 Alistair Francis
  2022-04-22  0:36 ` [PULL v2 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
                   ` (31 more replies)
  0 siblings, 32 replies; 35+ messages in thread
From: Alistair Francis @ 2022-04-22  0:36 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit da5006445a92bb7801f54a93452fac63ca2f634c:

  Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2022-04-21 15:16:52 -0700)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220422-1

for you to fetch changes up to faee5441a038898f64b335dbaecab102ba406552:

  hw/riscv: boot: Support 64bit fdt address. (2022-04-22 10:35:16 +1000)

----------------------------------------------------------------
First RISC-V PR for QEMU 7.1

 * Add support for Ibex SPI to OpenTitan
 * Add support for privileged spec version 1.12.0
 * Use privileged spec version 1.12.0 for virt machine by default
 * Allow software access to MIP SEIP
 * Add initial support for the Sdtrig extension
 * Optimisations for vector extensions
 * Improvements to the misa ISA string
 * Add isa extenstion strings to the device tree
 * Don't allow `-bios` options with KVM machines
 * Fix NAPOT range computation overflow
 * Fix DT property mmu-type when CPU mmu option is disabled
 * Make RISC-V ACLINT mtime MMIO register writable
 * Add and enable native debug feature
 * Support 64bit fdt address.

----------------------------------------------------------------
Alistair Francis (2):
      target/riscv: cpu: Fixup indentation
      target/riscv: Allow software access to MIP SEIP

Atish Patra (7):
      target/riscv: Define simpler privileged spec version numbering
      target/riscv: Add the privileged spec version 1.12.0
      target/riscv: Introduce privilege version field in the CSR ops.
      target/riscv: Add support for mconfigptr
      target/riscv: Add *envcfg* CSRs support
      target/riscv: Enable privileged spec version 1.12
      target/riscv: Add isa extenstion strings to the device tree

Bin Meng (7):
      target/riscv: Add initial support for the Sdtrig extension
      target/riscv: debug: Implement debug related TCGCPUOps
      target/riscv: cpu: Add a config option for native debug
      target/riscv: csr: Hook debug CSR read/write
      target/riscv: machine: Add debug state description
      target/riscv: cpu: Enable native debug feature
      hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()

Dylan Jhong (1):
      hw/riscv: boot: Support 64bit fdt address.

Frank Chang (3):
      hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
      hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
      hw/intc: Make RISC-V ACLINT mtime MMIO register writable

Jim Shu (1):
      hw/intc: riscv_aclint: Add reset function of ACLINT devices

Nicolas Pitre (1):
      target/riscv/pmp: fix NAPOT range computation overflow

Niklas Cassel (1):
      hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled

Ralf Ramsauer (1):
      hw/riscv: virt: Exit if the user provided -bios in combination with KVM

Richard Henderson (1):
      target/riscv: Use cpu_loop_exit_restore directly from mmu faults

Tsukasa OI (1):
      target/riscv: misa to ISA string conversion fix

Weiwei Li (3):
      target/riscv: optimize condition assign for scale < 0
      target/riscv: optimize helper for vmv<nr>r.v
      target/riscv: fix start byte for vmv<nf>r.v when vstart != 0

Wilfred Mallawa (2):
      hw/ssi: Add Ibex SPI device model
      riscv: opentitan: Connect opentitan SPI Host

 include/hw/core/tcg-cpu-ops.h           |   1 +
 include/hw/intc/riscv_aclint.h          |   1 +
 include/hw/riscv/boot.h                 |   4 +-
 include/hw/riscv/opentitan.h            |  30 +-
 include/hw/ssi/ibex_spi_host.h          |  94 +++++
 target/riscv/cpu.h                      |  40 ++-
 target/riscv/cpu_bits.h                 |  40 +++
 target/riscv/debug.h                    | 114 ++++++
 target/riscv/helper.h                   |   5 +-
 hw/intc/riscv_aclint.c                  | 144 ++++++--
 hw/riscv/boot.c                         |  12 +-
 hw/riscv/opentitan.c                    |  36 +-
 hw/riscv/virt.c                         |  24 +-
 hw/ssi/ibex_spi_host.c                  | 612 ++++++++++++++++++++++++++++++++
 target/riscv/cpu.c                      | 120 ++++++-
 target/riscv/cpu_helper.c               |  10 +-
 target/riscv/csr.c                      | 282 +++++++++++++--
 target/riscv/debug.c                    | 441 +++++++++++++++++++++++
 target/riscv/machine.c                  |  55 +++
 target/riscv/pmp.c                      |  14 +-
 target/riscv/vector_helper.c            |  31 +-
 target/riscv/insn_trans/trans_rvv.c.inc |  25 +-
 hw/ssi/meson.build                      |   1 +
 hw/ssi/trace-events                     |   7 +
 target/riscv/meson.build                |   1 +
 25 files changed, 1971 insertions(+), 173 deletions(-)
 create mode 100644 include/hw/ssi/ibex_spi_host.h
 create mode 100644 target/riscv/debug.h
 create mode 100644 hw/ssi/ibex_spi_host.c
 create mode 100644 target/riscv/debug.c

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