[PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[David Zhang]

changes in v2:
-----------------------
- set vsc_packet_rev2 for PSR1 which is safer
- add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
- add DC/DM change related to amdgpu PSR-SU-RC


David Zhang (18):
  drm/amd/display: align dmub cmd header to latest dmub FW to support
    PSR-SU
  drm/amd/display: feed PSR-SU as psr version to dmub FW
  drm/amd/display: combine dirty rectangles in DMUB FW
  drm/amd/display: update GSP1 generic info packet for PSRSU
  drm/amd/display: revise Start/End SDP data
  drm/amd/display: program PSR2 DPCD Configuration
  drm/amd/display: Passing Y-granularity to dmub fw
  drm/amd/display: Set default value of line_capture_indication
  drm/amd/display: add vline time in micro sec to PSR context
  drm/amd/display: fix system hang when PSR exits
  drm/amd/display: Set PSR level to enable ALPM by default
  drm/amd/display: use HW lock mgr for PSR-SU
  drm/amd/display: PSRSU+DSC WA for specific TCON
  drm/amd/display: add shared helpers to update psr config fields to
    power module
  drm/amd/display: calculate psr config settings in runtime in DM
  drm/amd/display: update cursor position to DMUB FW
  drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
    support
  drm/amd/display: PSR-SU rate control support in DC

Leo Li (1):
  drm/amd/display: Implement MPO PSR SU

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
 drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
 .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
 .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
 .../amd/display/include/ddc_service_types.h   |   1 +
 .../display/modules/info_packet/info_packet.c |  29 +-
 .../amd/display/modules/power/power_helpers.c |  84 ++++++
 .../amd/display/modules/power/power_helpers.h |   6 +
 21 files changed, 887 insertions(+), 19 deletions(-)

-- 
2.25.1

[PATCH v2 01/19] drm/amd/display: align dmub cmd header to latest dmub FW to support PSR-SU

[David Zhang]

[why]
PSR-SU is implemented in upstreamed dmub FW but not enabled on
DM and DC. We'd add necessary and missing definitions in dmub
cmd header to align w/ the up-to-date DMUB FW for PSR-SU support.

[how]
Add definitions and items below into dmub cmd header:
- DMUB psr version enumeration for PSR-SU
- dirty rectangle structure
- psr debug flag of forcing full frame update
- dmub command of updating dirty rectangle and cursor infor
- dmub psr command type of setting sink vtotal in PSR active
- dmub psr su debug flags structure
- dmub cmd structure for
  - updating dirty rectangle
  - cursor infor
  - setting sink vtotal
- dmub ringbuffer command items

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
 1 file changed, 245 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 385c28238beb..c6d9e9d0acab 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -101,6 +101,11 @@
 /* Trace buffer offset for entry */
 #define TRACE_BUFFER_ENTRY_OFFSET  16
 
+/**
+ * Maximum number of dirty rects supported by FW.
+ */
+#define DMUB_MAX_DIRTY_RECTS 3
+
 /**
  *
  * PSR control version legacy
@@ -165,6 +170,31 @@ union dmub_addr {
 	uint64_t quad_part; /*<< 64 bit address */
 };
 
+/**
+ * Dirty rect definition.
+ */
+struct dmub_rect {
+	/**
+	 * Dirty rect x offset.
+	 */
+	uint32_t x;
+
+	/**
+	 * Dirty rect y offset.
+	 */
+	uint32_t y;
+
+	/**
+	 * Dirty rect width.
+	 */
+	uint32_t width;
+
+	/**
+	 * Dirty rect height.
+	 */
+	uint32_t height;
+};
+
 /**
  * Flags that can be set by driver to change some PSR behaviour.
  */
@@ -177,6 +207,12 @@ union dmub_psr_debug_flags {
 		 * Enable visual confirm in FW.
 		 */
 		uint32_t visual_confirm : 1;
+
+		/**
+		 * Force all selective updates to bw full frame updates.
+		 */
+		uint32_t force_full_frame_update : 1;
+
 		/**
 		 * Use HW Lock Mgr object to do HW locking in FW.
 		 */
@@ -616,6 +652,14 @@ enum dmub_cmd_type {
 	 * Command type used for all ABM commands.
 	 */
 	DMUB_CMD__ABM = 66,
+	/**
+	 * Command type used to update dirty rects in FW.
+	 */
+	DMUB_CMD__UPDATE_DIRTY_RECT = 67,
+	/**
+	 * Command type used to update cursor info in FW.
+	 */
+	DMUB_CMD__UPDATE_CURSOR_INFO = 68,
 	/**
 	 * Command type used for HW locking in FW.
 	 */
@@ -1419,6 +1463,10 @@ enum dmub_cmd_psr_type {
 	 * Forces PSR enabled until an explicit PSR disable call.
 	 */
 	DMUB_CMD__PSR_FORCE_STATIC		= 5,
+	/**
+	 * Set vtotal in psr active for FreeSync PSR.
+	 */
+	DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
 	/**
 	 * Set PSR power option
 	 */
@@ -1433,6 +1481,10 @@ enum psr_version {
 	 * PSR version 1.
 	 */
 	PSR_VERSION_1				= 0,
+	/**
+	 * Freesync PSR SU.
+	 */
+	PSR_VERSION_SU_1			= 1,
 	/**
 	 * PSR not supported.
 	 */
@@ -1600,9 +1652,15 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint8_t frame_cap_ind;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * Granularity of Y offset supported by sink.
 	 */
-	uint8_t pad[2];
+	uint8_t su_y_granularity;
+	/**
+	 * Indicates whether sink should start capturing
+	 * immediately following active scan line,
+	 * or starting with the 2nd active scan line.
+	 */
+	uint8_t line_capture_indication;
 	/**
 	 * Multi-display optimizations are implemented on certain ASICs.
 	 */
@@ -1613,9 +1671,13 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint16_t init_sdp_deadline;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
+	 */
+	uint8_t rate_control_caps ;
+	/*
+	 * Force PSRSU always doing full frame update
 	 */
-	uint16_t pad2;
+	uint8_t force_ffu_mode;
 	/**
 	 * Length of each horizontal line in us.
 	 */
@@ -1807,6 +1869,164 @@ struct dmub_rb_cmd_psr_force_static {
 	struct dmub_cmd_psr_force_static_data psr_force_static_data;
 };
 
+/**
+ * PSR SU debug flags.
+ */
+union dmub_psr_su_debug_flags {
+	/**
+	 * PSR SU debug flags.
+	 */
+	struct {
+		/**
+		 * Update dirty rect in SW only.
+		 */
+		uint8_t update_dirty_rect_only : 1;
+		/**
+		 * Reset the cursor/plane state before processing the call.
+		 */
+		uint8_t reset_state : 1;
+	} bitfields;
+
+	/**
+	 * Union for debug flags.
+	 */
+	uint32_t u32All;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
+ * This triggers a selective update for PSR SU.
+ */
+struct dmub_cmd_update_dirty_rect_data {
+	/**
+	 * Dirty rects from OS.
+	 */
+	struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
+	/**
+	 * PSR SU debug flags.
+	 */
+	union dmub_psr_su_debug_flags debug_flags;
+	/**
+	 * OTG HW instance.
+	 */
+	uint8_t pipe_idx;
+	/**
+	 * Number of dirty rects.
+	 */
+	uint8_t dirty_rect_count;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+};
+
+/**
+ * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
+ */
+struct dmub_rb_cmd_update_dirty_rect {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
+	 */
+	struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
+ */
+struct dmub_cmd_update_cursor_info_data {
+	/**
+	 * Cursor dirty rects.
+	 */
+	struct dmub_rect cursor_rect;
+	/**
+	 * PSR SU debug flags.
+	 */
+	union dmub_psr_su_debug_flags debug_flags;
+	/**
+	 * Cursor enable/disable.
+	 */
+	uint8_t enable;
+	/**
+	 * OTG HW instance.
+	 */
+	uint8_t pipe_idx;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+};
+/**
+ * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
+ */
+struct dmub_rb_cmd_update_cursor_info {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
+	 */
+	struct dmub_cmd_update_cursor_info_data update_cursor_info_data;
+};
+
+/**
+ * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+ */
+struct dmub_cmd_psr_set_vtotal_data {
+	/**
+	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
+	 */
+	uint16_t psr_vtotal_idle;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/*
+	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
+	 */
+	uint16_t psr_vtotal_su;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad2[2];
+};
+
+/**
+ * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+ */
+struct dmub_rb_cmd_psr_set_vtotal {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+	 */
+	struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
+};
+
 /**
  * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
  */
@@ -1917,6 +2137,10 @@ enum hw_lock_client {
 	 * Driver is the client of HW Lock Manager.
 	 */
 	HW_LOCK_CLIENT_DRIVER = 0,
+	/**
+	 * PSR SU is the client of HW Lock Manager.
+	 */
+	HW_LOCK_CLIENT_PSR_SU		= 1,
 	/**
 	 * Invalid client.
 	 */
@@ -2620,7 +2844,6 @@ struct dmub_rb_cmd_get_usbc_cable_id {
  * union dmub_rb_cmd - DMUB inbox command.
  */
 union dmub_rb_cmd {
-	struct dmub_rb_cmd_lock_hw lock_hw;
 	/**
 	 * Elements shared with all commands.
 	 */
@@ -2681,6 +2904,23 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
 	 */
 	struct dmub_rb_cmd_psr_force_static psr_force_static;
+	/**
+	 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
+	 */
+	struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
+	/**
+	 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
+	 */
+	struct dmub_rb_cmd_update_cursor_info update_cursor_info;
+	/**
+	 * Definition of a DMUB_CMD__HW_LOCK command.
+	 * Command is used by driver and FW.
+	 */
+	struct dmub_rb_cmd_lock_hw lock_hw;
+	/**
+	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
+	 */
+	struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
 	/**
 	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
 	 */
-- 
2.25.1

[PATCH v2 02/19] drm/amd/display: feed PSR-SU as psr version to dmub FW

[David Zhang]

[why & how]
set psr version as PSR-SU in kernel-FW interface function to ensure
the correct dmub command parameter is fed into FW.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 1d4f0c45b536..f1411a22cf1e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -133,6 +133,9 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 	case DC_PSR_VERSION_1:
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
 		break;
+	case DC_PSR_VERSION_SU_1:
+		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1;
+		break;
 	case DC_PSR_VERSION_UNSUPPORTED:
 	default:
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
-- 
2.25.1

[PATCH v2 03/19] drm/amd/display: combine dirty rectangles in DMUB FW

[David Zhang]

[why]
In PSR-SU design, the DMUB FW handles the combination of multiple
dirty rectangles.

[how]
- create DC dmub update dirty rectangle helper which sends the
  dirty rectangles per pipe from DC to DMUB, and DMUB FW will
  handle to combine the dirty RECTs
- call the helper from DC commit plane update function.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 54 ++++++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  5 ++
 2 files changed, 59 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e41a48f596a3..a4a5a78e82f3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -72,6 +72,9 @@
 #include "dmub/dmub_srv.h"
 
 #include "i2caux_interface.h"
+
+#include "dce/dmub_psr.h"
+
 #include "dce/dmub_hw_lock_mgr.h"
 
 #include "dc_trace.h"
@@ -2824,6 +2827,55 @@ static void commit_planes_do_stream_update(struct dc *dc,
 	}
 }
 
+void dc_dmub_update_dirty_rect(struct dc *dc,
+			       int surface_count,
+			       struct dc_stream_state *stream,
+			       struct dc_surface_update *srf_updates,
+			       struct dc_state *context)
+{
+	union dmub_rb_cmd cmd;
+	struct dc_context *dc_ctx = dc->ctx;
+	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
+	unsigned int i, j;
+
+	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+		return;
+
+	memset(&cmd, 0x0, sizeof(cmd));
+	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
+	cmd.update_dirty_rect.header.sub_type = 0;
+	cmd.update_dirty_rect.header.payload_bytes =
+		sizeof(cmd.update_dirty_rect) -
+		sizeof(cmd.update_dirty_rect.header);
+	update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
+	for (i = 0; i < surface_count; i++) {
+		struct dc_plane_state *plane_state = srf_updates[i].surface;
+		const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
+
+		if (!srf_updates[i].surface || !flip_addr)
+			continue;
+		/* Do not send in immediate flip mode */
+		if (srf_updates[i].surface->flip_immediate)
+			continue;
+
+		update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
+		memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
+				sizeof(flip_addr->dirty_rects));
+		for (j = 0; j < dc->res_pool->pipe_count; j++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+
+			if (pipe_ctx->stream != stream)
+				continue;
+			if (pipe_ctx->plane_state != plane_state)
+				continue;
+
+			update_dirty_rect->pipe_idx = j;
+			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
+			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
+		}
+	}
+}
+
 static void commit_planes_for_stream(struct dc *dc,
 		struct dc_surface_update *srf_updates,
 		int surface_count,
@@ -2910,6 +2962,8 @@ static void commit_planes_for_stream(struct dc *dc,
 		 */
 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
 
+	dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
+
 	// Stream updates
 	if (stream_update)
 		commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 58941f4defb3..58036469c62a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -529,4 +529,9 @@ bool dc_stream_get_crtc_position(struct dc *dc,
 
 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);
 
+void dc_dmub_update_dirty_rect(struct dc *dc,
+			       int surface_count,
+			       struct dc_stream_state *stream,
+			       struct dc_surface_update *srf_updates,
+			       struct dc_state *context);
 #endif /* DC_STREAM_H_ */
-- 
2.25.1

[PATCH v2 04/19] drm/amd/display: update GSP1 generic info packet for PSRSU

[David Zhang]

[why & how]
Based on PSRSU specification, every selective update frame need to use
two SDP to indicate the frame active range. So we occupy another GSP1
for PSRSU execution.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 .../display/dc/dcn30/dcn30_dio_stream_encoder.c   | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
index a04ca4a98392..e40f01b596ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
@@ -419,6 +419,21 @@ static void enc3_stream_encoder_update_dp_info_packets(
 				&info_frame->vsc,
 				true);
 	}
+	/* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
+	 * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
+	 * In addition, currently the driver check the valid bit then update and
+	 * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
+	 * while entering PSR-SU mode. So we need another parameter(e.g. send)
+	 * in dc_info_packet to indicate which infopacket should be enabled by
+	 * default here.
+	 */
+	if (info_frame->vsc.valid) {
+		enc->vpg->funcs->update_generic_info_packet(
+				enc->vpg,
+				1,  /* packetIndex */
+				&info_frame->vsc,
+				true);
+	}
 	if (info_frame->spd.valid) {
 		enc->vpg->funcs->update_generic_info_packet(
 				enc->vpg,
-- 
2.25.1

[PATCH v2 05/19] drm/amd/display: revise Start/End SDP data

[David Zhang]

[why & how]
We need to implement the VSC packet rev4 that is required by PSRSU.

Follow the eDP 1.5 spec pg. 257

changes in v2:
-------------------
- set vsc packet rev2 for PSR1

Cc: Chandan Vurdigerenataraj <chandan.vurdigerenataraj@amd.com>

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 .../display/modules/info_packet/info_packet.c | 29 +++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
index 79bc207415bc..27ceba9d6d65 100644
--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
@@ -145,8 +145,10 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
 		stereo3dSupport = true;
 	}
 
-	/*VSC packet set to 2 when DP revision >= 1.2*/
-	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
+	/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		vsc_packet_revision = vsc_packet_rev4;
+	else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
 		vsc_packet_revision = vsc_packet_rev2;
 
 	/* Update to revision 5 for extended colorimetry support */
@@ -159,6 +161,29 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
 	if (vsc_packet_revision == vsc_packet_undefined)
 		return;
 
+	if (vsc_packet_revision == vsc_packet_rev4) {
+		/* Secondary-data Packet ID = 0*/
+		info_packet->hb0 = 0x00;
+		/* 07h - Packet Type Value indicating Video
+		 * Stream Configuration packet
+		 */
+		info_packet->hb1 = 0x07;
+		/* 04h = VSC SDP supporting 3D stereo + PSR/PSR2 + Y-coordinate
+		 * (applies to eDP v1.4 or higher).
+		 */
+		info_packet->hb2 = 0x04;
+		/* 0Eh = VSC SDP supporting 3D stereo + PSR2
+		 * (HB2 = 04h), with Y-coordinate of first scan
+		 * line of the SU region
+		 */
+		info_packet->hb3 = 0x0E;
+
+		for (i = 0; i < 28; i++)
+			info_packet->sb[i] = 0;
+
+		info_packet->valid = true;
+	}
+
 	if (vsc_packet_revision == vsc_packet_rev2) {
 		/* Secondary-data Packet ID = 0*/
 		info_packet->hb0 = 0x00;
-- 
2.25.1

[PATCH v2 06/19] drm/amd/display: program PSR2 DPCD Configuration

[David Zhang]

[Why]
To support PSR2 Source DPCD configuration

[How]
Update the PSR2 Source DPCD settings while the PSR2 enabled

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 23 ++++++++++++++++++-
 .../drm/amd/display/dc/inc/hw/link_encoder.h  | 13 ++++++++++-
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 67ef357e5798..a391a58252bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3175,6 +3175,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 	unsigned int panel_inst;
 	/* updateSinkPsrDpcdConfig*/
 	union dpcd_psr_configuration psr_configuration;
+	union dpcd_alpm_configuration alpm_configuration;
 
 	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
@@ -3200,7 +3201,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 			psr_config->psr_frame_capture_indication_req;
 
 	/* Check for PSR v2*/
-	if (psr_config->psr_version == 0x2) {
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
 		/* For PSR v2 selective update.
 		 * Indicates whether sink should start capturing
 		 * immediately following active scan line,
@@ -3211,6 +3212,14 @@ bool dc_link_setup_psr(struct dc_link *link,
 		 * IRQ_HPD when CRC mismatch is detected.
 		 */
 		psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
+		/* For PSR v2, set the bit when the Source device will
+		 * be enabling PSR2 operation.
+		 */
+		psr_configuration.bits.ENABLE_PSR2    = 1;
+		/* For PSR v2, the Sink device must be able to receive
+		 * SU region updates early in the frame time.
+		 */
+		psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
 	}
 
 	dm_helpers_dp_write_dpcd(
@@ -3220,6 +3229,18 @@ bool dc_link_setup_psr(struct dc_link *link,
 		&psr_configuration.raw,
 		sizeof(psr_configuration.raw));
 
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
+		memset(&alpm_configuration, 0, sizeof(alpm_configuration));
+
+		alpm_configuration.bits.ENABLE = 1;
+		dm_helpers_dp_write_dpcd(
+			link->ctx,
+			link,
+			DP_RECEIVER_ALPM_CONFIG,
+			&alpm_configuration.raw,
+			sizeof(alpm_configuration.raw));
+	}
+
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
 	psr_context->transmitterId = link->link_enc->transmitter;
 	psr_context->engineId = link->link_enc->preferred_engine;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 2013a70603ae..66132f3cac42 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -85,7 +85,18 @@ union dpcd_psr_configuration {
 		unsigned char LINE_CAPTURE_INDICATION   : 1;
 		/* For eDP 1.4, PSR v2*/
 		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
-		unsigned char RESERVED                  : 2;
+		unsigned char ENABLE_PSR2               : 1;
+		/* For eDP 1.5, PSR v2 w/ early transport */
+		unsigned char EARLY_TRANSPORT_ENABLE    : 1;
+	} bits;
+	unsigned char raw;
+};
+
+union dpcd_alpm_configuration {
+	struct {
+		unsigned char ENABLE                    : 1;
+		unsigned char IRQ_HPD_ENABLE            : 1;
+		unsigned char RESERVED                  : 6;
 	} bits;
 	unsigned char raw;
 };
-- 
2.25.1

[PATCH v2 07/19] drm/amd/display: Passing Y-granularity to dmub fw

[David Zhang]

[Why]
The Y-granularity panel parameter indicate the grid
pattern granularity in the Y direction for PSRSU.

[How]
Send the Y-granularity data by PSR_COPY_SETTINGS dmub command.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++
 drivers/gpu/drm/amd/display/dc/dc_types.h     | 8 ++++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 6 ++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a391a58252bc..d972dea21b2d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3239,6 +3239,10 @@ bool dc_link_setup_psr(struct dc_link *link,
 			DP_RECEIVER_ALPM_CONFIG,
 			&alpm_configuration.raw,
 			sizeof(alpm_configuration.raw));
+		psr_context->su_granularity_required =
+			psr_config->su_granularity_required;
+		psr_context->su_y_granularity =
+			psr_config->su_y_granularity;
 	}
 
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 2ba9f528c0fe..d61ea3e2bfbf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -672,6 +672,10 @@ struct psr_config {
 	unsigned int psr_sdp_transmit_line_num_deadline;
 	bool allow_smu_optimizations;
 	bool allow_multi_disp_optimizations;
+	/* Panel self refresh 2 selective update granularity required */
+	bool su_granularity_required;
+	/* psr2 selective update y granularity capability */
+	uint8_t su_y_granularity;
 };
 
 union dmcu_psr_level {
@@ -775,6 +779,10 @@ struct psr_context {
 	unsigned int frame_delay;
 	bool allow_smu_optimizations;
 	bool allow_multi_disp_optimizations;
+	/* Panel self refresh 2 selective update granularity required */
+	bool su_granularity_required;
+	/* psr2 selective update y granularity capability */
+	uint8_t su_y_granularity;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index f1411a22cf1e..6883dd5b80d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -333,6 +333,12 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.u32All = 0;
 	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
+
+	if (psr_context->su_granularity_required == 0)
+		copy_settings_data->su_y_granularity = 0;
+	else
+		copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
+
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
-- 
2.25.1

[PATCH v2 08/19] drm/amd/display: Set default value of line_capture_indication

[David Zhang]

[Why & how]
We only support line capture indication as 0 for PSRSU

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 6883dd5b80d6..bc4943205bce 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -339,6 +339,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	else
 		copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
 
+	copy_settings_data->line_capture_indication = 0;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
-- 
2.25.1

[PATCH v2 09/19] drm/amd/display: add vline time in micro sec to PSR context

[David Zhang]

[why]
The current PSR SU programming margin is fixed base on FHD 60HZ
panel. If the resolution and refresh rate become higher, the time
of current margin might not cover the programming SU time.

[how]
Notice that the programming SU time is the same among different
panels.

Instead of fixing the margin with target line number, change the
margin unit to micro second which indicate the time needed for
programming SU. Then FW set the margin line number base on the
line time and margin time.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 ++
 drivers/gpu/drm/amd/display/dc/dc_types.h     | 2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d972dea21b2d..1ae48fa65e64 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3243,6 +3243,8 @@ bool dc_link_setup_psr(struct dc_link *link,
 			psr_config->su_granularity_required;
 		psr_context->su_y_granularity =
 			psr_config->su_y_granularity;
+		psr_context->line_time_in_us =
+			psr_config->line_time_in_us;
 	}
 
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index d61ea3e2bfbf..119ce8b7a555 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -676,6 +676,7 @@ struct psr_config {
 	bool su_granularity_required;
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
+	unsigned int line_time_in_us;
 };
 
 union dmcu_psr_level {
@@ -783,6 +784,7 @@ struct psr_context {
 	bool su_granularity_required;
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
+	unsigned int line_time_in_us;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index bc4943205bce..c2d65756ce5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -340,6 +340,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 		copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
 
 	copy_settings_data->line_capture_indication = 0;
+	copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
-- 
2.25.1

[PATCH v2 10/19] drm/amd/display: fix system hang when PSR exits

[David Zhang]

[why]
When DC driver send PSR exit dmub command to DMUB FW, it might not
wait until PSR exit. Then it may hit the following deadlock situation.
1. DC driver send HW LOCK command to DMUB FW due to frame update
2. DMUB FW Set the HW lock
3. DMUB execute PSR exit sequence and stuck at polling DPG Pending
register due to the HW Lock is set
4. DC driver ask DMUB FW to unlock HW lock, but DMUB FW is polling
DPG pending register

[how]
The reason why DC driver doesn't wait until PSR exit is because some of
the PSR state machine state is not update the dc driver. So when DC
driver read back the PSR state, it take the state for PSR inactive.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  7 +++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 16 ++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 119ce8b7a555..144c387010c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -657,10 +657,17 @@ enum dc_psr_state {
 	PSR_STATE4b,
 	PSR_STATE4c,
 	PSR_STATE4d,
+	PSR_STATE4_FULL_FRAME,
+	PSR_STATE4a_FULL_FRAME,
+	PSR_STATE4b_FULL_FRAME,
+	PSR_STATE4c_FULL_FRAME,
+	PSR_STATE4_FULL_FRAME_POWERUP,
 	PSR_STATE5,
 	PSR_STATE5a,
 	PSR_STATE5b,
 	PSR_STATE5c,
+	PSR_STATE_HWLOCK_MGR,
+	PSR_STATE_POLLVUPDATE,
 	PSR_STATE_INVALID = 0xFF
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index c2d65756ce5d..e784002fe312 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -74,6 +74,22 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
 		state = PSR_STATE5b;
 	else if (raw_state == 0x53)
 		state = PSR_STATE5c;
+	else if (raw_state == 0x4A)
+		state = PSR_STATE4_FULL_FRAME;
+	else if (raw_state == 0x4B)
+		state = PSR_STATE4a_FULL_FRAME;
+	else if (raw_state == 0x4C)
+		state = PSR_STATE4b_FULL_FRAME;
+	else if (raw_state == 0x4D)
+		state = PSR_STATE4c_FULL_FRAME;
+	else if (raw_state == 0x4E)
+		state = PSR_STATE4_FULL_FRAME_POWERUP;
+	else if (raw_state == 0x60)
+		state = PSR_STATE_HWLOCK_MGR;
+	else if (raw_state == 0x61)
+		state = PSR_STATE_POLLVUPDATE;
+	else
+		state = PSR_STATE_INVALID;
 
 	return state;
 }
-- 
2.25.1

[PATCH v2 11/19] drm/amd/display: Set PSR level to enable ALPM by default

[David Zhang]

[Why & How]
While support ALPM, do ALPM state transition while PSR entry/exit.
ALPM is needed for PSR-SU feature, and since the function is ready,
we'd enable it by default.

- Add psr level definition to enable/disable ALPM and set ALPM
  powerdone mode.
- Enable ALPM by default

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++
 drivers/gpu/drm/amd/display/dc/dc_types.h     | 4 +++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1ae48fa65e64..259745074ebb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3333,6 +3333,10 @@ bool dc_link_setup_psr(struct dc_link *link,
 	 */
 	psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
 
+	/* enable ALPM */
+	psr_context->psr_level.bits.DISABLE_ALPM = 0;
+	psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
+
 	/* Controls additional delay after remote frame capture before
 	 * continuing power down, default = 0
 	 */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 144c387010c2..26b62f50ac4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -698,7 +698,9 @@ union dmcu_psr_level {
 		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
 		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
 		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
-		unsigned int RESERVED:22;
+		unsigned int DISABLE_ALPM:1;
+		unsigned int ALPM_DEFAULT_PD_MODE:1;
+		unsigned int RESERVED:20;
 	} bits;
 	unsigned int u32all;
 };
-- 
2.25.1

[PATCH v2 12/19] drm/amd/display: use HW lock mgr for PSR-SU

[David Zhang]

[why]
Feature requires synchronization of dig, pipe, and cursor locking
between driver and DMUB fw for PSR-SU

[how]
return True if PSR-SU in the checker should_use_dmub_lock()

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index b1b2e3c6f379..3f32e9c3fbaf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -65,5 +65,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
 
 bool should_use_dmub_lock(struct dc_link *link)
 {
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
 	return false;
 }
-- 
2.25.1

[PATCH v2 13/19] drm/amd/display: PSRSU+DSC WA for specific TCON

[David Zhang]

[why]
Some specific TCON chip has HW limitation to support PSRSU+DSC.

[how]
Force ffu mode when DSC enabled if we detect it is the specific
model from sink OUI DPCD. And disable ABM update for this case.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 251f2bbc96b9..5e7f70840e1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -108,6 +108,7 @@ struct psr_settings {
 	 */
 	bool psr_frame_capture_indication_req;
 	unsigned int psr_sdp_transmit_line_num_deadline;
+	uint8_t force_ffu_mode;
 	unsigned int psr_power_opt;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index e784002fe312..9ca0cbb0af9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -349,6 +349,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.u32All = 0;
 	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
+	copy_settings_data->debug.bitfields.force_full_frame_update	= 0;
 
 	if (psr_context->su_granularity_required == 0)
 		copy_settings_data->su_y_granularity = 0;
@@ -363,6 +364,19 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->panel_inst = panel_inst;
 	copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
 
+	/**
+	 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
+	 * Note that PSRSU+DSC is still under development.
+	 */
+	if (copy_settings_data->dsc_enable_status &&
+		link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
+		!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
+			sizeof(link->dpcd_caps.sink_dev_id_str)))
+		link->psr_settings.force_ffu_mode = 1;
+	else
+		link->psr_settings.force_ffu_mode = 0;
+	copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
+
 	if (link->fec_state == dc_link_fec_enabled &&
 		(!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
 			sizeof(link->dpcd_caps.sink_dev_id_str)) ||
-- 
2.25.1

[PATCH v2 14/19] drm/amd/display: add shared helpers to update psr config fields to power module

[David Zhang]

[why]
Currently the amdgpu DM psr configuration parameters are hardcoded
before feeding into the DC helper to setup PSR. We would define a
helper which is to calculate parts of the psr config fields to
avoid hard-coding.

[how]
To make helper shareable, declare and define the helper in the
module_helper, to set/update below fields:
- psr remote buffer setup time
- sdp tx line number deadline
- line time in us
- su_y_granularity
- su_granularity_required
- psr_frame_capture_indication_req
- psr_exit_link_training_required

add another helper to check given the stream context, if there is
only one stream and the output is eDP panel connected.

changes in v2:
------------------
- add detailed comment for how psr setup time is calculated as per
  eDP 1.5 spec

Cc: Chandan Vurdigerenataraj <chandan.vurdigerenataraj@amd.com>

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 .../amd/display/modules/power/power_helpers.c | 84 +++++++++++++++++++
 .../amd/display/modules/power/power_helpers.h |  6 ++
 2 files changed, 90 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 97928d4c3b9a..bc239d38c3c7 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -822,3 +822,87 @@ bool is_psr_su_specific_panel(struct dc_link *link)
 
 	return false;
 }
+
+/**
+ * mod_power_calc_psr_configs() - calculate/update generic psr configuration fields.
+ * @psr_config: [output], psr configuration structure to be updated
+ * @link: [input] dc link pointer
+ * @stream: [input] dc stream state pointer
+ *
+ * calculate and update the psr configuration fields that are not DM specific, i.e. such
+ * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW,
+ * this helper is assumed to be called before the call of the DC helper dc_link_setup_psr().
+ *
+ * PSR config fields to be updated within the helper:
+ * - psr_rfb_setup_time
+ * - psr_sdp_transmit_line_num_deadline
+ * - line_time_in_us
+ * - su_y_granularity
+ * - su_granularity_required
+ * - psr_frame_capture_indication_req
+ * - psr_exit_link_training_required
+ *
+ * PSR config fields that are DM specific and NOT updated within the helper:
+ * - allow_smu_optimizations
+ * - allow_multi_disp_optimizations
+ */
+void mod_power_calc_psr_configs(struct psr_config *psr_config,
+		struct dc_link *link,
+		const struct dc_stream_state *stream)
+{
+	unsigned int num_vblank_lines = 0;
+	unsigned int vblank_time_in_us = 0;
+	unsigned int sdp_tx_deadline_in_us = 0;
+	unsigned int line_time_in_us = 0;
+	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
+	const int psr_setup_time_step_in_us = 55;	/* refer to eDP spec DPCD 0x071h */
+
+	/* timing parameters */
+	num_vblank_lines = stream->timing.v_total -
+			 stream->timing.v_addressable -
+			 stream->timing.v_border_top -
+			 stream->timing.v_border_bottom;
+
+	vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);
+
+	line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;
+
+	/**
+	 * psr configuration fields
+	 *
+	 * as per eDP 1.5 pg. 377 of 459, DPCD 0x071h bits [3:1], psr setup time bits interpreted as below
+	 * 000b <--> 330 us (default)
+	 * 001b <--> 275 us
+	 * 010b <--> 220 us
+	 * 011b <--> 165 us
+	 * 100b <--> 110 us
+	 * 101b <--> 055 us
+	 * 110b <--> 000 us
+	 */
+	psr_config->psr_rfb_setup_time =
+		(6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * psr_setup_time_step_in_us;
+
+	if (psr_config->psr_rfb_setup_time > vblank_time_in_us) {
+		link->psr_settings.psr_frame_capture_indication_req = true;
+		link->psr_settings.psr_sdp_transmit_line_num_deadline = num_vblank_lines;
+	} else {
+		sdp_tx_deadline_in_us = vblank_time_in_us - psr_config->psr_rfb_setup_time;
+
+		/* Set the last possible line SDP may be transmitted without violating the RFB setup time */
+		link->psr_settings.psr_frame_capture_indication_req = false;
+		link->psr_settings.psr_sdp_transmit_line_num_deadline = sdp_tx_deadline_in_us / line_time_in_us;
+	}
+
+	psr_config->psr_sdp_transmit_line_num_deadline = link->psr_settings.psr_sdp_transmit_line_num_deadline;
+	psr_config->line_time_in_us = line_time_in_us;
+	psr_config->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap;
+	psr_config->su_granularity_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED;
+	psr_config->psr_frame_capture_indication_req = link->psr_settings.psr_frame_capture_indication_req;
+	psr_config->psr_exit_link_training_required =
+		!link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED;
+}
+
+bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)
+{
+	return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
+}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 1a634d8c78c5..316452e9dbc9 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -27,6 +27,7 @@
 
 #include "dc/inc/hw/dmcu.h"
 #include "dc/inc/hw/abm.h"
+#include "dc/inc/core_types.h"
 
 struct resource_pool;
 
@@ -53,4 +54,9 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 		unsigned int inst);
 
 bool is_psr_su_specific_panel(struct dc_link *link);
+void mod_power_calc_psr_configs(struct psr_config *psr_config,
+		struct dc_link *link,
+		const struct dc_stream_state *stream);
+bool mod_power_only_edp(const struct dc_state *context,
+		const struct dc_stream_state *stream);
 #endif /* MODULES_POWER_POWER_HELPERS_H_ */
-- 
2.25.1

[PATCH v2 15/19] drm/amd/display: calculate psr config settings in runtime in DM

[David Zhang]

[why]
Currently the psr configuration parameters are hardcoded before
feeding into the DC helper before passing to DMUB FW. We'd rework
to call a shared helper to calculate/update generic psr config
fields which are relying on the stream timing and eDP sink PSR
caps to avoid hard-coding.

[how]
- drop part of hard-coded psr config fields by replacing w/ the
  call of helper from DM before feeding into DC link setup psr
  helper
- For those DM specific psr config fields, e.g. allow smu opt, is
  not to be set/updated from the shared helper but to rely on the
  DC feature mask
- for the psr version field in psr_config structure, since only
  the field psr_version of DC link psr_settings matters for that
  fed to DMUB FW, thus no need to set/update the psr_version field
  of psr_config structure.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 141fd2721501..52508bdda8e9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -97,19 +97,24 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
 	struct dc_link *link = NULL;
 	struct psr_config psr_config = {0};
 	struct psr_context psr_context = {0};
+	struct dc *dc = NULL;
 	bool ret = false;
 
 	if (stream == NULL)
 		return false;
 
 	link = stream->link;
+	dc = link->ctx->dc;
 
 	if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
-		psr_config.psr_version = link->psr_settings.psr_version;
-		psr_config.psr_frame_capture_indication_req = 0;
-		psr_config.psr_rfb_setup_time = 0x37;
-		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
-		psr_config.allow_smu_optimizations = 0x0;
+		mod_power_calc_psr_configs(&psr_config, link, stream);
+
+		/* linux DM specific updating for psr config fields */
+		psr_config.allow_smu_optimizations =
+			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
+			mod_power_only_edp(dc->current_state, stream);
+		psr_config.allow_multi_disp_optimizations =
+			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
 
 		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
 
-- 
2.25.1

[PATCH v2 16/19] drm/amd/display: update cursor position to DMUB FW

[David Zhang]

[why]
To involve the cursor position into dirty rectangle calculation.

[how]
- separate plane and cursor update by different DMUB command
- send the cursor information while cursor updating, when updating
  cursor position/attribute, store cursor pos/attr to hubp, and
  notify dmub FW to exit psr before program cursor registers

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 ++++++++++++++++++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
 4 files changed, 136 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 3a7f76e2c598..564e061ccb58 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1188,6 +1188,8 @@ void hubp1_cursor_set_position(
 	uint32_t dst_x_offset;
 	uint32_t cur_en = pos->enable ? 1 : 0;
 
+	hubp->curs_pos = *pos;
+
 	/*
 	 * Guard aganst cursor_set_position() from being called with invalid
 	 * attributes
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e02ac75afbf7..b30ba9c3166b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -51,6 +51,8 @@
 #include "link_hwss.h"
 #include "dpcd_defs.h"
 #include "dsc.h"
+#include "dce/dmub_psr.h"
+#include "dc_dmub_srv.h"
 #include "dce/dmub_hw_lock_mgr.h"
 #include "dc_trace.h"
 #include "dce/dmub_outbox.h"
@@ -3327,6 +3329,115 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 	return false;
 }
 
+static void dcn10_dmub_update_cursor_data(
+		struct pipe_ctx *pipe_ctx,
+		struct hubp *hubp,
+		const struct dc_cursor_mi_param *param,
+		const struct dc_cursor_position *cur_pos,
+		const struct dc_cursor_attributes *cur_attr)
+{
+	union dmub_rb_cmd cmd;
+	struct dmub_cmd_update_cursor_info_data *update_cursor_info;
+	const struct dc_cursor_position *pos;
+	const struct dc_cursor_attributes *attr;
+	int src_x_offset = 0;
+	int src_y_offset = 0;
+	int x_hotspot = 0;
+	int cursor_height = 0;
+	int cursor_width = 0;
+	uint32_t cur_en = 0;
+	unsigned int panel_inst = 0;
+
+	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
+
+	if (!debug->enable_sw_cntl_psr && pipe_ctx->stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+		return;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ||
+		pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+		return;
+
+	/**
+	 * if cur_pos == NULL means the caller is from cursor_set_attribute
+	 * then driver use previous cursor position data
+	 * if cur_attr == NULL means the caller is from cursor_set_position
+	 * then driver use previous cursor attribute
+	 * if cur_pos or cur_attr is not NULL then update it
+	 */
+	if (cur_pos != NULL)
+		pos = cur_pos;
+	else
+		pos = &hubp->curs_pos;
+
+	if (cur_attr != NULL)
+		attr = cur_attr;
+	else
+		attr = &hubp->curs_attr;
+
+	if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, pipe_ctx->stream->link, &panel_inst))
+		return;
+
+	src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
+	src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
+	x_hotspot = pos->x_hotspot;
+	cursor_height = (int)attr->height;
+	cursor_width = (int)attr->width;
+	cur_en = pos->enable ? 1:0;
+
+	// Rotated cursor width/height and hotspots tweaks for offset calculation
+	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
+		swap(cursor_height, cursor_width);
+		if (param->rotation == ROTATION_ANGLE_90) {
+			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
+			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
+		}
+	} else if (param->rotation == ROTATION_ANGLE_180) {
+		src_x_offset = pos->x - param->viewport.x;
+		src_y_offset = pos->y - param->viewport.y;
+	}
+
+	if (param->mirror) {
+		x_hotspot = param->viewport.width - x_hotspot;
+		src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
+	}
+
+	if (src_x_offset >= (int)param->viewport.width)
+		cur_en = 0;  /* not visible beyond right edge*/
+
+	if (src_x_offset + cursor_width <= 0)
+		cur_en = 0;  /* not visible beyond left edge*/
+
+	if (src_y_offset >= (int)param->viewport.height)
+		cur_en = 0;  /* not visible beyond bottom edge*/
+
+	if (src_y_offset + cursor_height <= 0)
+		cur_en = 0;  /* not visible beyond top edge*/
+
+	// Cursor bitmaps have different hotspot values
+	// There's a possibility that the above logic returns a negative value, so we clamp them to 0
+	if (src_x_offset < 0)
+		src_x_offset = 0;
+	if (src_y_offset < 0)
+		src_y_offset = 0;
+
+	memset(&cmd, 0x0, sizeof(cmd));
+	cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO;
+	cmd.update_cursor_info.header.payload_bytes =
+			sizeof(cmd.update_cursor_info.update_cursor_info_data);
+	update_cursor_info = &cmd.update_cursor_info.update_cursor_info_data;
+	update_cursor_info->cursor_rect.x = src_x_offset + param->viewport.x;
+	update_cursor_info->cursor_rect.y = src_y_offset + param->viewport.y;
+	update_cursor_info->cursor_rect.width = attr->width;
+	update_cursor_info->cursor_rect.height = attr->height;
+	update_cursor_info->enable = cur_en;
+	update_cursor_info->pipe_idx = pipe_ctx->pipe_idx;
+	update_cursor_info->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+	update_cursor_info->panel_inst = panel_inst;
+	dc_dmub_srv_cmd_queue(pipe_ctx->stream->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(pipe_ctx->stream->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(pipe_ctx->stream->ctx->dmub_srv);
+}
+
 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 {
 	struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
@@ -3525,6 +3636,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 			pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
 	}
 
+	dcn10_dmub_update_cursor_data(pipe_ctx, hubp, &param, &pos_cpy, NULL);
 	hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
 	dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
 }
@@ -3532,6 +3644,25 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
 {
 	struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+	struct dc_cursor_mi_param param = { 0 };
+
+	/**
+	 * If enter PSR without cursor attribute update
+	 * the cursor attribute of dmub_restore_plane
+	 * are initial value. call dmub to exit PSR and
+	 * restore plane then update cursor attribute to
+	 * avoid override with initial value
+	 */
+	if (pipe_ctx->plane_state != NULL) {
+		param.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
+		param.ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz;
+		param.viewport = pipe_ctx->plane_res.scl_data.viewport;
+		param.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz;
+		param.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert;
+		param.rotation = pipe_ctx->plane_state->rotation;
+		param.mirror = pipe_ctx->plane_state->horizontal_mirror;
+		dcn10_dmub_update_cursor_data(pipe_ctx, pipe_ctx->plane_res.hubp, &param, NULL, attributes);
+	}
 
 	pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
 			pipe_ctx->plane_res.hubp, attributes);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index a665af19f201..9570c2118ccc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -967,6 +967,8 @@ void hubp2_cursor_set_position(
 	uint32_t dst_x_offset;
 	uint32_t cur_en = pos->enable ? 1 : 0;
 
+	hubp->curs_pos = *pos;
+
 	/*
 	 * Guard aganst cursor_set_position() from being called with invalid
 	 * attributes
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index ad69d78c4ac3..fc53ee013557 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -63,6 +63,7 @@ struct hubp {
 	int opp_id;
 	int mpcc_id;
 	struct dc_cursor_attributes curs_attr;
+	struct dc_cursor_position curs_pos;
 	bool power_gated;
 };
 
-- 
2.25.1

[PATCH v2 17/19] drm/amd/display: Implement MPO PSR SU

[David Zhang]

From: Leo Li <sunpeng.li@amd.com>

[WHY]

For additional power savings, PSR SU (also referred to as PSR2) can be
enabled on eDP panels with PSR SU support.

PSR2 saves more power compared to PSR1 by allowing more opportunities
for the display hardware to be shut down. In comparison to PSR1, Shut
down can now occur in-between frames, as well as in display regions
where there is no visible update. In otherwords, it allows for some
display hw components to be enabled only for a **selectively updated**
region of the visible display. Hence PSR SU.

[HOW]

To define the SU region, support from the OS is required. OS needs to
inform driver of damaged regions that need to be flushed to the eDP
panel. Today, such support is lacking in most compositors.

Therefore, an in-between solution is to implement PSR SU for MPO and
cursor scenarios. The plane bounds can be used to define the damaged
region to be flushed to panel. This is achieved by:

* Leveraging dm_crtc_state->mpo_requested flag to identify when MPO is
  enabled.
* If MPO is enabled, only add updated plane bounds to dirty region.
  Determine plane update by either:
    * Existence of drm damaged clips attached to the plane (added by a
      damage-aware compositor)
    * Change in fb id (flip)
    * Change in plane bounds (position and dimensions)
* If cursor is enabled, the old_pos and new_pos of cursor plus cursor
  size is used as damaged regions(*).

(*) Cursor updates follow a different code path through DC. PSR SU for
cursor is already implemented in DC, and the only thing required to
enable is to set DC_PSR_VERSION_SU_1 on the eDP link. See
dcn10_dmub_update_cursor_data().

Signed-off-by: Leo Li <sunpeng.li@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++++++++++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |   6 +-
 2 files changed, 144 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2ea20dd7fccf..29dd59d06fa4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1255,10 +1255,20 @@ static void vblank_control_worker(struct work_struct *work)
 
 	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
 
-	/* Control PSR based on vblank requirements from OS */
+	/*
+	 * Control PSR based on vblank requirements from OS
+	 *
+	 * If panel supports PSR SU, there's no need to disable PSR when OS is
+	 * submitting fast atomic commits (we infer this by whether the OS
+	 * requests vblank events). Fast atomic commits will simply trigger a
+	 * full-frame-update (FFU); a specific case of selective-update (SU)
+	 * where the SU region is the full hactive*vactive region. See
+	 * fill_dc_dirty_rects().
+	 */
 	if (vblank_work->stream && vblank_work->stream->link) {
 		if (vblank_work->enable) {
-			if (vblank_work->stream->link->psr_settings.psr_allow_active)
+			if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 &&
+			    vblank_work->stream->link->psr_settings.psr_allow_active)
 				amdgpu_dm_psr_disable(vblank_work->stream);
 		} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
 			   !vblank_work->stream->link->psr_settings.psr_allow_active &&
@@ -5631,6 +5641,117 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
 	return 0;
 }
 
+/**
+ * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
+ *
+ * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
+ *         remote fb
+ * @old_plane_state: Old state of @plane
+ * @new_plane_state: New state of @plane
+ * @crtc_state: New state of CRTC connected to the @plane
+ * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
+ *
+ * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
+ * (referred to as "damage clips" in DRM nomenclature) that require updating on
+ * the eDP remote buffer. The responsibility of specifying the dirty regions is
+ * amdgpu_dm's.
+ *
+ * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
+ * plane with regions that require flushing to the eDP remote buffer. In
+ * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
+ * implicitly provide damage clips without any client support via the plane
+ * bounds.
+ *
+ * Today, amdgpu_dm only supports the MPO and cursor usecase.
+ *
+ * TODO: Also enable for FB_DAMAGE_CLIPS
+ */
+static void fill_dc_dirty_rects(struct drm_plane *plane,
+				struct drm_plane_state *old_plane_state,
+				struct drm_plane_state *new_plane_state,
+				struct drm_crtc_state *crtc_state,
+				struct dc_flip_addrs *flip_addrs)
+{
+	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
+	struct rect *dirty_rects = flip_addrs->dirty_rects;
+	uint32_t num_clips;
+	bool bb_changed;
+	bool fb_changed;
+	uint32_t i = 0;
+
+	flip_addrs->dirty_rect_count = 0;
+
+	/*
+	 * Cursor plane has it's own dirty rect update interface. See
+	 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
+	 */
+	if (plane->type == DRM_PLANE_TYPE_CURSOR)
+		return;
+
+	/*
+	 * Today, we only consider MPO use-case for PSR SU. If MPO not
+	 * requested, and there is a plane update, do FFU.
+	 */
+	if (!dm_crtc_state->mpo_requested) {
+		dirty_rects[0].x = 0;
+		dirty_rects[0].y = 0;
+		dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
+		dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
+		flip_addrs->dirty_rect_count = 1;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
+				 new_plane_state->plane->base.id,
+				 dm_crtc_state->base.mode.crtc_hdisplay,
+				 dm_crtc_state->base.mode.crtc_vdisplay);
+		return;
+	}
+
+	/*
+	 * MPO is requested. Add entire plane bounding box to dirty rects if
+	 * flipped to or damaged.
+	 *
+	 * If plane is moved or resized, also add old bounding box to dirty
+	 * rects.
+	 */
+	num_clips = drm_plane_get_damage_clips_count(new_plane_state);
+	fb_changed = old_plane_state->fb->base.id !=
+		     new_plane_state->fb->base.id;
+	bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
+		      old_plane_state->crtc_y != new_plane_state->crtc_y ||
+		      old_plane_state->crtc_w != new_plane_state->crtc_w ||
+		      old_plane_state->crtc_h != new_plane_state->crtc_h);
+
+	DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
+			 new_plane_state->plane->base.id,
+			 bb_changed, fb_changed, num_clips);
+
+	if (num_clips || fb_changed || bb_changed) {
+		dirty_rects[i].x = new_plane_state->crtc_x;
+		dirty_rects[i].y = new_plane_state->crtc_y;
+		dirty_rects[i].width = new_plane_state->crtc_w;
+		dirty_rects[i].height = new_plane_state->crtc_h;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
+				 new_plane_state->plane->base.id,
+				 dirty_rects[i].x, dirty_rects[i].y,
+				 dirty_rects[i].width, dirty_rects[i].height);
+		i += 1;
+	}
+
+	/* Add old plane bounding-box if plane is moved or resized */
+	if (bb_changed) {
+		dirty_rects[i].x = old_plane_state->crtc_x;
+		dirty_rects[i].y = old_plane_state->crtc_y;
+		dirty_rects[i].width = old_plane_state->crtc_w;
+		dirty_rects[i].height = old_plane_state->crtc_h;
+		DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
+				old_plane_state->plane->base.id,
+				dirty_rects[i].x, dirty_rects[i].y,
+				dirty_rects[i].width, dirty_rects[i].height);
+		i += 1;
+	}
+
+	flip_addrs->dirty_rect_count = i;
+}
+
 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
 					   const struct dm_connector_state *dm_state,
 					   struct dc_stream_state *stream)
@@ -6579,6 +6700,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
 	state->cm_has_degamma = cur->cm_has_degamma;
 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
 	state->force_dpms_off = cur->force_dpms_off;
+	state->mpo_requested = cur->mpo_requested;
 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
 
 	return &state->base;
@@ -9219,6 +9341,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		bundle->surface_updates[planes_count].plane_info =
 			&bundle->plane_infos[planes_count];
 
+		fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
+				    new_crtc_state,
+				    &bundle->flip_addrs[planes_count]);
+
 		/*
 		 * Only allow immediate flips for fast updates that don't
 		 * change FB pitch, DCC state, rotation or mirroing.
@@ -9414,6 +9540,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 
 			/* Allow PSR when skip count is 0. */
 			acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
+
+			/*
+			 * If sink supports PSR SU, there is no need to rely on
+			 * a vblank event disable request to enable PSR. PSR SU
+			 * can be enabled immediately once OS demonstrates an
+			 * adequate number of fast atomic commits to notify KMD
+			 * of update events. See `vblank_control_worker()`.
+			 */
+			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
+			    acrtc_attach->dm_irq_params.allow_psr_entry &&
+			    !acrtc_state->stream->link->psr_settings.psr_allow_active)
+				amdgpu_dm_psr_enable(acrtc_state->stream);
 		} else {
 			acrtc_attach->dm_irq_params.allow_psr_entry = false;
 		}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 52508bdda8e9..c8da18e45b0e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -79,10 +79,12 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
 		link->psr_settings.psr_feature_enabled = true;
 	}
 
-	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n",
+	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
 		link->psr_settings.psr_feature_enabled,
 		link->psr_settings.psr_version,
-		link->dpcd_caps.psr_info.psr_version);
+		link->dpcd_caps.psr_info.psr_version,
+		link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
+		link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
 
 }
 
-- 
2.25.1

[PATCH v2 18/19] drm/amd/display: expose AMD source specific DPCD for FreeSync PSR support

[David Zhang]

[why & how]
The source specific DPCD exposure which is to set the sink device PSR
active vtotal control mode.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/include/ddc_service_types.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 73b9e0a87e54..054253286886 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -40,6 +40,7 @@
 
 #define DP_DEVICE_ID_38EC11 0x38EC11
 #define DP_FORCE_PSRSU_CAPABILITY 0x40F
+#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE 0x375
 
 enum ddc_result {
 	DDC_RESULT_UNKNOWN = 0,
-- 
2.25.1

[PATCH v2 19/19] drm/amd/display: PSR-SU rate control support in DC

[David Zhang]

[why & how]
We need to add the necessary DC codes to support PSR-SU rate
control (RC).

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +++++++++++
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  3 +++
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 +++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++++++
 6 files changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 259745074ebb..08dedc16a9c5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1765,6 +1765,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 	 */
 	program_hpd_filter(link);
 
+	link->psr_settings.psr_vtotal_control_support = false;
 	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
 
 	DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
@@ -3377,6 +3378,19 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
 		*residency = 0;
 }
 
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	struct dc *dc = link->ctx->dc;
+	struct dmub_psr *psr = dc->res_pool->psr;
+
+	if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
+		return false;
+
+	psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
+
+	return true;
+}
+
 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
 {
 	return &link->link_status;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 5e7f70840e1a..4e15e68375da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -100,6 +100,7 @@ struct psr_settings {
 	bool psr_feature_enabled;		// PSR is supported by sink
 	bool psr_allow_active;			// PSR is currently active
 	enum dc_psr_version psr_version;		// Internal PSR version, determined based on DPCD
+	bool psr_vtotal_control_support;	// Vtotal control is supported by sink
 
 	/* These parameters are calculated in Driver,
 	 * based on display timing and Sink capabilities.
@@ -326,6 +327,8 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
 void dc_link_blank_all_dp_displays(struct dc *dc);
 
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init);
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 
 /* Request DC to detect if there is a Panel connected.
  * boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 26b62f50ac4e..fa735d5f730f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -684,6 +684,7 @@ struct psr_config {
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 union dmcu_psr_level {
@@ -794,6 +795,7 @@ struct psr_context {
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 9ca0cbb0af9b..0df06740ec39 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -250,6 +250,27 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_
 	dc_dmub_srv_wait_idle(dc->dmub_srv);
 }
 
+/**
+ * Set PSR vtotal requirement for FreeSync PSR.
+ */
+static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	union dmub_rb_cmd cmd;
+	struct dc_context *dc = dmub->ctx;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
+	cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
+	cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
+
+	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
 /*
  * Set PSR power optimization flags.
  */
@@ -358,6 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 
 	copy_settings_data->line_capture_indication = 0;
 	copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
+	copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
@@ -435,6 +457,7 @@ static const struct dmub_psr_funcs psr_funcs = {
 	.psr_set_level			= dmub_psr_set_level,
 	.psr_force_static		= dmub_psr_force_static,
 	.psr_get_residency		= dmub_psr_get_residency,
+	.psr_set_sink_vtotal_in_psr_active	= dmub_psr_set_sink_vtotal_in_psr_active,
 	.psr_set_power_opt		= dmub_psr_set_power_opt,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index 01acc01cc191..74005b9d352a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -46,6 +46,8 @@ struct dmub_psr_funcs {
 	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
 	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
 	uint8_t panel_inst);
+	void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,
+	uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 	void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 66132f3cac42..c89643eaa0f4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -101,6 +101,14 @@ union dpcd_alpm_configuration {
 	unsigned char raw;
 };
 
+union dpcd_sink_active_vtotal_control_mode {
+	struct {
+		unsigned char ENABLE                    : 1;
+		unsigned char RESERVED                  : 7;
+	} bits;
+	unsigned char raw;
+};
+
 union psr_error_status {
 	struct {
 		unsigned char LINK_CRC_ERROR        :1;
-- 
2.25.1

Re: [PATCH v2 19/19] drm/amd/display: PSR-SU rate control support in DC

[Harry Wentland]

On 5/10/22 16:45, David Zhang wrote:
> [why & how]
> We need to add the necessary DC codes to support PSR-SU rate
> control (RC).

We'll probably want to expand a bit on what rate control
is and also note that this is just adding core functionality
for RC but not enabling it.

Harry

> 
> Signed-off-by: David Zhang <dingchen.zhang@amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +++++++++++
>  drivers/gpu/drm/amd/display/dc/dc_link.h      |  3 +++
>  drivers/gpu/drm/amd/display/dc/dc_types.h     |  2 ++
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 +++++++++++++++++++
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
>  .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++++++
>  6 files changed, 52 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 259745074ebb..08dedc16a9c5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1765,6 +1765,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
>  	 */
>  	program_hpd_filter(link);
>  
> +	link->psr_settings.psr_vtotal_control_support = false;
>  	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
>  
>  	DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
> @@ -3377,6 +3378,19 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
>  		*residency = 0;
>  }
>  
> +bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
> +{
> +	struct dc *dc = link->ctx->dc;
> +	struct dmub_psr *psr = dc->res_pool->psr;
> +
> +	if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
> +		return false;
> +
> +	psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
> +
> +	return true;
> +}
> +
>  const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
>  {
>  	return &link->link_status;
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
> index 5e7f70840e1a..4e15e68375da 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_link.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
> @@ -100,6 +100,7 @@ struct psr_settings {
>  	bool psr_feature_enabled;		// PSR is supported by sink
>  	bool psr_allow_active;			// PSR is currently active
>  	enum dc_psr_version psr_version;		// Internal PSR version, determined based on DPCD
> +	bool psr_vtotal_control_support;	// Vtotal control is supported by sink
>  
>  	/* These parameters are calculated in Driver,
>  	 * based on display timing and Sink capabilities.
> @@ -326,6 +327,8 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
>  void dc_link_blank_all_dp_displays(struct dc *dc);
>  
>  void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init);
> +bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link,
> +		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
>  
>  /* Request DC to detect if there is a Panel connected.
>   * boot - If this call is during initial boot.
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
> index 26b62f50ac4e..fa735d5f730f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
> @@ -684,6 +684,7 @@ struct psr_config {
>  	/* psr2 selective update y granularity capability */
>  	uint8_t su_y_granularity;
>  	unsigned int line_time_in_us;
> +	uint8_t rate_control_caps;
>  };
>  
>  union dmcu_psr_level {
> @@ -794,6 +795,7 @@ struct psr_context {
>  	/* psr2 selective update y granularity capability */
>  	uint8_t su_y_granularity;
>  	unsigned int line_time_in_us;
> +	uint8_t rate_control_caps;
>  };
>  
>  struct colorspace_transform {
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
> index 9ca0cbb0af9b..0df06740ec39 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
> @@ -250,6 +250,27 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_
>  	dc_dmub_srv_wait_idle(dc->dmub_srv);
>  }
>  
> +/**
> + * Set PSR vtotal requirement for FreeSync PSR.
> + */
> +static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
> +		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
> +{
> +	union dmub_rb_cmd cmd;
> +	struct dc_context *dc = dmub->ctx;
> +
> +	memset(&cmd, 0, sizeof(cmd));
> +	cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
> +	cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
> +	cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
> +	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
> +	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
> +
> +	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
> +	dc_dmub_srv_cmd_execute(dc->dmub_srv);
> +	dc_dmub_srv_wait_idle(dc->dmub_srv);
> +}
> +
>  /*
>   * Set PSR power optimization flags.
>   */
> @@ -358,6 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
>  
>  	copy_settings_data->line_capture_indication = 0;
>  	copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
> +	copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
>  	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
>  	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
>  	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
> @@ -435,6 +457,7 @@ static const struct dmub_psr_funcs psr_funcs = {
>  	.psr_set_level			= dmub_psr_set_level,
>  	.psr_force_static		= dmub_psr_force_static,
>  	.psr_get_residency		= dmub_psr_get_residency,
> +	.psr_set_sink_vtotal_in_psr_active	= dmub_psr_set_sink_vtotal_in_psr_active,
>  	.psr_set_power_opt		= dmub_psr_set_power_opt,
>  };
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
> index 01acc01cc191..74005b9d352a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
> @@ -46,6 +46,8 @@ struct dmub_psr_funcs {
>  	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
>  	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
>  	uint8_t panel_inst);
> +	void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,
> +	uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
>  	void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);
>  };
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> index 66132f3cac42..c89643eaa0f4 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> @@ -101,6 +101,14 @@ union dpcd_alpm_configuration {
>  	unsigned char raw;
>  };
>  
> +union dpcd_sink_active_vtotal_control_mode {
> +	struct {
> +		unsigned char ENABLE                    : 1;
> +		unsigned char RESERVED                  : 7;
> +	} bits;
> +	unsigned char raw;
> +};
> +
>  union psr_error_status {
>  	struct {
>  		unsigned char LINK_CRC_ERROR        :1;

Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[Alex Deucher]

On Tue, May 10, 2022 at 4:45 PM David Zhang <dingchen.zhang@amd.com> wrote:
>
> changes in v2:
> -----------------------
> - set vsc_packet_rev2 for PSR1 which is safer
> - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
> - add DC/DM change related to amdgpu PSR-SU-RC
>
>
> David Zhang (18):
>   drm/amd/display: align dmub cmd header to latest dmub FW to support
>     PSR-SU
>   drm/amd/display: feed PSR-SU as psr version to dmub FW
>   drm/amd/display: combine dirty rectangles in DMUB FW
>   drm/amd/display: update GSP1 generic info packet for PSRSU
>   drm/amd/display: revise Start/End SDP data
>   drm/amd/display: program PSR2 DPCD Configuration
>   drm/amd/display: Passing Y-granularity to dmub fw
>   drm/amd/display: Set default value of line_capture_indication
>   drm/amd/display: add vline time in micro sec to PSR context
>   drm/amd/display: fix system hang when PSR exits
>   drm/amd/display: Set PSR level to enable ALPM by default
>   drm/amd/display: use HW lock mgr for PSR-SU
>   drm/amd/display: PSRSU+DSC WA for specific TCON
>   drm/amd/display: add shared helpers to update psr config fields to
>     power module
>   drm/amd/display: calculate psr config settings in runtime in DM
>   drm/amd/display: update cursor position to DMUB FW
>   drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
>     support
>   drm/amd/display: PSR-SU rate control support in DC
>
> Leo Li (1):
>   drm/amd/display: Implement MPO PSR SU

A couple of suggestions from Daniel on IRC:
1.  Might be good to extract the "calculate total crtc damage" code
from i915 in intel_psr2_sel_fetch_update, stuff that into damage
helpers and reuse for i915 and amdgpu
2.  The commit message on "drm/amd/display: Implement MPO PSR SU" is a
bit funny, since if you use the helpers right you always get damage
information, just when it's from userspace that doesn't set explicit
damage it's just always the entire plane.

Alex

>
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
>  drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
>  drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
>  drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
>  drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
>  .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
>  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
>  .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
>  drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
>  .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
>  .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
>  .../amd/display/include/ddc_service_types.h   |   1 +
>  .../display/modules/info_packet/info_packet.c |  29 +-
>  .../amd/display/modules/power/power_helpers.c |  84 ++++++
>  .../amd/display/modules/power/power_helpers.h |   6 +
>  21 files changed, 887 insertions(+), 19 deletions(-)
>
> --
> 2.25.1
>

Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[Daniel Vetter]

On Wed, 11 May 2022 at 17:35, Alex Deucher <alexdeucher@gmail.com> wrote:
>
> On Tue, May 10, 2022 at 4:45 PM David Zhang <dingchen.zhang@amd.com> wrote:
> >
> > changes in v2:
> > -----------------------
> > - set vsc_packet_rev2 for PSR1 which is safer
> > - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
> > - add DC/DM change related to amdgpu PSR-SU-RC
> >
> >
> > David Zhang (18):
> >   drm/amd/display: align dmub cmd header to latest dmub FW to support
> >     PSR-SU
> >   drm/amd/display: feed PSR-SU as psr version to dmub FW
> >   drm/amd/display: combine dirty rectangles in DMUB FW
> >   drm/amd/display: update GSP1 generic info packet for PSRSU
> >   drm/amd/display: revise Start/End SDP data
> >   drm/amd/display: program PSR2 DPCD Configuration
> >   drm/amd/display: Passing Y-granularity to dmub fw
> >   drm/amd/display: Set default value of line_capture_indication
> >   drm/amd/display: add vline time in micro sec to PSR context
> >   drm/amd/display: fix system hang when PSR exits
> >   drm/amd/display: Set PSR level to enable ALPM by default
> >   drm/amd/display: use HW lock mgr for PSR-SU
> >   drm/amd/display: PSRSU+DSC WA for specific TCON
> >   drm/amd/display: add shared helpers to update psr config fields to
> >     power module
> >   drm/amd/display: calculate psr config settings in runtime in DM
> >   drm/amd/display: update cursor position to DMUB FW
> >   drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
> >     support
> >   drm/amd/display: PSR-SU rate control support in DC
> >
> > Leo Li (1):
> >   drm/amd/display: Implement MPO PSR SU
>
> A couple of suggestions from Daniel on IRC:
> 1.  Might be good to extract the "calculate total crtc damage" code
> from i915 in intel_psr2_sel_fetch_update, stuff that into damage
> helpers and reuse for i915 and amdgpu

To expand a bit on this. There is currently a helper for total damage,
but it's at the fb/plane level for drivers which need to upload
buffers (usb/spi or virtual) drm_atomic_helper_damage_merged(). That
one probably needs to be renamed to signify it's about the plane, and
then we need a new drm_atomic_helper_crtc_damage_merged() which
(extract from i915 code ideally) which computes total crtc damage for
stuff like psr2/su or the command mode dsi panels (unfortunately none
of the drivers for android for these panels have been upstreamed yet).

I also think that the split between dc and kms is a bit funny, I'd put
only the resulting damage rect into dc_pipe and do the computation of
that in the drm/kms linux code outside of dc functions (or in the glue
code for dc), since I'm assuming on windows it's completely different
approach in how you compute damage. Especially once we have the crtc
damage helper on linux.

> 2.  The commit message on "drm/amd/display: Implement MPO PSR SU" is a
> bit funny, since if you use the helpers right you always get damage
> information, just when it's from userspace that doesn't set explicit
> damage it's just always the entire plane.

Yeah so that one was just another reason to use the helpers more in
amdgpu for this.
-Daniel

>
> Alex
>
> >
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
> >  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
> >  drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
> >  drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
> >  drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
> >  drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
> >  drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
> >  .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
> >  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
> >  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
> >  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
> >  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
> >  .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
> >  .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
> >  drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
> >  .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
> >  .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
> >  .../amd/display/include/ddc_service_types.h   |   1 +
> >  .../display/modules/info_packet/info_packet.c |  29 +-
> >  .../amd/display/modules/power/power_helpers.c |  84 ++++++
> >  .../amd/display/modules/power/power_helpers.h |   6 +
> >  21 files changed, 887 insertions(+), 19 deletions(-)
> >
> > --
> > 2.25.1
> >



-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[Zhang, Dingchen (David)]

[AMD Official Use Only - General]

Hi Daniel

Thanks for your comments and explanations. I replied in-line and look forward to more discussion.

regards
David


From: Daniel Vetter <daniel@ffwll.ch>
Sent: Thursday, May 12, 2022 7:22 AM
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Zhang, Dingchen (David) <Dingchen.Zhang@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

On Wed, 11 May 2022 at 17:35, Alex Deucher <alexdeucher@gmail.com> wrote:
>
> On Tue, May 10, 2022 at 4:45 PM David Zhang <dingchen.zhang@amd.com> wrote:
> >
> > changes in v2:
> > -----------------------
> > - set vsc_packet_rev2 for PSR1 which is safer
> > - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
> > - add DC/DM change related to amdgpu PSR-SU-RC
> >
> >
> > David Zhang (18):
> >   drm/amd/display: align dmub cmd header to latest dmub FW to support
> >     PSR-SU
> >   drm/amd/display: feed PSR-SU as psr version to dmub FW
> >   drm/amd/display: combine dirty rectangles in DMUB FW
> >   drm/amd/display: update GSP1 generic info packet for PSRSU
> >   drm/amd/display: revise Start/End SDP data
> >   drm/amd/display: program PSR2 DPCD Configuration
> >   drm/amd/display: Passing Y-granularity to dmub fw
> >   drm/amd/display: Set default value of line_capture_indication
> >   drm/amd/display: add vline time in micro sec to PSR context
> >   drm/amd/display: fix system hang when PSR exits
> >   drm/amd/display: Set PSR level to enable ALPM by default
> >   drm/amd/display: use HW lock mgr for PSR-SU
> >   drm/amd/display: PSRSU+DSC WA for specific TCON
> >   drm/amd/display: add shared helpers to update psr config fields to
> >     power module
> >   drm/amd/display: calculate psr config settings in runtime in DM
> >   drm/amd/display: update cursor position to DMUB FW
> >   drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
> >     support
> >   drm/amd/display: PSR-SU rate control support in DC
> >
> > Leo Li (1):
> >   drm/amd/display: Implement MPO PSR SU
>
> A couple of suggestions from Daniel on IRC:
> 1.  Might be good to extract the "calculate total crtc damage" code
> from i915 in intel_psr2_sel_fetch_update, stuff that into damage
> helpers and reuse for i915 and amdgpu

To expand a bit on this. There is currently a helper for total damage,
but it's at the fb/plane level for drivers which need to upload
buffers (usb/spi or virtual) drm_atomic_helper_damage_merged(). That
one probably needs to be renamed to signify it's about the plane, and
then we need a new drm_atomic_helper_crtc_damage_merged() which
(extract from i915 code ideally) which computes total crtc damage for
stuff like psr2/su or the command mode dsi panels (unfortunately none
of the drivers for android for these panels have been upstreamed yet).

<<<
Checked the DRM comment for the helper `drm_atomic_helper_damage_merged()` and
quoted below:
*****
Drivers might want to use the helper functions drm_atomic_helper_damage_iter_init()
and drm_atomic_helper_damage_iter_next() or drm_atomic_helper_damage_merged()
if the driver can only handle a single damage region at most.
*****
Currently for amdgpu, the multiple damage clips combination (merging) is handled in
DMUB firmware. And the DRM comment shows that the usage of "damage_merged()"
helper is for the driver which can only handle single damage region at most.

Since AMDGPU is capable of handling multiple damaged clip (in DMUB FW), can I
understand that the group of helpers of `damage_merged()` in DRM is not mandatory
but optional?



I also think that the split between dc and kms is a bit funny, I'd put
only the resulting damage rect into dc_pipe and do the computation of
that in the drm/kms linux code outside of dc functions (or in the glue
code for dc), since I'm assuming on windows it's completely different
approach in how you compute damage. Especially once we have the crtc
damage helper on linux.

> 2.  The commit message on "drm/amd/display: Implement MPO PSR SU" is a
> bit funny, since if you use the helpers right you always get damage
> information, just when it's from userspace that doesn't set explicit
> damage it's just always the entire plane.

<<<
The current implementation to mark the entire MPO as dirt RECT is not the final
version. Our next step is to implement the translation of DRM damaged clips to
DC regions and pass to let DMUB FW to handle, which is able to handle at most
3 damaged regions for each DC surface.



Yeah so that one was just another reason to use the helpers more in
amdgpu for this.
-Daniel

>
> Alex
>
> >
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
> >  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
> >  drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
> >  drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
> >  drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
> >  drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
> >  drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
> >  .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
> >  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
> >  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
> >  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
> >  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
> >  .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
> >  .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
> >  drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
> >  .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
> >  .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
> >  .../amd/display/include/ddc_service_types.h   |   1 +
> >  .../display/modules/info_packet/info_packet.c |  29 +-
> >  .../amd/display/modules/power/power_helpers.c |  84 ++++++
> >  .../amd/display/modules/power/power_helpers.h |   6 +
> >  21 files changed, 887 insertions(+), 19 deletions(-)
> >
> > --
> > 2.25.1
> >



--
Daniel Vetter
Software Engineer, Intel Corporation
https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=05%7C01%7Cdingchen.zhang%40amd.com%7Cbf7f256980c04124f60808da3409b3d4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637879513542024968%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=tlr9ThR7DPE%2B8wv9e3n7Ud63Ju9%2FRrka4OdK1KRgeWI%3D&amp;reserved=0

Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[Daniel Vetter]

On Thu, 12 May 2022 at 19:22, Zhang, Dingchen (David)
<Dingchen.Zhang@amd.com> wrote:
>
> [AMD Official Use Only - General]
>
> Hi Daniel
>
> Thanks for your comments and explanations. I replied in-line and look forward to more discussion.
>
> regards
> David
>
>
> From: Daniel Vetter <daniel@ffwll.ch>
> Sent: Thursday, May 12, 2022 7:22 AM
> To: Alex Deucher <alexdeucher@gmail.com>
> Cc: Zhang, Dingchen (David) <Dingchen.Zhang@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
> Subject: Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU
>
> On Wed, 11 May 2022 at 17:35, Alex Deucher <alexdeucher@gmail.com> wrote:
> >
> > On Tue, May 10, 2022 at 4:45 PM David Zhang <dingchen.zhang@amd.com> wrote:
> > >
> > > changes in v2:
> > > -----------------------
> > > - set vsc_packet_rev2 for PSR1 which is safer
> > > - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
> > > - add DC/DM change related to amdgpu PSR-SU-RC
> > >
> > >
> > > David Zhang (18):
> > >   drm/amd/display: align dmub cmd header to latest dmub FW to support
> > >     PSR-SU
> > >   drm/amd/display: feed PSR-SU as psr version to dmub FW
> > >   drm/amd/display: combine dirty rectangles in DMUB FW
> > >   drm/amd/display: update GSP1 generic info packet for PSRSU
> > >   drm/amd/display: revise Start/End SDP data
> > >   drm/amd/display: program PSR2 DPCD Configuration
> > >   drm/amd/display: Passing Y-granularity to dmub fw
> > >   drm/amd/display: Set default value of line_capture_indication
> > >   drm/amd/display: add vline time in micro sec to PSR context
> > >   drm/amd/display: fix system hang when PSR exits
> > >   drm/amd/display: Set PSR level to enable ALPM by default
> > >   drm/amd/display: use HW lock mgr for PSR-SU
> > >   drm/amd/display: PSRSU+DSC WA for specific TCON
> > >   drm/amd/display: add shared helpers to update psr config fields to
> > >     power module
> > >   drm/amd/display: calculate psr config settings in runtime in DM
> > >   drm/amd/display: update cursor position to DMUB FW
> > >   drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
> > >     support
> > >   drm/amd/display: PSR-SU rate control support in DC
> > >
> > > Leo Li (1):
> > >   drm/amd/display: Implement MPO PSR SU
> >
> > A couple of suggestions from Daniel on IRC:
> > 1.  Might be good to extract the "calculate total crtc damage" code
> > from i915 in intel_psr2_sel_fetch_update, stuff that into damage
> > helpers and reuse for i915 and amdgpu
>
> To expand a bit on this. There is currently a helper for total damage,
> but it's at the fb/plane level for drivers which need to upload
> buffers (usb/spi or virtual) drm_atomic_helper_damage_merged(). That
> one probably needs to be renamed to signify it's about the plane, and
> then we need a new drm_atomic_helper_crtc_damage_merged() which
> (extract from i915 code ideally) which computes total crtc damage for
> stuff like psr2/su or the command mode dsi panels (unfortunately none
> of the drivers for android for these panels have been upstreamed yet).
>
> <<<
> Checked the DRM comment for the helper `drm_atomic_helper_damage_merged()` and
> quoted below:
> *****
> Drivers might want to use the helper functions drm_atomic_helper_damage_iter_init()
> and drm_atomic_helper_damage_iter_next() or drm_atomic_helper_damage_merged()
> if the driver can only handle a single damage region at most.
> *****
> Currently for amdgpu, the multiple damage clips combination (merging) is handled in
> DMUB firmware. And the DRM comment shows that the usage of "damage_merged()"
> helper is for the driver which can only handle single damage region at most.
>
> Since AMDGPU is capable of handling multiple damaged clip (in DMUB FW), can I
> understand that the group of helpers of `damage_merged()` in DRM is not mandatory
> but optional?

Ah I didn't see from a quick read that this was possible. How does
this work when the plane is enabled/disabled or resized or moved?
-Daniel

> I also think that the split between dc and kms is a bit funny, I'd put
> only the resulting damage rect into dc_pipe and do the computation of
> that in the drm/kms linux code outside of dc functions (or in the glue
> code for dc), since I'm assuming on windows it's completely different
> approach in how you compute damage. Especially once we have the crtc
> damage helper on linux.
>
> > 2.  The commit message on "drm/amd/display: Implement MPO PSR SU" is a
> > bit funny, since if you use the helpers right you always get damage
> > information, just when it's from userspace that doesn't set explicit
> > damage it's just always the entire plane.
>
> <<<
> The current implementation to mark the entire MPO as dirt RECT is not the final
> version. Our next step is to implement the translation of DRM damaged clips to
> DC regions and pass to let DMUB FW to handle, which is able to handle at most
> 3 damaged regions for each DC surface.
>
>
>
> Yeah so that one was just another reason to use the helpers more in
> amdgpu for this.
> -Daniel
>
> >
> > Alex
> >
> > >
> > >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
> > >  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
> > >  drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
> > >  drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
> > >  drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
> > >  drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
> > >  drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
> > >  .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
> > >  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
> > >  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
> > >  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
> > >  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
> > >  .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
> > >  .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
> > >  drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
> > >  .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
> > >  .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
> > >  .../amd/display/include/ddc_service_types.h   |   1 +
> > >  .../display/modules/info_packet/info_packet.c |  29 +-
> > >  .../amd/display/modules/power/power_helpers.c |  84 ++++++
> > >  .../amd/display/modules/power/power_helpers.h |   6 +
> > >  21 files changed, 887 insertions(+), 19 deletions(-)
> > >
> > > --
> > > 2.25.1
> > >
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=05%7C01%7Cdingchen.zhang%40amd.com%7Cbf7f256980c04124f60808da3409b3d4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637879513542024968%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=tlr9ThR7DPE%2B8wv9e3n7Ud63Ju9%2FRrka4OdK1KRgeWI%3D&amp;reserved=0



-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[Leo Li]

On 2022-05-12 13:39, Daniel Vetter wrote:
> On Thu, 12 May 2022 at 19:22, Zhang, Dingchen (David)
> <Dingchen.Zhang@amd.com> wrote:
>>
>> [AMD Official Use Only - General]
>>
>> Hi Daniel
>>
>> Thanks for your comments and explanations. I replied in-line and look forward to more discussion.
>>
>> regards
>> David
>>
>>
>> From: Daniel Vetter <daniel@ffwll.ch>
>> Sent: Thursday, May 12, 2022 7:22 AM
>> To: Alex Deucher <alexdeucher@gmail.com>
>> Cc: Zhang, Dingchen (David) <Dingchen.Zhang@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
>> Subject: Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU
>>
>> On Wed, 11 May 2022 at 17:35, Alex Deucher <alexdeucher@gmail.com> wrote:
>>>
>>> On Tue, May 10, 2022 at 4:45 PM David Zhang <dingchen.zhang@amd.com> wrote:
>>>>
>>>> changes in v2:
>>>> -----------------------
>>>> - set vsc_packet_rev2 for PSR1 which is safer
>>>> - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
>>>> - add DC/DM change related to amdgpu PSR-SU-RC
>>>>
>>>>
>>>> David Zhang (18):
>>>>    drm/amd/display: align dmub cmd header to latest dmub FW to support
>>>>      PSR-SU
>>>>    drm/amd/display: feed PSR-SU as psr version to dmub FW
>>>>    drm/amd/display: combine dirty rectangles in DMUB FW
>>>>    drm/amd/display: update GSP1 generic info packet for PSRSU
>>>>    drm/amd/display: revise Start/End SDP data
>>>>    drm/amd/display: program PSR2 DPCD Configuration
>>>>    drm/amd/display: Passing Y-granularity to dmub fw
>>>>    drm/amd/display: Set default value of line_capture_indication
>>>>    drm/amd/display: add vline time in micro sec to PSR context
>>>>    drm/amd/display: fix system hang when PSR exits
>>>>    drm/amd/display: Set PSR level to enable ALPM by default
>>>>    drm/amd/display: use HW lock mgr for PSR-SU
>>>>    drm/amd/display: PSRSU+DSC WA for specific TCON
>>>>    drm/amd/display: add shared helpers to update psr config fields to
>>>>      power module
>>>>    drm/amd/display: calculate psr config settings in runtime in DM
>>>>    drm/amd/display: update cursor position to DMUB FW
>>>>    drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
>>>>      support
>>>>    drm/amd/display: PSR-SU rate control support in DC
>>>>
>>>> Leo Li (1):
>>>>    drm/amd/display: Implement MPO PSR SU
>>>
>>> A couple of suggestions from Daniel on IRC:
>>> 1.  Might be good to extract the "calculate total crtc damage" code
>>> from i915 in intel_psr2_sel_fetch_update, stuff that into damage
>>> helpers and reuse for i915 and amdgpu
>>
>> To expand a bit on this. There is currently a helper for total damage,
>> but it's at the fb/plane level for drivers which need to upload
>> buffers (usb/spi or virtual) drm_atomic_helper_damage_merged(). That
>> one probably needs to be renamed to signify it's about the plane, and
>> then we need a new drm_atomic_helper_crtc_damage_merged() which
>> (extract from i915 code ideally) which computes total crtc damage for
>> stuff like psr2/su or the command mode dsi panels (unfortunately none
>> of the drivers for android for these panels have been upstreamed yet).
>>
>> <<<
>> Checked the DRM comment for the helper `drm_atomic_helper_damage_merged()` and
>> quoted below:
>> *****
>> Drivers might want to use the helper functions drm_atomic_helper_damage_iter_init()
>> and drm_atomic_helper_damage_iter_next() or drm_atomic_helper_damage_merged()
>> if the driver can only handle a single damage region at most.
>> *****
>> Currently for amdgpu, the multiple damage clips combination (merging) is handled in
>> DMUB firmware. And the DRM comment shows that the usage of "damage_merged()"
>> helper is for the driver which can only handle single damage region at most.
>>
>> Since AMDGPU is capable of handling multiple damaged clip (in DMUB FW), can I
>> understand that the group of helpers of `damage_merged()` in DRM is not mandatory
>> but optional?
> 
> Ah I didn't see from a quick read that this was possible. How does
> this work when the plane is enabled/disabled or resized or moved?
> -Daniel

Hi Daniel,

When a plane is disabled, enabled, and/or resized(*), PSR is temporarily 
disabled. The mechanism to do so isn't in this patchset, but was added 
when PSR1 was first introduced to amdgpu_dm.

In short, amdgpu_dm will disable PSR whenever DC requires a full update 
to program an atomic state (needs bandwidth recalculations and/or 
shuffling hw resources). For DC, enabling, disabling, and changing the 
scaling of a plane are considered full updates.

When the plane is moved, both the old and new plane bounds are given to 
FW as dirty rectangles. (*)Resize should fall under the same bucket, 
though DC would consider that as a full update. I think disabling PSR 
would take precedence... will give this another spin to check.

Thanks,
Leo

> 
>> I also think that the split between dc and kms is a bit funny, I'd put
>> only the resulting damage rect into dc_pipe and do the computation of
>> that in the drm/kms linux code outside of dc functions (or in the glue
>> code for dc), since I'm assuming on windows it's completely different
>> approach in how you compute damage. Especially once we have the crtc
>> damage helper on linux.
>>
>>> 2.  The commit message on "drm/amd/display: Implement MPO PSR SU" is a
>>> bit funny, since if you use the helpers right you always get damage
>>> information, just when it's from userspace that doesn't set explicit
>>> damage it's just always the entire plane.
>>
>> <<<
>> The current implementation to mark the entire MPO as dirt RECT is not the final
>> version. Our next step is to implement the translation of DRM damaged clips to
>> DC regions and pass to let DMUB FW to handle, which is able to handle at most
>> 3 damaged regions for each DC surface.
>>
>>
>>
>> Yeah so that one was just another reason to use the helpers more in
>> amdgpu for this.
>> -Daniel
>>
>>>
>>> Alex
>>>
>>>>
>>>>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
>>>>   .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
>>>>   drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
>>>>   drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
>>>>   drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
>>>>   drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
>>>>   drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
>>>>   .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
>>>>   drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
>>>>   drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
>>>>   .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
>>>>   .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
>>>>   .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
>>>>   .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
>>>>   drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
>>>>   .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
>>>>   .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
>>>>   .../amd/display/include/ddc_service_types.h   |   1 +
>>>>   .../display/modules/info_packet/info_packet.c |  29 +-
>>>>   .../amd/display/modules/power/power_helpers.c |  84 ++++++
>>>>   .../amd/display/modules/power/power_helpers.h |   6 +
>>>>   21 files changed, 887 insertions(+), 19 deletions(-)
>>>>
>>>> --
>>>> 2.25.1
>>>>
>>
>>
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=05%7C01%7CSunpeng.Li%40amd.com%7C2e39f7cf022f46ee917b08da343e5867%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637879739624499442%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=5Scos4KwScr%2F5MRPprq%2B0uyp76QRPDNRDt04afOVm5Y%3D&amp;reserved=0
> 
> 
> 

Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[Daniel Vetter]

On Mon, 16 May 2022 at 18:23, Leo Li <sunpeng.li@amd.com> wrote:
>
>
>
> On 2022-05-12 13:39, Daniel Vetter wrote:
> > On Thu, 12 May 2022 at 19:22, Zhang, Dingchen (David)
> > <Dingchen.Zhang@amd.com> wrote:
> >>
> >> [AMD Official Use Only - General]
> >>
> >> Hi Daniel
> >>
> >> Thanks for your comments and explanations. I replied in-line and look forward to more discussion.
> >>
> >> regards
> >> David
> >>
> >>
> >> From: Daniel Vetter <daniel@ffwll.ch>
> >> Sent: Thursday, May 12, 2022 7:22 AM
> >> To: Alex Deucher <alexdeucher@gmail.com>
> >> Cc: Zhang, Dingchen (David) <Dingchen.Zhang@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
> >> Subject: Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU
> >>
> >> On Wed, 11 May 2022 at 17:35, Alex Deucher <alexdeucher@gmail.com> wrote:
> >>>
> >>> On Tue, May 10, 2022 at 4:45 PM David Zhang <dingchen.zhang@amd.com> wrote:
> >>>>
> >>>> changes in v2:
> >>>> -----------------------
> >>>> - set vsc_packet_rev2 for PSR1 which is safer
> >>>> - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
> >>>> - add DC/DM change related to amdgpu PSR-SU-RC
> >>>>
> >>>>
> >>>> David Zhang (18):
> >>>>    drm/amd/display: align dmub cmd header to latest dmub FW to support
> >>>>      PSR-SU
> >>>>    drm/amd/display: feed PSR-SU as psr version to dmub FW
> >>>>    drm/amd/display: combine dirty rectangles in DMUB FW
> >>>>    drm/amd/display: update GSP1 generic info packet for PSRSU
> >>>>    drm/amd/display: revise Start/End SDP data
> >>>>    drm/amd/display: program PSR2 DPCD Configuration
> >>>>    drm/amd/display: Passing Y-granularity to dmub fw
> >>>>    drm/amd/display: Set default value of line_capture_indication
> >>>>    drm/amd/display: add vline time in micro sec to PSR context
> >>>>    drm/amd/display: fix system hang when PSR exits
> >>>>    drm/amd/display: Set PSR level to enable ALPM by default
> >>>>    drm/amd/display: use HW lock mgr for PSR-SU
> >>>>    drm/amd/display: PSRSU+DSC WA for specific TCON
> >>>>    drm/amd/display: add shared helpers to update psr config fields to
> >>>>      power module
> >>>>    drm/amd/display: calculate psr config settings in runtime in DM
> >>>>    drm/amd/display: update cursor position to DMUB FW
> >>>>    drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
> >>>>      support
> >>>>    drm/amd/display: PSR-SU rate control support in DC
> >>>>
> >>>> Leo Li (1):
> >>>>    drm/amd/display: Implement MPO PSR SU
> >>>
> >>> A couple of suggestions from Daniel on IRC:
> >>> 1.  Might be good to extract the "calculate total crtc damage" code
> >>> from i915 in intel_psr2_sel_fetch_update, stuff that into damage
> >>> helpers and reuse for i915 and amdgpu
> >>
> >> To expand a bit on this. There is currently a helper for total damage,
> >> but it's at the fb/plane level for drivers which need to upload
> >> buffers (usb/spi or virtual) drm_atomic_helper_damage_merged(). That
> >> one probably needs to be renamed to signify it's about the plane, and
> >> then we need a new drm_atomic_helper_crtc_damage_merged() which
> >> (extract from i915 code ideally) which computes total crtc damage for
> >> stuff like psr2/su or the command mode dsi panels (unfortunately none
> >> of the drivers for android for these panels have been upstreamed yet).
> >>
> >> <<<
> >> Checked the DRM comment for the helper `drm_atomic_helper_damage_merged()` and
> >> quoted below:
> >> *****
> >> Drivers might want to use the helper functions drm_atomic_helper_damage_iter_init()
> >> and drm_atomic_helper_damage_iter_next() or drm_atomic_helper_damage_merged()
> >> if the driver can only handle a single damage region at most.
> >> *****
> >> Currently for amdgpu, the multiple damage clips combination (merging) is handled in
> >> DMUB firmware. And the DRM comment shows that the usage of "damage_merged()"
> >> helper is for the driver which can only handle single damage region at most.
> >>
> >> Since AMDGPU is capable of handling multiple damaged clip (in DMUB FW), can I
> >> understand that the group of helpers of `damage_merged()` in DRM is not mandatory
> >> but optional?
> >
> > Ah I didn't see from a quick read that this was possible. How does
> > this work when the plane is enabled/disabled or resized or moved?
> > -Daniel
>
> Hi Daniel,
>
> When a plane is disabled, enabled, and/or resized(*), PSR is temporarily
> disabled. The mechanism to do so isn't in this patchset, but was added
> when PSR1 was first introduced to amdgpu_dm.
>
> In short, amdgpu_dm will disable PSR whenever DC requires a full update
> to program an atomic state (needs bandwidth recalculations and/or
> shuffling hw resources). For DC, enabling, disabling, and changing the
> scaling of a plane are considered full updates.
>
> When the plane is moved, both the old and new plane bounds are given to
> FW as dirty rectangles. (*)Resize should fall under the same bucket,
> though DC would consider that as a full update. I think disabling PSR
> would take precedence... will give this another spin to check.

That sounds a bit suboptimal with compositors that want to maximize
plane usage, but I guess if your hw can't do anything (i.e. no upload
rectangle that's in crtc coordinates) then that's just what it is. And
for that case I guess there's not much more helpers that make sense to
share, since the hw is just so different than what I've heard about
thus far.

Ofc if all these limitations are just DC and not the hw, then that
would indicate DC has become a midlayer in this area and needs to
expose the actual hw interface and all that, but sounds like that's
not the case. Just fairly strange hw design.

Cheers, Daniel

>
> Thanks,
> Leo
>
> >
> >> I also think that the split between dc and kms is a bit funny, I'd put
> >> only the resulting damage rect into dc_pipe and do the computation of
> >> that in the drm/kms linux code outside of dc functions (or in the glue
> >> code for dc), since I'm assuming on windows it's completely different
> >> approach in how you compute damage. Especially once we have the crtc
> >> damage helper on linux.
> >>
> >>> 2.  The commit message on "drm/amd/display: Implement MPO PSR SU" is a
> >>> bit funny, since if you use the helpers right you always get damage
> >>> information, just when it's from userspace that doesn't set explicit
> >>> damage it's just always the entire plane.
> >>
> >> <<<
> >> The current implementation to mark the entire MPO as dirt RECT is not the final
> >> version. Our next step is to implement the translation of DRM damaged clips to
> >> DC regions and pass to let DMUB FW to handle, which is able to handle at most
> >> 3 damaged regions for each DC surface.
> >>
> >>
> >>
> >> Yeah so that one was just another reason to use the helpers more in
> >> amdgpu for this.
> >> -Daniel
> >>
> >>>
> >>> Alex
> >>>
> >>>>
> >>>>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
> >>>>   .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
> >>>>   drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
> >>>>   drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
> >>>>   drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
> >>>>   drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
> >>>>   drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
> >>>>   .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
> >>>>   drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
> >>>>   drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
> >>>>   .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
> >>>>   .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
> >>>>   .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
> >>>>   .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
> >>>>   drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
> >>>>   .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
> >>>>   .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
> >>>>   .../amd/display/include/ddc_service_types.h   |   1 +
> >>>>   .../display/modules/info_packet/info_packet.c |  29 +-
> >>>>   .../amd/display/modules/power/power_helpers.c |  84 ++++++
> >>>>   .../amd/display/modules/power/power_helpers.h |   6 +
> >>>>   21 files changed, 887 insertions(+), 19 deletions(-)
> >>>>
> >>>> --
> >>>> 2.25.1
> >>>>
> >>
> >>
> >>
> >> --
> >> Daniel Vetter
> >> Software Engineer, Intel Corporation
> >> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=05%7C01%7CSunpeng.Li%40amd.com%7C2e39f7cf022f46ee917b08da343e5867%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637879739624499442%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=5Scos4KwScr%2F5MRPprq%2B0uyp76QRPDNRDt04afOVm5Y%3D&amp;reserved=0
> >
> >
> >



-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU

[Harry Wentland]

Patches 1-18 are
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Patch 19 needs a bit more of a patch description.

Harry

On 5/10/22 16:44, David Zhang wrote:
> changes in v2:
> -----------------------
> - set vsc_packet_rev2 for PSR1 which is safer
> - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
> - add DC/DM change related to amdgpu PSR-SU-RC
> 
> 
> David Zhang (18):
>   drm/amd/display: align dmub cmd header to latest dmub FW to support
>     PSR-SU
>   drm/amd/display: feed PSR-SU as psr version to dmub FW
>   drm/amd/display: combine dirty rectangles in DMUB FW
>   drm/amd/display: update GSP1 generic info packet for PSRSU
>   drm/amd/display: revise Start/End SDP data
>   drm/amd/display: program PSR2 DPCD Configuration
>   drm/amd/display: Passing Y-granularity to dmub fw
>   drm/amd/display: Set default value of line_capture_indication
>   drm/amd/display: add vline time in micro sec to PSR context
>   drm/amd/display: fix system hang when PSR exits
>   drm/amd/display: Set PSR level to enable ALPM by default
>   drm/amd/display: use HW lock mgr for PSR-SU
>   drm/amd/display: PSRSU+DSC WA for specific TCON
>   drm/amd/display: add shared helpers to update psr config fields to
>     power module
>   drm/amd/display: calculate psr config settings in runtime in DM
>   drm/amd/display: update cursor position to DMUB FW
>   drm/amd/display: expose AMD source specific DPCD for FreeSync PSR
>     support
>   drm/amd/display: PSR-SU rate control support in DC
> 
> Leo Li (1):
>   drm/amd/display: Implement MPO PSR SU
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 142 +++++++++-
>  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |  21 +-
>  drivers/gpu/drm/amd/display/dc/core/dc.c      |  54 ++++
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++-
>  drivers/gpu/drm/amd/display/dc/dc_link.h      |   4 +
>  drivers/gpu/drm/amd/display/dc/dc_stream.h    |   5 +
>  drivers/gpu/drm/amd/display/dc/dc_types.h     |  23 +-
>  .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   2 +
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  64 +++++
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |   2 +
>  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   2 +
>  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 131 +++++++++
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |   2 +
>  .../dc/dcn30/dcn30_dio_stream_encoder.c       |  15 ++
>  drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   1 +
>  .../drm/amd/display/dc/inc/hw/link_encoder.h  |  21 +-
>  .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 250 +++++++++++++++++-
>  .../amd/display/include/ddc_service_types.h   |   1 +
>  .../display/modules/info_packet/info_packet.c |  29 +-
>  .../amd/display/modules/power/power_helpers.c |  84 ++++++
>  .../amd/display/modules/power/power_helpers.h |   6 +
>  21 files changed, 887 insertions(+), 19 deletions(-)
>