From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Anup Patel <anup@brainfault.org>, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Tue, 26 Jul 2022 19:06:23 +0100 [thread overview] Message-ID: <20220726180623.1668-7-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP Single). Below is the list of IP blocks added in the initial SoC DTSI which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - CPG - PINCTRL - PLIC - SCIF0 - SYSC Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi new file mode 100644 index 000000000000..6e0b640c6c7f --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a07g043-cpg.h> + +/ { + compatible = "renesas,r9a07g043"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + ax45mp: cpu@0 { + compatible = "andestech,ax45mp", "riscv"; + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>, + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, + <414 IRQ_TYPE_LEVEL_HIGH>, + <415 IRQ_TYPE_LEVEL_HIGH>, + <413 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; + }; + + plic: interrupt-controller@12c00000 { + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells = <2>; + #address-cells = <0>; + riscv,ndev = <543>; + interrupt-controller; + reg = <0x0 0x12c00000 0 0x400000>; + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; + }; + }; +}; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Anup Patel <anup@brainfault.org>, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Tue, 26 Jul 2022 19:06:23 +0100 [thread overview] Message-ID: <20220726180623.1668-7-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw) In-Reply-To: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP Single). Below is the list of IP blocks added in the initial SoC DTSI which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - CPG - PINCTRL - PLIC - SCIF0 - SYSC Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi new file mode 100644 index 000000000000..6e0b640c6c7f --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a07g043-cpg.h> + +/ { + compatible = "renesas,r9a07g043"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + ax45mp: cpu@0 { + compatible = "andestech,ax45mp", "riscv"; + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>, + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, + <414 IRQ_TYPE_LEVEL_HIGH>, + <415 IRQ_TYPE_LEVEL_HIGH>, + <413 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; + }; + + plic: interrupt-controller@12c00000 { + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells = <2>; + #address-cells = <0>; + riscv,ndev = <543>; + interrupt-controller; + reg = <0x0 0x12c00000 0 0x400000>; + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; + }; + }; +}; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-07-26 18:07 UTC|newest] Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-26 18:06 [PATCH 0/6] Add support for Renesas RZ/Five SoC Lad Prabhakar 2022-07-26 18:06 ` Lad Prabhakar 2022-07-26 18:06 ` [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch Lad Prabhakar 2022-07-26 18:06 ` Lad Prabhakar 2022-07-27 8:50 ` Krzysztof Kozlowski 2022-07-27 8:50 ` Krzysztof Kozlowski 2022-07-27 8:55 ` Lad, Prabhakar 2022-07-27 8:55 ` Lad, Prabhakar 2022-07-27 8:53 ` Krzysztof Kozlowski 2022-07-27 8:53 ` Krzysztof Kozlowski 2022-07-27 9:00 ` Lad, Prabhakar 2022-07-27 9:00 ` Lad, Prabhakar 2022-07-27 9:31 ` Krzysztof Kozlowski 2022-07-27 9:31 ` Krzysztof Kozlowski 2022-07-27 9:48 ` Lad, Prabhakar 2022-07-27 9:48 ` Lad, Prabhakar 2022-08-11 15:26 ` Geert Uytterhoeven 2022-08-11 15:26 ` Geert Uytterhoeven 2022-08-11 23:37 ` Lad, Prabhakar 2022-08-11 23:37 ` Lad, Prabhakar 2022-07-27 15:43 ` Rob Herring 2022-07-27 15:43 ` Rob Herring 2022-07-26 18:06 ` [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar 2022-07-26 18:06 ` Lad Prabhakar 2022-07-27 8:51 ` Krzysztof Kozlowski 2022-07-27 8:51 ` Krzysztof Kozlowski 2022-07-26 18:06 ` [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar 2022-07-26 18:06 ` Lad Prabhakar 2022-07-27 8:51 ` Krzysztof Kozlowski 2022-07-27 8:51 ` Krzysztof Kozlowski 2022-07-26 18:06 ` [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Lad Prabhakar 2022-07-26 18:06 ` Lad Prabhakar 2022-07-27 8:54 ` Krzysztof Kozlowski 2022-07-27 8:54 ` Krzysztof Kozlowski 2022-07-27 9:05 ` Lad, Prabhakar 2022-07-27 9:05 ` Lad, Prabhakar 2022-07-27 9:27 ` Biju Das 2022-07-27 9:27 ` Biju Das 2022-07-27 9:35 ` Lad, Prabhakar 2022-07-27 9:35 ` Lad, Prabhakar 2022-07-27 9:54 ` Krzysztof Kozlowski 2022-07-27 9:54 ` Krzysztof Kozlowski 2022-07-27 10:06 ` Lad, Prabhakar 2022-07-27 10:06 ` Lad, Prabhakar 2022-07-27 10:09 ` Krzysztof Kozlowski 2022-07-27 10:09 ` Krzysztof Kozlowski 2022-07-27 11:37 ` Lad, Prabhakar 2022-07-27 11:37 ` Lad, Prabhakar 2022-07-27 11:44 ` Krzysztof Kozlowski 2022-07-27 11:44 ` Krzysztof Kozlowski 2022-07-27 12:21 ` Biju Das 2022-07-27 12:21 ` Biju Das 2022-07-27 12:36 ` Krzysztof Kozlowski 2022-07-27 12:36 ` Krzysztof Kozlowski 2022-07-27 12:56 ` Biju Das 2022-07-27 12:56 ` Biju Das 2022-07-27 13:00 ` Krzysztof Kozlowski 2022-07-27 13:00 ` Krzysztof Kozlowski 2022-07-27 13:29 ` Conor.Dooley 2022-07-27 13:29 ` Conor.Dooley 2022-07-27 15:32 ` Lad, Prabhakar 2022-07-27 15:32 ` Lad, Prabhakar 2022-08-11 15:42 ` Geert Uytterhoeven 2022-08-11 15:42 ` Geert Uytterhoeven 2022-08-12 6:23 ` Krzysztof Kozlowski 2022-08-12 6:23 ` Krzysztof Kozlowski 2022-08-12 9:49 ` Lad, Prabhakar 2022-08-12 9:49 ` Lad, Prabhakar 2022-08-12 15:10 ` Palmer Dabbelt 2022-08-12 15:10 ` Palmer Dabbelt 2022-07-26 18:06 ` [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar 2022-07-26 18:06 ` Lad Prabhakar 2022-07-26 18:49 ` Conor.Dooley 2022-07-26 18:49 ` Conor.Dooley 2022-07-27 8:19 ` Lad, Prabhakar 2022-07-27 8:19 ` Lad, Prabhakar 2022-07-26 18:06 ` Lad Prabhakar [this message] 2022-07-26 18:06 ` [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar 2022-07-26 18:25 ` Conor.Dooley 2022-07-26 18:25 ` Conor.Dooley 2022-07-26 18:53 ` Conor.Dooley 2022-07-26 18:53 ` Conor.Dooley 2022-07-27 8:09 ` Lad, Prabhakar 2022-07-27 8:09 ` Lad, Prabhakar 2022-07-27 8:21 ` Conor.Dooley 2022-07-27 8:21 ` Conor.Dooley 2022-07-27 8:30 ` Lad, Prabhakar 2022-07-27 8:30 ` Lad, Prabhakar 2022-07-27 8:55 ` Krzysztof Kozlowski 2022-07-27 8:55 ` Krzysztof Kozlowski 2022-07-27 9:08 ` Lad, Prabhakar 2022-07-27 9:08 ` Lad, Prabhakar 2022-07-26 18:51 ` [PATCH 0/6] Add support " Conor.Dooley 2022-07-26 18:51 ` Conor.Dooley 2022-07-27 8:00 ` Lad, Prabhakar 2022-07-27 8:00 ` Lad, Prabhakar
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