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From: Palmer Dabbelt <palmer@dabbelt.com>
To: krzysztof.kozlowski@linaro.org
Cc: geert@linux-m68k.org, biju.das.jz@bp.renesas.com,
	prabhakar.csengg@gmail.com,
	prabhakar.mahadev-lad.rj@bp.renesas.com, magnus.damm@gmail.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	aou@eecs.berkeley.edu, anup@brainfault.org,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
Date: Fri, 12 Aug 2022 08:10:43 -0700 (PDT)	[thread overview]
Message-ID: <mhng-16e843f9-aba2-41fe-9027-8362472fc7d7@palmer-mbp2014> (raw)
In-Reply-To: <1aa477b2-1d91-066e-5fcd-849ece62388d@linaro.org>

On Thu, 11 Aug 2022 23:23:10 PDT (-0700), krzysztof.kozlowski@linaro.org wrote:
> On 11/08/2022 18:42, Geert Uytterhoeven wrote:
>> At the DT validation level, I think the proper solution is to
>> merge Documentation/devicetree/bindings/arm/renesas.yaml and
>> Documentation/devicetree/bindings/riscv/renesas.yaml into a single
>> file under Documentation/devicetree/bindings/soc/renesas/.
>>
>> What do other people think?
>
> I am ok with it.

Seems reasonable to me too, but I pretty much always err on the side of 
keeping SOC stuff split out from the RISC-V stuff.  Just looking at 
Documentation/devicetree/bindings/riscv/, it's pretty much all SOC stuff 
-- should we just move everything but cpus.yaml over?

WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com>
To: krzysztof.kozlowski@linaro.org
Cc: geert@linux-m68k.org, biju.das.jz@bp.renesas.com,
	prabhakar.csengg@gmail.com,
	prabhakar.mahadev-lad.rj@bp.renesas.com, magnus.damm@gmail.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	aou@eecs.berkeley.edu, anup@brainfault.org,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
Date: Fri, 12 Aug 2022 08:10:43 -0700 (PDT)	[thread overview]
Message-ID: <mhng-16e843f9-aba2-41fe-9027-8362472fc7d7@palmer-mbp2014> (raw)
In-Reply-To: <1aa477b2-1d91-066e-5fcd-849ece62388d@linaro.org>

On Thu, 11 Aug 2022 23:23:10 PDT (-0700), krzysztof.kozlowski@linaro.org wrote:
> On 11/08/2022 18:42, Geert Uytterhoeven wrote:
>> At the DT validation level, I think the proper solution is to
>> merge Documentation/devicetree/bindings/arm/renesas.yaml and
>> Documentation/devicetree/bindings/riscv/renesas.yaml into a single
>> file under Documentation/devicetree/bindings/soc/renesas/.
>>
>> What do other people think?
>
> I am ok with it.

Seems reasonable to me too, but I pretty much always err on the side of 
keeping SOC stuff split out from the RISC-V stuff.  Just looking at 
Documentation/devicetree/bindings/riscv/, it's pretty much all SOC stuff 
-- should we just move everything but cpus.yaml over?

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2022-08-12 15:10 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-26 18:06 [PATCH 0/6] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-26 18:06 ` [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch Lad Prabhakar
2022-07-26 18:06   ` Lad Prabhakar
2022-07-27  8:50   ` Krzysztof Kozlowski
2022-07-27  8:50     ` Krzysztof Kozlowski
2022-07-27  8:55     ` Lad, Prabhakar
2022-07-27  8:55       ` Lad, Prabhakar
2022-07-27  8:53   ` Krzysztof Kozlowski
2022-07-27  8:53     ` Krzysztof Kozlowski
2022-07-27  9:00     ` Lad, Prabhakar
2022-07-27  9:00       ` Lad, Prabhakar
2022-07-27  9:31       ` Krzysztof Kozlowski
2022-07-27  9:31         ` Krzysztof Kozlowski
2022-07-27  9:48         ` Lad, Prabhakar
2022-07-27  9:48           ` Lad, Prabhakar
2022-08-11 15:26           ` Geert Uytterhoeven
2022-08-11 15:26             ` Geert Uytterhoeven
2022-08-11 23:37             ` Lad, Prabhakar
2022-08-11 23:37               ` Lad, Prabhakar
2022-07-27 15:43   ` Rob Herring
2022-07-27 15:43     ` Rob Herring
2022-07-26 18:06 ` [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-07-26 18:06   ` Lad Prabhakar
2022-07-27  8:51   ` Krzysztof Kozlowski
2022-07-27  8:51     ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-07-26 18:06   ` Lad Prabhakar
2022-07-27  8:51   ` Krzysztof Kozlowski
2022-07-27  8:51     ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Lad Prabhakar
2022-07-26 18:06   ` Lad Prabhakar
2022-07-27  8:54   ` Krzysztof Kozlowski
2022-07-27  8:54     ` Krzysztof Kozlowski
2022-07-27  9:05     ` Lad, Prabhakar
2022-07-27  9:05       ` Lad, Prabhakar
2022-07-27  9:27       ` Biju Das
2022-07-27  9:27         ` Biju Das
2022-07-27  9:35         ` Lad, Prabhakar
2022-07-27  9:35           ` Lad, Prabhakar
2022-07-27  9:54       ` Krzysztof Kozlowski
2022-07-27  9:54         ` Krzysztof Kozlowski
2022-07-27 10:06         ` Lad, Prabhakar
2022-07-27 10:06           ` Lad, Prabhakar
2022-07-27 10:09           ` Krzysztof Kozlowski
2022-07-27 10:09             ` Krzysztof Kozlowski
2022-07-27 11:37             ` Lad, Prabhakar
2022-07-27 11:37               ` Lad, Prabhakar
2022-07-27 11:44               ` Krzysztof Kozlowski
2022-07-27 11:44                 ` Krzysztof Kozlowski
2022-07-27 12:21                 ` Biju Das
2022-07-27 12:21                   ` Biju Das
2022-07-27 12:36                   ` Krzysztof Kozlowski
2022-07-27 12:36                     ` Krzysztof Kozlowski
2022-07-27 12:56                     ` Biju Das
2022-07-27 12:56                       ` Biju Das
2022-07-27 13:00                       ` Krzysztof Kozlowski
2022-07-27 13:00                         ` Krzysztof Kozlowski
2022-07-27 13:29                         ` Conor.Dooley
2022-07-27 13:29                           ` Conor.Dooley
2022-07-27 15:32                           ` Lad, Prabhakar
2022-07-27 15:32                             ` Lad, Prabhakar
2022-08-11 15:42                     ` Geert Uytterhoeven
2022-08-11 15:42                       ` Geert Uytterhoeven
2022-08-12  6:23                       ` Krzysztof Kozlowski
2022-08-12  6:23                         ` Krzysztof Kozlowski
2022-08-12  9:49                         ` Lad, Prabhakar
2022-08-12  9:49                           ` Lad, Prabhakar
2022-08-12 15:10                         ` Palmer Dabbelt [this message]
2022-08-12 15:10                           ` Palmer Dabbelt
2022-07-26 18:06 ` [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-07-26 18:06   ` Lad Prabhakar
2022-07-26 18:49   ` Conor.Dooley
2022-07-26 18:49     ` Conor.Dooley
2022-07-27  8:19     ` Lad, Prabhakar
2022-07-27  8:19       ` Lad, Prabhakar
2022-07-26 18:06 ` [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06   ` Lad Prabhakar
2022-07-26 18:25   ` Conor.Dooley
2022-07-26 18:25     ` Conor.Dooley
2022-07-26 18:53     ` Conor.Dooley
2022-07-26 18:53       ` Conor.Dooley
2022-07-27  8:09     ` Lad, Prabhakar
2022-07-27  8:09       ` Lad, Prabhakar
2022-07-27  8:21       ` Conor.Dooley
2022-07-27  8:21         ` Conor.Dooley
2022-07-27  8:30         ` Lad, Prabhakar
2022-07-27  8:30           ` Lad, Prabhakar
2022-07-27  8:55   ` Krzysztof Kozlowski
2022-07-27  8:55     ` Krzysztof Kozlowski
2022-07-27  9:08     ` Lad, Prabhakar
2022-07-27  9:08       ` Lad, Prabhakar
2022-07-26 18:51 ` [PATCH 0/6] Add support " Conor.Dooley
2022-07-26 18:51   ` Conor.Dooley
2022-07-27  8:00   ` Lad, Prabhakar
2022-07-27  8:00     ` Lad, Prabhakar

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