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From: Matt Ranostay <mranostay@ti.com>
To: <nm@ti.com>, <afd@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
	<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<s-vadapalli@ti.com>, <r-gunasekaran@ti.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v7 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
Date: Tue, 22 Nov 2022 02:16:16 -0800	[thread overview]
Message-ID: <20221122101616.770050-9-mranostay@ti.com> (raw)
In-Reply-To: <20221122101616.770050-1-mranostay@ti.com>

From: Aswath Govindraju <a-govindraju@ti.com>

x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 0503e690cfaf..561d70cdee9b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -374,6 +374,13 @@ flash@0{
 	};
 };
 
+&pcie1_rc {
+	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+};
+
 &mcu_mcan0 {
 	status = "okay";
 	pinctrl-names = "default";
-- 
2.38.GIT


WARNING: multiple messages have this Message-ID (diff)
From: Matt Ranostay <mranostay@ti.com>
To: <nm@ti.com>, <afd@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
	<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<s-vadapalli@ti.com>, <r-gunasekaran@ti.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v7 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
Date: Tue, 22 Nov 2022 02:16:16 -0800	[thread overview]
Message-ID: <20221122101616.770050-9-mranostay@ti.com> (raw)
In-Reply-To: <20221122101616.770050-1-mranostay@ti.com>

From: Aswath Govindraju <a-govindraju@ti.com>

x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 0503e690cfaf..561d70cdee9b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -374,6 +374,13 @@ flash@0{
 	};
 };
 
+&pcie1_rc {
+	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+};
+
 &mcu_mcan0 {
 	status = "okay";
 	pinctrl-names = "default";
-- 
2.38.GIT


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  parent reply	other threads:[~2022-11-22 10:17 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-22 10:16 [PATCH v7 0/8] arm64: j721s2: Add support for additional IPs Matt Ranostay
2022-11-22 10:16 ` Matt Ranostay
2022-11-22 10:16 ` [PATCH v7 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB Matt Ranostay
2022-11-22 10:16   ` Matt Ranostay
2023-01-09  4:07   ` Vignesh Raghavendra
2023-01-09  4:07     ` Vignesh Raghavendra
2022-11-22 10:16 ` [PATCH v7 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Matt Ranostay
2022-11-22 10:16   ` Matt Ranostay
2022-11-23 10:35   ` Ravi Gunasekaran
2022-11-23 10:35     ` Ravi Gunasekaran
2023-01-09  4:09   ` Vignesh Raghavendra
2023-01-09  4:09     ` Vignesh Raghavendra
2022-11-22 10:16 ` [PATCH v7 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Matt Ranostay
2022-11-22 10:16   ` Matt Ranostay
2022-11-22 14:03   ` Vaishnav Achath
2022-11-22 14:03     ` Vaishnav Achath
2022-11-29 17:34   ` Andrew Davis
2022-11-29 17:34     ` Andrew Davis
2023-01-09  4:10   ` Vignesh Raghavendra
2023-01-09  4:10     ` Vignesh Raghavendra
2022-11-22 10:16 ` [PATCH v7 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Matt Ranostay
2022-11-22 10:16   ` Matt Ranostay
2022-11-22 10:16 ` [PATCH v7 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Matt Ranostay
2022-11-22 10:16   ` Matt Ranostay
2022-11-22 10:16 ` [PATCH v7 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Matt Ranostay
2022-11-22 10:16   ` Matt Ranostay
2022-11-22 14:04   ` Vaishnav Achath
2022-11-22 14:04     ` Vaishnav Achath
2022-11-22 10:16 ` [PATCH v7 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Matt Ranostay
2022-11-22 10:16   ` Matt Ranostay
2022-11-29 17:53   ` Andrew Davis
2022-11-29 17:53     ` Andrew Davis
     [not found]     ` <20230117092331.GA3277247@desktop-3598>
2023-01-17  9:32       ` Siddharth Vadapalli
2023-01-17  9:32         ` Siddharth Vadapalli
2022-11-22 10:16 ` Matt Ranostay [this message]
2022-11-22 10:16   ` [PATCH v7 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Matt Ranostay

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