From: Vaishnav Achath <vaishnav.a@ti.com> To: Matt Ranostay <mranostay@ti.com>, <nm@ti.com>, <afd@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <s-vadapalli@ti.com>, <r-gunasekaran@ti.com> Cc: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Vaishnav Achath <vaishnav.a@ti.com> Subject: Re: [PATCH v7 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Date: Tue, 22 Nov 2022 19:34:06 +0530 [thread overview] Message-ID: <e5de300b-3410-edc1-1e22-ee3d43fe783e@ti.com> (raw) In-Reply-To: <20221122101616.770050-7-mranostay@ti.com> On 22/11/22 15:46, Matt Ranostay wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a > QSPI NOR flash on the common processor board connected to the OSPI1 > instance. Add support for the same > > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > --- > .../dts/ti/k3-j721s2-common-proc-board.dts | 34 +++++++++++++++ > arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++++++++++++++ > 2 files changed, 76 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > index c787d46f89de..0503e690cfaf 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > @@ -206,6 +206,20 @@ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { > J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ > >; > }; > + > + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { > + pinctrl-single,pins = < > + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ > + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ > + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ > + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ > + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ > + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ > + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ > + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ > + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ > + >; > + }; > }; > > &main_gpio2 { > @@ -340,6 +354,26 @@ &usb0 { > maximum-speed = "high-speed"; > }; > > +&ospi1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; > + > + flash@0{ > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <40000000>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <2>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +}; > + > &mcu_mcan0 { > status = "okay"; > pinctrl-names = "default"; > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > index 6930efff8a5a..2ffea00e19d7 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > @@ -39,6 +39,28 @@ transceiver0: can-phy0 { > }; > }; > > +&wkup_pmx0 { > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { > + pinctrl-single,pins = < > + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ > + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ > + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ > + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ > + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ > + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ > + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ > + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ > + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ > + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ > + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ > + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ > + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ > + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ > + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ > + >; > + }; > +}; > + > &main_pmx0 { > main_i2c0_pins_default: main-i2c0-pins-default { > pinctrl-single,pins = < > @@ -79,3 +101,23 @@ &main_mcan16 { > pinctrl-names = "default"; > phys = <&transceiver0>; > }; > + > +&ospi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <8>; > + spi-rx-bus-width = <8>; > + spi-max-frequency = <25000000>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <4>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> > +}; -- Regards, Vaishnav
WARNING: multiple messages have this Message-ID (diff)
From: Vaishnav Achath <vaishnav.a@ti.com> To: Matt Ranostay <mranostay@ti.com>, <nm@ti.com>, <afd@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <s-vadapalli@ti.com>, <r-gunasekaran@ti.com> Cc: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Vaishnav Achath <vaishnav.a@ti.com> Subject: Re: [PATCH v7 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Date: Tue, 22 Nov 2022 19:34:06 +0530 [thread overview] Message-ID: <e5de300b-3410-edc1-1e22-ee3d43fe783e@ti.com> (raw) In-Reply-To: <20221122101616.770050-7-mranostay@ti.com> On 22/11/22 15:46, Matt Ranostay wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a > QSPI NOR flash on the common processor board connected to the OSPI1 > instance. Add support for the same > > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > --- > .../dts/ti/k3-j721s2-common-proc-board.dts | 34 +++++++++++++++ > arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++++++++++++++++ > 2 files changed, 76 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > index c787d46f89de..0503e690cfaf 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > @@ -206,6 +206,20 @@ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { > J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ > >; > }; > + > + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { > + pinctrl-single,pins = < > + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ > + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ > + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ > + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ > + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ > + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ > + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ > + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ > + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ > + >; > + }; > }; > > &main_gpio2 { > @@ -340,6 +354,26 @@ &usb0 { > maximum-speed = "high-speed"; > }; > > +&ospi1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; > + > + flash@0{ > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <1>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <40000000>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <2>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +}; > + > &mcu_mcan0 { > status = "okay"; > pinctrl-names = "default"; > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > index 6930efff8a5a..2ffea00e19d7 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi > @@ -39,6 +39,28 @@ transceiver0: can-phy0 { > }; > }; > > +&wkup_pmx0 { > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { > + pinctrl-single,pins = < > + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ > + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ > + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ > + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ > + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ > + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ > + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ > + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ > + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ > + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ > + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ > + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ > + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ > + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ > + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ > + >; > + }; > +}; > + > &main_pmx0 { > main_i2c0_pins_default: main-i2c0-pins-default { > pinctrl-single,pins = < > @@ -79,3 +101,23 @@ &main_mcan16 { > pinctrl-names = "default"; > phys = <&transceiver0>; > }; > + > +&ospi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <8>; > + spi-rx-bus-width = <8>; > + spi-max-frequency = <25000000>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <4>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> > +}; -- Regards, Vaishnav _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-11-22 14:05 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-22 10:16 [PATCH v7 0/8] arm64: j721s2: Add support for additional IPs Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2022-11-22 10:16 ` [PATCH v7 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2023-01-09 4:07 ` Vignesh Raghavendra 2023-01-09 4:07 ` Vignesh Raghavendra 2022-11-22 10:16 ` [PATCH v7 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2022-11-23 10:35 ` Ravi Gunasekaran 2022-11-23 10:35 ` Ravi Gunasekaran 2023-01-09 4:09 ` Vignesh Raghavendra 2023-01-09 4:09 ` Vignesh Raghavendra 2022-11-22 10:16 ` [PATCH v7 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2022-11-22 14:03 ` Vaishnav Achath 2022-11-22 14:03 ` Vaishnav Achath 2022-11-29 17:34 ` Andrew Davis 2022-11-29 17:34 ` Andrew Davis 2023-01-09 4:10 ` Vignesh Raghavendra 2023-01-09 4:10 ` Vignesh Raghavendra 2022-11-22 10:16 ` [PATCH v7 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2022-11-22 10:16 ` [PATCH v7 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2022-11-22 10:16 ` [PATCH v7 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2022-11-22 14:04 ` Vaishnav Achath [this message] 2022-11-22 14:04 ` Vaishnav Achath 2022-11-22 10:16 ` [PATCH v7 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay 2022-11-29 17:53 ` Andrew Davis 2022-11-29 17:53 ` Andrew Davis [not found] ` <20230117092331.GA3277247@desktop-3598> 2023-01-17 9:32 ` Siddharth Vadapalli 2023-01-17 9:32 ` Siddharth Vadapalli 2022-11-22 10:16 ` [PATCH v7 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Matt Ranostay 2022-11-22 10:16 ` Matt Ranostay
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