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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 05/15] hw/riscv/boot.c: introduce riscv_default_firmware_name()
Date: Wed, 21 Dec 2022 15:22:50 -0300	[thread overview]
Message-ID: <20221221182300.307900-6-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com>

Some boards are duplicating the 'riscv_find_and_load_firmware' call
because the 32 and 64 bits images have different names. Create
a function to handle this detail instead of hardcoding it in the boards.

Ideally we would bake this logic inside riscv_find_and_load_firmware(),
or even create a riscv_load_default_firmware(), but at this moment we
cannot infer whether the machine is running 32 or 64 bits without
accessing RISCVHartArrayState, which in turn can't be accessed via the
common code from boot.c. In the end we would exchange 'firmware_name'
for a flag with riscv_is_32bit(), which isn't much better than what we
already have today.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/boot.c         |  9 +++++++++
 hw/riscv/sifive_u.c     | 11 ++++-------
 hw/riscv/spike.c        | 14 +++++---------
 hw/riscv/virt.c         | 10 +++-------
 include/hw/riscv/boot.h |  1 +
 5 files changed, 22 insertions(+), 23 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 7361d5c0d8..e1a544b1d9 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -75,6 +75,15 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
     }
 }
 
+const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
+{
+    if (riscv_is_32bit(harts)) {
+        return RISCV32_BIOS_BIN;
+    }
+
+    return RISCV64_BIOS_BIN;
+}
+
 static char *riscv_find_firmware(const char *firmware_filename)
 {
     char *filename;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9cf66957ab..ddceb750ea 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -533,6 +533,7 @@ static void sifive_u_machine_init(MachineState *machine)
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
+    const char *firmware_name;
     uint32_t start_addr_hi32 = 0x00000000;
     int i;
     uint32_t fdt_load_addr;
@@ -595,13 +596,9 @@ static void sifive_u_machine_init(MachineState *machine)
         break;
     }
 
-    if (riscv_is_32bit(&s->soc.u_cpus)) {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_BIN, start_addr, NULL);
-    } else {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_BIN, start_addr, NULL);
-    }
+    firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+                                                     start_addr, NULL);
 
     if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index d96f013e2e..43341c20b6 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -191,6 +191,7 @@ static void spike_board_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     target_ulong firmware_end_addr, kernel_start_addr;
+    const char *firmware_name;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
     char *soc_name;
@@ -261,15 +262,10 @@ static void spike_board_init(MachineState *machine)
      * keeping ELF files here was intentional because BIN files don't work
      * for the Spike machine as HTIF emulation depends on ELF parsing.
      */
-    if (riscv_is_32bit(&s->soc[0])) {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
-                                    htif_symbol_callback);
-    } else {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
-                                    htif_symbol_callback);
-    }
+    firmware_name = riscv_default_firmware_name(&s->soc[0]);
+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+                                                     memmap[SPIKE_DRAM].base,
+                                                     htif_symbol_callback);
 
     /* Load kernel */
     if (machine->kernel_filename) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 94ff2a1584..408f7a2256 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1237,6 +1237,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
     MachineState *machine = MACHINE(s);
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
+    const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
 
@@ -1256,13 +1257,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
         }
     }
 
-    if (riscv_is_32bit(&s->soc[0])) {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_BIN, start_addr, NULL);
-    } else {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_BIN, start_addr, NULL);
-    }
+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+                                                     start_addr, NULL);
 
     /*
      * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index c03e4e74c5..60cf320c88 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -37,6 +37,7 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
                                           symbol_fn_t sym_cb);
+const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
 target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr firmware_load_addr,
                                  symbol_fn_t sym_cb);
-- 
2.38.1



  parent reply	other threads:[~2022-12-21 18:24 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-21 18:22 [PATCH 00/15] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
2022-12-21 18:22 ` [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test Daniel Henrique Barboza
2022-12-22 10:24   ` Bin Meng
2022-12-22 10:47     ` Daniel Henrique Barboza
2022-12-22 12:56       ` Bin Meng
2022-12-22 16:56         ` Anup Patel
2022-12-22 20:58           ` Daniel Henrique Barboza
2022-12-23  6:25           ` Bin Meng
2022-12-24  3:52             ` Bin Meng
2022-12-26 13:56               ` Bin Meng
2022-12-26 14:00                 ` Daniel Henrique Barboza
2022-12-27 18:02                 ` Daniel Henrique Barboza
2022-12-23  2:40   ` Alistair Francis
2022-12-27 23:04   ` Wainer dos Santos Moschetta
2022-12-21 18:22 ` [PATCH 02/15] hw/riscv/spike: use 'fdt' from MachineState Daniel Henrique Barboza
2022-12-22 14:25   ` Philippe Mathieu-Daudé
2022-12-22 16:43     ` Daniel Henrique Barboza
2022-12-23  3:10   ` Alistair Francis
2022-12-23  9:09   ` Bin Meng
2022-12-21 18:22 ` [PATCH 03/15] hw/riscv/sifive_u: " Daniel Henrique Barboza
2022-12-22 14:25   ` Philippe Mathieu-Daudé
2022-12-23  3:12   ` Alistair Francis
2022-12-23  9:10   ` Bin Meng
2022-12-21 18:22 ` [PATCH 04/15] hw/riscv/boot.c: make riscv_find_firmware() static Daniel Henrique Barboza
2022-12-22 14:26   ` Philippe Mathieu-Daudé
2022-12-23  3:13   ` Alistair Francis
2022-12-23  9:13   ` Bin Meng
2022-12-21 18:22 ` Daniel Henrique Barboza [this message]
2022-12-23  3:17   ` [PATCH 05/15] hw/riscv/boot.c: introduce riscv_default_firmware_name() Alistair Francis
2022-12-23  9:20   ` Bin Meng
2022-12-21 18:22 ` [PATCH 06/15] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Daniel Henrique Barboza
2022-12-22 14:27   ` Philippe Mathieu-Daudé
2022-12-23  3:19   ` Alistair Francis
2022-12-23 10:04   ` Bin Meng
2022-12-26 13:49     ` Bin Meng
2022-12-26 13:52       ` Daniel Henrique Barboza
2022-12-21 18:22 ` [PATCH 07/15] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Daniel Henrique Barboza
2022-12-23 10:15   ` Bin Meng
2022-12-21 18:22 ` [PATCH 08/15] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Daniel Henrique Barboza
2022-12-23 10:32   ` Bin Meng
2022-12-21 18:22 ` [PATCH 09/15] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Daniel Henrique Barboza
2022-12-22 14:27   ` Philippe Mathieu-Daudé
2022-12-23 10:47   ` Bin Meng
2022-12-21 18:22 ` [PATCH 10/15] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Daniel Henrique Barboza
2022-12-22 14:28   ` Philippe Mathieu-Daudé
2022-12-23 10:55   ` Bin Meng
2022-12-21 18:22 ` [PATCH 11/15] hw/riscv/boot.c: consolidate all kernel init " Daniel Henrique Barboza
2022-12-23 12:55   ` Bin Meng
2022-12-21 18:22 ` [PATCH 12/15] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
2022-12-22 14:29   ` Philippe Mathieu-Daudé
2022-12-23 12:56   ` Bin Meng
2022-12-21 18:22 ` [PATCH 13/15] hw/riscv/spike.c: simplify create_fdt() Daniel Henrique Barboza
2022-12-23 13:06   ` Bin Meng
2022-12-26 14:18     ` Daniel Henrique Barboza
2022-12-21 18:22 ` [PATCH 14/15] hw/riscv/virt.c: " Daniel Henrique Barboza
2022-12-21 18:23 ` [PATCH 15/15] hw/riscv/sifive_u: " Daniel Henrique Barboza

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