[PATCH 00/15] riscv: opensbi boot test and cleanups

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

Hi,

This series starts by adding a simple Avocado smoke test for RISC-V
machines that uses opensbi. The newly added test is then used to
validate the cleanups made along the way. With this test, running
'make check-avocado' after building all RISC-V targets will run the
test as follows:

 (06/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv64_virt: PASS (0.05 s)
 (07/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv64_spike: PASS (0.04 s)
 (08/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv64_sifive_u: PASS (0.06 s)
 (09/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_virt: PASS (0.05 s)
 (10/17) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_sifive_u: PASS (0.06 s)

Note that there are other tests that aren't being run with RISC-V yet.
We'll enable them as needed later on.

After adding this test, our goal is then to reduce boot code repetition
between RISC-V boards and consolidate all boot activities related with
the -kernel option in a single function, riscv_load_kernel().

Aside from allowing all boards to load initrd if -initrd is used (see
patch 11), no other functional changes were intended.

Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>

Daniel Henrique Barboza (15):
  tests/avocado: add RISC-V opensbi boot test
  hw/riscv/spike: use 'fdt' from MachineState
  hw/riscv/sifive_u: use 'fdt' from MachineState
  hw/riscv/boot.c: make riscv_find_firmware() static
  hw/riscv/boot.c: introduce riscv_default_firmware_name()
  hw/riscv/spike.c: load initrd right after riscv_load_kernel()
  hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
  hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
  hw/riscv/boot.c: use MachineState in riscv_load_initrd()
  hw/riscv/boot.c: use MachineState in riscv_load_kernel()
  hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
  hw/riscv/boot.c: make riscv_load_initrd() static
  hw/riscv/spike.c: simplify create_fdt()
  hw/riscv/virt.c: simplify create_fdt()
  hw/riscv/sifive_u: simplify create_fdt()

 hw/riscv/boot.c                | 137 ++++++++++++++++++++-------------
 hw/riscv/microchip_pfsoc.c     |  19 +----
 hw/riscv/opentitan.c           |   3 +-
 hw/riscv/sifive_e.c            |   3 +-
 hw/riscv/sifive_u.c            |  51 ++++--------
 hw/riscv/spike.c               |  53 ++++---------
 hw/riscv/virt.c                |  38 ++-------
 include/hw/riscv/boot.h        |   6 +-
 include/hw/riscv/sifive_u.h    |   3 -
 include/hw/riscv/spike.h       |   2 -
 tests/avocado/riscv_opensbi.py |  65 ++++++++++++++++
 11 files changed, 189 insertions(+), 191 deletions(-)
 create mode 100644 tests/avocado/riscv_opensbi.py

-- 
2.38.1