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From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 03/15] hw/riscv/sifive_u: use 'fdt' from MachineState
Date: Fri, 23 Dec 2022 13:12:20 +1000	[thread overview]
Message-ID: <CAKmqyKO_S=KO4mTGbPzCZ+o_AKAmsJvSPCCPfbsmbcSmofzM9w@mail.gmail.com> (raw)
In-Reply-To: <20221221182300.307900-4-dbarboza@ventanamicro.com>

On Thu, Dec 22, 2022 at 4:29 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> The MachineState object provides a 'fdt' pointer that is already being
> used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
> command.
>
> Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
> instead.
>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/sifive_u.c         | 15 ++++++---------
>  include/hw/riscv/sifive_u.h |  3 ---
>  2 files changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index b40a4767e2..9cf66957ab 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -98,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
>  {
>      MachineState *ms = MACHINE(qdev_get_machine());
>      void *fdt;
> -    int cpu;
> +    int cpu, fdt_size;
>      uint32_t *cells;
>      char *nodename;
>      uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
> @@ -112,14 +112,14 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
>      };
>
>      if (ms->dtb) {
> -        fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
> +        fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
>          if (!fdt) {
>              error_report("load_device_tree() failed");
>              exit(1);
>          }
>          goto update_bootargs;
>      } else {
> -        fdt = s->fdt = create_device_tree(&s->fdt_size);
> +        fdt = ms->fdt = create_device_tree(&fdt_size);
>          if (!fdt) {
>              error_report("create_device_tree() failed");
>              exit(1);
> @@ -615,9 +615,9 @@ static void sifive_u_machine_init(MachineState *machine)
>              hwaddr end = riscv_load_initrd(machine->initrd_filename,
>                                             machine->ram_size, kernel_entry,
>                                             &start);
> -            qemu_fdt_setprop_cell(s->fdt, "/chosen",
> +            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
>                                    "linux,initrd-start", start);
> -            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
> +            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
>                                    end);
>          }
>      } else {
> @@ -630,14 +630,11 @@ static void sifive_u_machine_init(MachineState *machine)
>
>      /* Compute the fdt load address in dram */
>      fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
> -                                   machine->ram_size, s->fdt);
> +                                   machine->ram_size, machine->fdt);
>      if (!riscv_is_32bit(&s->soc.u_cpus)) {
>          start_addr_hi32 = (uint64_t)start_addr >> 32;
>      }
>
> -    /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
> -    machine->fdt = s->fdt;
> -
>      /* reset vector */
>      uint32_t reset_vec[12] = {
>          s->msel,                       /* MSEL pin state */
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index e680d61ece..4a8828a30e 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -67,9 +67,6 @@ typedef struct SiFiveUState {
>      /*< public >*/
>      SiFiveUSoCState soc;
>
> -    void *fdt;
> -    int fdt_size;
> -
>      bool start_in_flash;
>      uint32_t msel;
>      uint32_t serial;
> --
> 2.38.1
>
>


  parent reply	other threads:[~2022-12-23  3:13 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-21 18:22 [PATCH 00/15] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
2022-12-21 18:22 ` [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test Daniel Henrique Barboza
2022-12-22 10:24   ` Bin Meng
2022-12-22 10:47     ` Daniel Henrique Barboza
2022-12-22 12:56       ` Bin Meng
2022-12-22 16:56         ` Anup Patel
2022-12-22 20:58           ` Daniel Henrique Barboza
2022-12-23  6:25           ` Bin Meng
2022-12-24  3:52             ` Bin Meng
2022-12-26 13:56               ` Bin Meng
2022-12-26 14:00                 ` Daniel Henrique Barboza
2022-12-27 18:02                 ` Daniel Henrique Barboza
2022-12-23  2:40   ` Alistair Francis
2022-12-27 23:04   ` Wainer dos Santos Moschetta
2022-12-21 18:22 ` [PATCH 02/15] hw/riscv/spike: use 'fdt' from MachineState Daniel Henrique Barboza
2022-12-22 14:25   ` Philippe Mathieu-Daudé
2022-12-22 16:43     ` Daniel Henrique Barboza
2022-12-23  3:10   ` Alistair Francis
2022-12-23  9:09   ` Bin Meng
2022-12-21 18:22 ` [PATCH 03/15] hw/riscv/sifive_u: " Daniel Henrique Barboza
2022-12-22 14:25   ` Philippe Mathieu-Daudé
2022-12-23  3:12   ` Alistair Francis [this message]
2022-12-23  9:10   ` Bin Meng
2022-12-21 18:22 ` [PATCH 04/15] hw/riscv/boot.c: make riscv_find_firmware() static Daniel Henrique Barboza
2022-12-22 14:26   ` Philippe Mathieu-Daudé
2022-12-23  3:13   ` Alistair Francis
2022-12-23  9:13   ` Bin Meng
2022-12-21 18:22 ` [PATCH 05/15] hw/riscv/boot.c: introduce riscv_default_firmware_name() Daniel Henrique Barboza
2022-12-23  3:17   ` Alistair Francis
2022-12-23  9:20   ` Bin Meng
2022-12-21 18:22 ` [PATCH 06/15] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Daniel Henrique Barboza
2022-12-22 14:27   ` Philippe Mathieu-Daudé
2022-12-23  3:19   ` Alistair Francis
2022-12-23 10:04   ` Bin Meng
2022-12-26 13:49     ` Bin Meng
2022-12-26 13:52       ` Daniel Henrique Barboza
2022-12-21 18:22 ` [PATCH 07/15] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Daniel Henrique Barboza
2022-12-23 10:15   ` Bin Meng
2022-12-21 18:22 ` [PATCH 08/15] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Daniel Henrique Barboza
2022-12-23 10:32   ` Bin Meng
2022-12-21 18:22 ` [PATCH 09/15] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Daniel Henrique Barboza
2022-12-22 14:27   ` Philippe Mathieu-Daudé
2022-12-23 10:47   ` Bin Meng
2022-12-21 18:22 ` [PATCH 10/15] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Daniel Henrique Barboza
2022-12-22 14:28   ` Philippe Mathieu-Daudé
2022-12-23 10:55   ` Bin Meng
2022-12-21 18:22 ` [PATCH 11/15] hw/riscv/boot.c: consolidate all kernel init " Daniel Henrique Barboza
2022-12-23 12:55   ` Bin Meng
2022-12-21 18:22 ` [PATCH 12/15] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
2022-12-22 14:29   ` Philippe Mathieu-Daudé
2022-12-23 12:56   ` Bin Meng
2022-12-21 18:22 ` [PATCH 13/15] hw/riscv/spike.c: simplify create_fdt() Daniel Henrique Barboza
2022-12-23 13:06   ` Bin Meng
2022-12-26 14:18     ` Daniel Henrique Barboza
2022-12-21 18:22 ` [PATCH 14/15] hw/riscv/virt.c: " Daniel Henrique Barboza
2022-12-21 18:23 ` [PATCH 15/15] hw/riscv/sifive_u: " Daniel Henrique Barboza

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