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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@collabora.com>
To: mturquette@baylibre.com
Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	angelogioacchino.delregno@collabora.com, wenst@chromium.org,
	johnson.wang@mediatek.com, miles.chen@mediatek.com,
	fparent@baylibre.com, chun-jie.chen@mediatek.com,
	sam.shih@mediatek.com, y.oudjana@protonmail.com,
	nfraprado@collabora.com, rex-bc.chen@mediatek.com,
	ryder.lee@kernel.org, daniel@makrotopia.org,
	jose.exposito89@gmail.com, yangyingliang@huawei.com,
	pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com,
	ikjn@chromium.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
	kernel@collabora.com
Subject: [PATCH v2 14/23] clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs
Date: Fri, 23 Dec 2022 10:42:50 +0100	[thread overview]
Message-ID: <20221223094259.87373-15-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com>

This driver is registered early in clk_mt8192_top_init_early() and
then again in clk_mt8192_top_probe(): the difference between the
two is that the early one is probed with CLK_OF_DECLARE_DRIVER and
the latter is regularly probed as a platform_driver.

Knowing that it is not necessary for this platform to register the
TOP_CSW_F26M_D2 clock that early, move it to top_divs and register
it with the others during platform_driver probe for topckgen;

While at it, since the only reason why the early probe existed was
to register that clock, remove that entirely - leaving this driver
to use only platform_driver.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8192.c | 39 ++++++-------------------------
 1 file changed, 7 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 9a9d51bfb84d..ec9dc7fe848e 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -26,10 +26,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
 	FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
 };
 
-static const struct mtk_fixed_factor top_early_divs[] = {
-	FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
-};
-
 static const struct mtk_fixed_factor top_divs[] = {
 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
@@ -95,6 +91,7 @@ static const struct mtk_fixed_factor top_divs[] = {
 	FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
 	FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
 	FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
+	FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
 	FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0),
@@ -1047,27 +1044,6 @@ static const struct mtk_pll_data plls[] = {
 	      0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
 };
 
-static struct clk_hw_onecell_data *top_clk_data;
-
-static void clk_mt8192_top_init_early(struct device_node *node)
-{
-	int i;
-
-	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
-	if (!top_clk_data)
-		return;
-
-	for (i = 0; i < CLK_TOP_NR_CLK; i++)
-		top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
-
-	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
-
-	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
-}
-
-CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen",
-		      clk_mt8192_top_init_early);
-
 /* Register mux notifier for MFG mux */
 static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
 {
@@ -1093,6 +1069,7 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
 static int clk_mt8192_top_probe(struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
+	struct clk_hw_onecell_data *top_clk_data;
 	int r;
 	void __iomem *base;
 
@@ -1100,17 +1077,17 @@ static int clk_mt8192_top_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
+	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+	if (!top_clk_data)
+		return;
+
 	r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
 	if (r)
 		return r;
 
-	r = mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
-	if (r)
-		goto unregister_fixed_clks;
-
 	r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
 	if (r)
-		goto unregister_early_factors;
+		goto unregister_fixed_clks;
 
 	r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
 				   &mt8192_clk_lock, top_clk_data, &pdev->dev);
@@ -1150,8 +1127,6 @@ static int clk_mt8192_top_probe(struct platform_device *pdev)
 	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
 unregister_factors:
 	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
-unregister_early_factors:
-	mtk_clk_unregister_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
 unregister_fixed_clks:
 	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 				      top_clk_data);
-- 
2.39.0


WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: mturquette@baylibre.com
Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	angelogioacchino.delregno@collabora.com, wenst@chromium.org,
	johnson.wang@mediatek.com, miles.chen@mediatek.com,
	fparent@baylibre.com, chun-jie.chen@mediatek.com,
	sam.shih@mediatek.com, y.oudjana@protonmail.com,
	nfraprado@collabora.com, rex-bc.chen@mediatek.com,
	ryder.lee@kernel.org, daniel@makrotopia.org,
	jose.exposito89@gmail.com, yangyingliang@huawei.com,
	pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com,
	ikjn@chromium.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
	kernel@collabora.com
Subject: [PATCH v2 14/23] clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs
Date: Fri, 23 Dec 2022 10:42:50 +0100	[thread overview]
Message-ID: <20221223094259.87373-15-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com>

This driver is registered early in clk_mt8192_top_init_early() and
then again in clk_mt8192_top_probe(): the difference between the
two is that the early one is probed with CLK_OF_DECLARE_DRIVER and
the latter is regularly probed as a platform_driver.

Knowing that it is not necessary for this platform to register the
TOP_CSW_F26M_D2 clock that early, move it to top_divs and register
it with the others during platform_driver probe for topckgen;

While at it, since the only reason why the early probe existed was
to register that clock, remove that entirely - leaving this driver
to use only platform_driver.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8192.c | 39 ++++++-------------------------
 1 file changed, 7 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 9a9d51bfb84d..ec9dc7fe848e 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -26,10 +26,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
 	FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
 };
 
-static const struct mtk_fixed_factor top_early_divs[] = {
-	FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
-};
-
 static const struct mtk_fixed_factor top_divs[] = {
 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
@@ -95,6 +91,7 @@ static const struct mtk_fixed_factor top_divs[] = {
 	FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
 	FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
 	FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
+	FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
 	FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0),
@@ -1047,27 +1044,6 @@ static const struct mtk_pll_data plls[] = {
 	      0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
 };
 
-static struct clk_hw_onecell_data *top_clk_data;
-
-static void clk_mt8192_top_init_early(struct device_node *node)
-{
-	int i;
-
-	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
-	if (!top_clk_data)
-		return;
-
-	for (i = 0; i < CLK_TOP_NR_CLK; i++)
-		top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
-
-	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
-
-	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
-}
-
-CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen",
-		      clk_mt8192_top_init_early);
-
 /* Register mux notifier for MFG mux */
 static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
 {
@@ -1093,6 +1069,7 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
 static int clk_mt8192_top_probe(struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
+	struct clk_hw_onecell_data *top_clk_data;
 	int r;
 	void __iomem *base;
 
@@ -1100,17 +1077,17 @@ static int clk_mt8192_top_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
+	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+	if (!top_clk_data)
+		return;
+
 	r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
 	if (r)
 		return r;
 
-	r = mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
-	if (r)
-		goto unregister_fixed_clks;
-
 	r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
 	if (r)
-		goto unregister_early_factors;
+		goto unregister_fixed_clks;
 
 	r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
 				   &mt8192_clk_lock, top_clk_data, &pdev->dev);
@@ -1150,8 +1127,6 @@ static int clk_mt8192_top_probe(struct platform_device *pdev)
 	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
 unregister_factors:
 	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
-unregister_early_factors:
-	mtk_clk_unregister_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
 unregister_fixed_clks:
 	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 				      top_clk_data);
-- 
2.39.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-12-23  9:45 UTC|newest]

Thread overview: 154+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-23  9:42 [PATCH v2 00/23] MediaTek clocks cleanups and improvements AngeloGioacchino Del Regno
2022-12-23  9:42 ` AngeloGioacchino Del Regno
2022-12-23  9:42 ` [PATCH v2 01/23] clk: mediatek: mt8192: Correctly unregister and free clocks on failure AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-26  6:55   ` Chen-Yu Tsai
2022-12-26  6:55     ` Chen-Yu Tsai
2023-01-04 10:55   ` Markus Schneider-Pargmann
2023-01-04 10:55     ` Markus Schneider-Pargmann
2022-12-23  9:42 ` [PATCH v2 02/23] clk: mediatek: mt8192: Propagate struct device for gate clocks AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-26  6:56   ` Chen-Yu Tsai
2022-12-26  6:56     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 03/23] clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates() AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-26  7:05   ` Chen-Yu Tsai
2022-12-26  7:05     ` Chen-Yu Tsai
2023-01-04 11:21   ` Markus Schneider-Pargmann
2023-01-04 11:21     ` Markus Schneider-Pargmann
2023-01-10 11:05     ` AngeloGioacchino Del Regno
2023-01-10 11:05       ` AngeloGioacchino Del Regno
2022-12-23  9:42 ` [PATCH v2 04/23] clk: mediatek: cpumux: Propagate struct device where possible AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-26  7:07   ` Chen-Yu Tsai
2022-12-26  7:07     ` Chen-Yu Tsai
2023-01-06 17:00     ` Markus Schneider-Pargmann
2023-01-06 17:00       ` Markus Schneider-Pargmann
2022-12-23  9:42 ` [PATCH v2 05/23] clk: mediatek: clk-mtk: Propagate struct device for composites AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  4:37   ` Chen-Yu Tsai
2022-12-30  4:37     ` Chen-Yu Tsai
2023-01-06 17:09   ` Markus Schneider-Pargmann
2023-01-06 17:09     ` Markus Schneider-Pargmann
2022-12-23  9:42 ` [PATCH v2 06/23] clk: mediatek: clk-mux: Propagate struct device for mtk-mux AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  4:43   ` Chen-Yu Tsai
2022-12-30  4:43     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 07/23] clk: mediatek: clk-mtk: Add dummy clock ops AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-28  7:24   ` Miles Chen
2022-12-28  7:24     ` Miles Chen
2022-12-30  5:19   ` Chen-Yu Tsai
2022-12-30  5:19     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 08/23] clk: mediatek: mt8173: Migrate to platform driver and common probe AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  8:22   ` Chen-Yu Tsai
2022-12-30  8:22     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 09/23] clk: mediatek: mt8173: Remove mtk_clk_enable_critical() AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  4:58   ` Chen-Yu Tsai
2022-12-30  4:58     ` Chen-Yu Tsai
2023-01-10 12:32     ` AngeloGioacchino Del Regno
2023-01-10 12:32       ` AngeloGioacchino Del Regno
2023-01-11  2:27       ` Chen-Yu Tsai
2023-01-11  2:27         ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 10/23] clk: mediatek: mt8173: Break down clock drivers and allow module build AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-24  1:47   ` kernel test robot
2022-12-23  9:42 ` [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() where possible AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-28  7:50   ` Miles Chen
2022-12-28  7:50     ` Miles Chen
2022-12-30  5:12   ` Chen-Yu Tsai
2022-12-30  5:12     ` Chen-Yu Tsai
2023-01-10 13:31     ` AngeloGioacchino Del Regno
2023-01-10 13:31       ` AngeloGioacchino Del Regno
2023-01-11  2:47       ` Chen-Yu Tsai
2023-01-11  2:47         ` Chen-Yu Tsai
2023-01-11  8:56         ` [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() Miles Chen
2023-01-11  8:56           ` Miles Chen
2023-01-11 10:36           ` AngeloGioacchino Del Regno
2023-01-11 10:36             ` AngeloGioacchino Del Regno
2022-12-23  9:42 ` [PATCH v2 12/23] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-27 16:22   ` Miles Chen
2022-12-27 16:22     ` Miles Chen
2022-12-30  7:14   ` Chen-Yu Tsai
2022-12-30  7:14     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 13/23] clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-28  7:54   ` Miles Chen
2022-12-28  7:54     ` Miles Chen
2022-12-30  7:15   ` Chen-Yu Tsai
2022-12-30  7:15     ` Chen-Yu Tsai
2022-12-23  9:42 ` AngeloGioacchino Del Regno [this message]
2022-12-23  9:42   ` [PATCH v2 14/23] clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs AngeloGioacchino Del Regno
2022-12-28  7:58   ` Miles Chen
2022-12-28  7:58     ` Miles Chen
2022-12-30  5:17   ` Chen-Yu Tsai
2022-12-30  5:17     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 15/23] clk: mediatek: mt8192: Join top_adj_divs and top_muxes AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-28  8:31   ` Miles Chen
2022-12-28  8:31     ` Miles Chen
2022-12-30  8:09     ` Chen-Yu Tsai
2022-12-30  8:09       ` Chen-Yu Tsai
2022-12-30  8:06   ` Chen-Yu Tsai
2022-12-30  8:06     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 16/23] clk: mediatek: mt8186: Join top_adj_div " AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  8:17   ` Chen-Yu Tsai
2022-12-30  8:17     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 17/23] clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  8:19   ` Chen-Yu Tsai
2022-12-30  8:19     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 18/23] clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-29  8:21   ` Miles Chen
2022-12-29  8:21     ` Miles Chen
2022-12-30  8:12     ` Chen-Yu Tsai
2022-12-30  8:12       ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 19/23] clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  8:18   ` Chen-Yu Tsai
2022-12-30  8:18     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 20/23] clk: mediatek: clk-mt8186-topckgen: Migrate " AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  5:55   ` Miles Chen
2022-12-30  5:55     ` Miles Chen
2022-12-30  8:15   ` Chen-Yu Tsai
2022-12-30  8:15     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 21/23] clk: mediatek: clk-mt6795-topckgen: " AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  5:56   ` Miles Chen
2022-12-30  5:56     ` Miles Chen
2022-12-30  8:13   ` Chen-Yu Tsai
2022-12-30  8:13     ` Chen-Yu Tsai
2022-12-23  9:42 ` [PATCH v2 22/23] clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-30  5:23   ` Chen-Yu Tsai
2022-12-30  5:23     ` Chen-Yu Tsai
2022-12-30  6:04   ` Miles Chen
2022-12-30  6:04     ` Miles Chen
2022-12-23  9:42 ` [PATCH v2 23/23] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-23  9:42   ` AngeloGioacchino Del Regno
2022-12-27 16:18   ` [PATCH v2 12/23] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() Miles Chen
2022-12-27 16:18     ` Miles Chen
2022-12-27 16:26     ` Miles Chen
2022-12-27 16:26       ` Miles Chen
2022-12-30  6:05   ` [PATCH v2 23/23] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() Miles Chen
2022-12-30  6:05     ` Miles Chen
2022-12-30  8:14   ` Chen-Yu Tsai
2022-12-30  8:14     ` Chen-Yu Tsai
2022-12-30  6:13 ` [PATCH v2 00/23] MediaTek clocks cleanups and improvements Miles Chen
2022-12-30  6:13   ` Miles Chen
2022-12-30  6:42   ` Chen-Yu Tsai
2022-12-30  6:42     ` Chen-Yu Tsai
2022-12-30  7:19     ` Miles Chen
2022-12-30  7:19       ` Miles Chen
2023-01-03  9:36 ` Chen-Yu Tsai
2023-01-03  9:36   ` Chen-Yu Tsai
2022-12-23 20:33 [PATCH v2 10/23] clk: mediatek: mt8173: Break down clock drivers and allow module build kernel test robot
2022-12-24  7:13 ` Dan Carpenter
2022-12-24  7:13 ` Dan Carpenter

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