From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Guo Ren <ren_guo@c-sky.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko@sntech.de>, Atish Patra <atishp@rivosinc.com>, Anup Patel <apatel@ventanamicro.com>, Guo Ren <guoren@kernel.org>, Mayuresh Chitale <mchitale@ventanamicro.com>, Conor Dooley <conor.dooley@microchip.com>, Dao Lu <daolu@rivosinc.com>, Jisheng Zhang <jszhang@kernel.org>, Andrew Jones <ajones@ventanamicro.com>, Vincent Chen <vincent.chen@sifive.com>, Tsukasa OI <research_trasio@irq.a4lg.com> Subject: [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Date: Wed, 25 Jan 2023 14:20:39 +0000 [thread overview] Message-ID: <20230125142056.18356-3-andy.chiu@sifive.com> (raw) In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com> From: Guo Ren <ren_guo@c-sky.com> Add V-extension into riscv_isa_ext_keys array and detect it with isa string parsing. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Suggested-by: Vineet Gupta <vineetg@rivosinc.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/include/asm/vector.h | 26 ++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 arch/riscv/include/asm/vector.h diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 57439da71c77..f413db6118e5 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -35,6 +35,7 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_m ('m' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_v ('v' - 'a') /* * Increse this to higher value as kernel support more ISA extensions. @@ -73,6 +74,7 @@ static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); enum riscv_isa_ext_key { RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ RISCV_ISA_EXT_KEY_SVINVAL, + RISCV_ISA_EXT_KEY_VECTOR, /* For 'V' */ RISCV_ISA_EXT_KEY_ZIHINTPAUSE, RISCV_ISA_EXT_KEY_MAX, }; @@ -95,6 +97,8 @@ static __always_inline int riscv_isa_ext2key(int num) return RISCV_ISA_EXT_KEY_FPU; case RISCV_ISA_EXT_SVINVAL: return RISCV_ISA_EXT_KEY_SVINVAL; + case RISCV_ISA_EXT_v: + return RISCV_ISA_EXT_KEY_VECTOR; case RISCV_ISA_EXT_ZIHINTPAUSE: return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; default: diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h new file mode 100644 index 000000000000..917c8867e702 --- /dev/null +++ b/arch/riscv/include/asm/vector.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2020 SiFive + */ + +#ifndef __ASM_RISCV_VECTOR_H +#define __ASM_RISCV_VECTOR_H + +#include <linux/types.h> + +#ifdef CONFIG_RISCV_ISA_V + +#include <asm/hwcap.h> + +static __always_inline bool has_vector(void) +{ + return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]); +} + +#else /* ! CONFIG_RISCV_ISA_V */ + +static __always_inline bool has_vector(void) { return false; } + +#endif /* CONFIG_RISCV_ISA_V */ + +#endif /* ! __ASM_RISCV_VECTOR_H */ diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..c52bb7bbbabe 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,5 +21,6 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dde0e91d7668..c433899542ff 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,7 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; elf_hwcap = 0; @@ -256,6 +257,17 @@ void __init riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { +#ifndef CONFIG_RISCV_ISA_V + /* + * ISA string in device tree might have 'v' flag, but + * CONFIG_RISCV_ISA_V is disabled in kernel. + * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. + */ + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; +#endif + } + memset(print_str, 0, sizeof(print_str)); for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Guo Ren <ren_guo@c-sky.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Heiko Stuebner <heiko@sntech.de>, Atish Patra <atishp@rivosinc.com>, Anup Patel <apatel@ventanamicro.com>, Guo Ren <guoren@kernel.org>, Mayuresh Chitale <mchitale@ventanamicro.com>, Conor Dooley <conor.dooley@microchip.com>, Dao Lu <daolu@rivosinc.com>, Jisheng Zhang <jszhang@kernel.org>, Andrew Jones <ajones@ventanamicro.com>, Vincent Chen <vincent.chen@sifive.com>, Tsukasa OI <research_trasio@irq.a4lg.com> Subject: [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Date: Wed, 25 Jan 2023 14:20:39 +0000 [thread overview] Message-ID: <20230125142056.18356-3-andy.chiu@sifive.com> (raw) In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com> From: Guo Ren <ren_guo@c-sky.com> Add V-extension into riscv_isa_ext_keys array and detect it with isa string parsing. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Suggested-by: Vineet Gupta <vineetg@rivosinc.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/include/asm/vector.h | 26 ++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 arch/riscv/include/asm/vector.h diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 57439da71c77..f413db6118e5 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -35,6 +35,7 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_m ('m' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_v ('v' - 'a') /* * Increse this to higher value as kernel support more ISA extensions. @@ -73,6 +74,7 @@ static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); enum riscv_isa_ext_key { RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ RISCV_ISA_EXT_KEY_SVINVAL, + RISCV_ISA_EXT_KEY_VECTOR, /* For 'V' */ RISCV_ISA_EXT_KEY_ZIHINTPAUSE, RISCV_ISA_EXT_KEY_MAX, }; @@ -95,6 +97,8 @@ static __always_inline int riscv_isa_ext2key(int num) return RISCV_ISA_EXT_KEY_FPU; case RISCV_ISA_EXT_SVINVAL: return RISCV_ISA_EXT_KEY_SVINVAL; + case RISCV_ISA_EXT_v: + return RISCV_ISA_EXT_KEY_VECTOR; case RISCV_ISA_EXT_ZIHINTPAUSE: return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; default: diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h new file mode 100644 index 000000000000..917c8867e702 --- /dev/null +++ b/arch/riscv/include/asm/vector.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2020 SiFive + */ + +#ifndef __ASM_RISCV_VECTOR_H +#define __ASM_RISCV_VECTOR_H + +#include <linux/types.h> + +#ifdef CONFIG_RISCV_ISA_V + +#include <asm/hwcap.h> + +static __always_inline bool has_vector(void) +{ + return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]); +} + +#else /* ! CONFIG_RISCV_ISA_V */ + +static __always_inline bool has_vector(void) { return false; } + +#endif /* CONFIG_RISCV_ISA_V */ + +#endif /* ! __ASM_RISCV_VECTOR_H */ diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..c52bb7bbbabe 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,5 +21,6 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index dde0e91d7668..c433899542ff 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,7 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; elf_hwcap = 0; @@ -256,6 +257,17 @@ void __init riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { +#ifndef CONFIG_RISCV_ISA_V + /* + * ISA string in device tree might have 'v' flag, but + * CONFIG_RISCV_ISA_V is disabled in kernel. + * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. + */ + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; +#endif + } + memset(print_str, 0, sizeof(print_str)); for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-25 14:21 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:15 ` Conor Dooley 2023-01-25 21:15 ` Conor Dooley 2023-01-25 14:20 ` Andy Chiu [this message] 2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-01-25 21:33 ` Conor Dooley 2023-01-25 21:33 ` Conor Dooley 2023-01-28 7:09 ` Guo Ren 2023-01-28 7:09 ` Guo Ren 2023-01-28 10:28 ` Conor Dooley 2023-01-28 10:28 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 22:16 ` Conor Dooley 2023-01-25 22:16 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 22:18 ` Conor Dooley 2023-01-25 22:18 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:51 ` Conor Dooley 2023-01-25 21:51 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:06 ` Conor Dooley 2023-01-26 21:06 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:24 ` Conor Dooley 2023-01-26 21:24 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:32 ` Conor Dooley 2023-01-26 21:32 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:44 ` Conor Dooley 2023-01-26 21:44 ` Conor Dooley 2023-01-31 2:55 ` Vineet Gupta 2023-01-31 2:55 ` Vineet Gupta 2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:11 ` Conor Dooley 2023-01-26 23:11 ` Conor Dooley 2023-02-06 12:00 ` Andy Chiu 2023-02-06 12:00 ` Andy Chiu 2023-02-06 13:40 ` Conor Dooley 2023-02-06 13:40 ` Conor Dooley 2023-02-10 12:00 ` Andy Chiu 2023-02-10 12:00 ` Andy Chiu 2023-02-07 14:36 ` Björn Töpel 2023-02-07 14:36 ` Björn Töpel 2023-02-13 22:54 ` Vineet Gupta 2023-02-13 22:54 ` Vineet Gupta 2023-02-14 6:43 ` Björn Töpel 2023-02-14 6:43 ` Björn Töpel 2023-02-14 15:36 ` Andy Chiu 2023-02-14 15:36 ` Andy Chiu 2023-02-14 16:50 ` Björn Töpel 2023-02-14 16:50 ` Björn Töpel 2023-02-14 17:24 ` Vineet Gupta 2023-02-14 17:24 ` Vineet Gupta 2023-02-15 7:14 ` Björn Töpel 2023-02-15 7:14 ` Björn Töpel 2023-02-15 14:39 ` Andy Chiu 2023-02-15 14:39 ` Andy Chiu 2023-02-07 21:18 ` Vineet Gupta 2023-02-07 21:18 ` Vineet Gupta 2023-02-08 9:20 ` Björn Töpel 2023-02-08 9:20 ` Björn Töpel 2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:19 ` Conor Dooley 2023-01-26 23:19 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:31 ` Conor Dooley 2023-01-27 20:31 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:43 ` Conor Dooley 2023-01-27 20:43 ` Conor Dooley 2023-01-30 9:58 ` Andy Chiu 2023-01-30 9:58 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 11:28 ` Anup Patel 2023-01-27 11:28 ` Anup Patel 2023-01-30 8:18 ` Andy Chiu 2023-01-30 8:18 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 22:24 ` Conor Dooley 2023-01-25 22:24 ` Conor Dooley 2023-01-30 6:38 ` Andy Chiu 2023-01-30 6:38 ` Andy Chiu 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 7:46 ` Andy Chiu 2023-01-30 7:46 ` Andy Chiu 2023-01-30 8:13 ` Conor Dooley 2023-01-30 8:13 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley
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