From: Vineet Gupta <vineetg@rivosinc.com>
To: Andy Chiu <andy.chiu@sifive.com>, Conor Dooley <conor@kernel.org>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
greentime.hu@sifive.com, guoren@linux.alibaba.com,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH -next v13 19/19] riscv: Enable Vector code to be built
Date: Mon, 30 Jan 2023 10:38:24 -0800 [thread overview]
Message-ID: <c5470393-af09-e86b-b388-d6b830451e8f@rivosinc.com> (raw)
In-Reply-To: <CABgGipWndcnUxUvWtyxyETtLaJT42VaZoiat7uDmnOjREEt9tg@mail.gmail.com>
On 1/29/23 22:38, Andy Chiu wrote:
>>> + default n
>> I forget, but is the reason for this being default n, when the others
>> are default y a conscious choice?
> Yes, I think it could be y if V is allocated in the first-use trap, as
> far as I'm concerned. Hey Vineet, do you have any comments about that?
Yes I think this can be enabled by default now that everything is
allocated on demand.
FWIW thread_struct would have 5 word overhead due to struct
__riscv_v_state but nothing I would worry about too much.
-Vineet
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WARNING: multiple messages have this Message-ID (diff)
From: Vineet Gupta <vineetg@rivosinc.com>
To: Andy Chiu <andy.chiu@sifive.com>, Conor Dooley <conor@kernel.org>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
greentime.hu@sifive.com, guoren@linux.alibaba.com,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH -next v13 19/19] riscv: Enable Vector code to be built
Date: Mon, 30 Jan 2023 10:38:24 -0800 [thread overview]
Message-ID: <c5470393-af09-e86b-b388-d6b830451e8f@rivosinc.com> (raw)
In-Reply-To: <CABgGipWndcnUxUvWtyxyETtLaJT42VaZoiat7uDmnOjREEt9tg@mail.gmail.com>
On 1/29/23 22:38, Andy Chiu wrote:
>>> + default n
>> I forget, but is the reason for this being default n, when the others
>> are default y a conscious choice?
> Yes, I think it could be y if V is allocated in the first-use trap, as
> far as I'm concerned. Hey Vineet, do you have any comments about that?
Yes I think this can be enabled by default now that everything is
allocated on demand.
FWIW thread_struct would have 5 word overhead due to struct
__riscv_v_state but nothing I would worry about too much.
-Vineet
next prev parent reply other threads:[~2023-01-30 18:38 UTC|newest]
Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 21:15 ` Conor Dooley
2023-01-25 21:15 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 21:33 ` Conor Dooley
2023-01-25 21:33 ` Conor Dooley
2023-01-28 7:09 ` Guo Ren
2023-01-28 7:09 ` Guo Ren
2023-01-28 10:28 ` Conor Dooley
2023-01-28 10:28 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 22:16 ` Conor Dooley
2023-01-25 22:16 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 21:54 ` Conor Dooley
2023-01-25 21:54 ` Conor Dooley
2023-01-25 21:57 ` Vineet Gupta
2023-01-25 21:57 ` Vineet Gupta
2023-01-25 22:18 ` Conor Dooley
2023-01-25 22:18 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 21:51 ` Conor Dooley
2023-01-25 21:51 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-26 21:06 ` Conor Dooley
2023-01-26 21:06 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-26 21:24 ` Conor Dooley
2023-01-26 21:24 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-26 21:32 ` Conor Dooley
2023-01-26 21:32 ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-26 21:44 ` Conor Dooley
2023-01-26 21:44 ` Conor Dooley
2023-01-31 2:55 ` Vineet Gupta
2023-01-31 2:55 ` Vineet Gupta
2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-26 23:11 ` Conor Dooley
2023-01-26 23:11 ` Conor Dooley
2023-02-06 12:00 ` Andy Chiu
2023-02-06 12:00 ` Andy Chiu
2023-02-06 13:40 ` Conor Dooley
2023-02-06 13:40 ` Conor Dooley
2023-02-10 12:00 ` Andy Chiu
2023-02-10 12:00 ` Andy Chiu
2023-02-07 14:36 ` Björn Töpel
2023-02-07 14:36 ` Björn Töpel
2023-02-13 22:54 ` Vineet Gupta
2023-02-13 22:54 ` Vineet Gupta
2023-02-14 6:43 ` Björn Töpel
2023-02-14 6:43 ` Björn Töpel
2023-02-14 15:36 ` Andy Chiu
2023-02-14 15:36 ` Andy Chiu
2023-02-14 16:50 ` Björn Töpel
2023-02-14 16:50 ` Björn Töpel
2023-02-14 17:24 ` Vineet Gupta
2023-02-14 17:24 ` Vineet Gupta
2023-02-15 7:14 ` Björn Töpel
2023-02-15 7:14 ` Björn Töpel
2023-02-15 14:39 ` Andy Chiu
2023-02-15 14:39 ` Andy Chiu
2023-02-07 21:18 ` Vineet Gupta
2023-02-07 21:18 ` Vineet Gupta
2023-02-08 9:20 ` Björn Töpel
2023-02-08 9:20 ` Björn Töpel
2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-26 23:19 ` Conor Dooley
2023-01-26 23:19 ` Conor Dooley
2023-01-31 12:34 ` Andy Chiu
2023-01-31 12:34 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-27 20:31 ` Conor Dooley
2023-01-27 20:31 ` Conor Dooley
2023-01-31 12:34 ` Andy Chiu
2023-01-31 12:34 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-27 20:43 ` Conor Dooley
2023-01-27 20:43 ` Conor Dooley
2023-01-30 9:58 ` Andy Chiu
2023-01-30 9:58 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-27 11:28 ` Anup Patel
2023-01-27 11:28 ` Anup Patel
2023-01-30 8:18 ` Andy Chiu
2023-01-30 8:18 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 21:04 ` Conor Dooley
2023-01-25 21:04 ` Conor Dooley
2023-01-25 21:38 ` Jessica Clarke
2023-01-25 21:38 ` Jessica Clarke
2023-01-25 22:24 ` Conor Dooley
2023-01-25 22:24 ` Conor Dooley
2023-01-30 6:38 ` Andy Chiu
2023-01-30 6:38 ` Andy Chiu
2023-01-30 18:38 ` Vineet Gupta [this message]
2023-01-30 18:38 ` Vineet Gupta
2023-01-30 7:46 ` Andy Chiu
2023-01-30 7:46 ` Andy Chiu
2023-01-30 8:13 ` Conor Dooley
2023-01-30 8:13 ` Conor Dooley
2023-02-08 18:19 ` Conor Dooley
2023-02-08 18:19 ` Conor Dooley
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