From: Conor Dooley <conor@kernel.org> To: Andy Chiu <andy.chiu@sifive.com> Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: Re: [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Date: Fri, 27 Jan 2023 20:43:55 +0000 [thread overview] Message-ID: <Y9Q3i2z8uh1Bttzw@spud> (raw) In-Reply-To: <20230125142056.18356-17-andy.chiu@sifive.com> [-- Attachment #1: Type: text/plain, Size: 2069 bytes --] On Wed, Jan 25, 2023 at 02:20:53PM +0000, Andy Chiu wrote: > riscv: Add V extension to KVM ISA I figure this should probably be "riscv: kvm:" or some variant with more capital letters. > From: Vincent Chen <vincent.chen@sifive.com> > > Add V extension to KVM isa extension list to enable supporting of V > extension on VCPUs. > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/vcpu.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index 92af6f3f057c..e7c9183ad4af 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -100,6 +100,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_H, > KVM_RISCV_ISA_EXT_I, > KVM_RISCV_ISA_EXT_M, > + KVM_RISCV_ISA_EXT_V, > KVM_RISCV_ISA_EXT_SVPBMT, > KVM_RISCV_ISA_EXT_SSTC, > KVM_RISCV_ISA_EXT_SVINVAL, Ehh, this UAPI so, AFAIU, you cannot add this in the middle of the enum and new entries must go at the bottom. Quoting Drew: "we can't touch enum KVM_RISCV_ISA_EXT_ID as that's UAPI. All new extensions must be added at the bottom. We originally also had to keep kvm_isa_ext_arr[] in that order, but commit 1b5cbb8733f9 ("RISC-V: KVM: Make ISA ext mappings explicit") allows us to list its elements in any order." > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 7c08567097f0..b060d26ab783 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -57,6 +57,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > [KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h, > [KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i, > [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, > + [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, > > KVM_ISA_EXT_ARR(SSTC), > KVM_ISA_EXT_ARR(SVINVAL), This one here is fine however. Thanks, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: Andy Chiu <andy.chiu@sifive.com> Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: Re: [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Date: Fri, 27 Jan 2023 20:43:55 +0000 [thread overview] Message-ID: <Y9Q3i2z8uh1Bttzw@spud> (raw) In-Reply-To: <20230125142056.18356-17-andy.chiu@sifive.com> [-- Attachment #1.1: Type: text/plain, Size: 2069 bytes --] On Wed, Jan 25, 2023 at 02:20:53PM +0000, Andy Chiu wrote: > riscv: Add V extension to KVM ISA I figure this should probably be "riscv: kvm:" or some variant with more capital letters. > From: Vincent Chen <vincent.chen@sifive.com> > > Add V extension to KVM isa extension list to enable supporting of V > extension on VCPUs. > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/vcpu.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index 92af6f3f057c..e7c9183ad4af 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -100,6 +100,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_H, > KVM_RISCV_ISA_EXT_I, > KVM_RISCV_ISA_EXT_M, > + KVM_RISCV_ISA_EXT_V, > KVM_RISCV_ISA_EXT_SVPBMT, > KVM_RISCV_ISA_EXT_SSTC, > KVM_RISCV_ISA_EXT_SVINVAL, Ehh, this UAPI so, AFAIU, you cannot add this in the middle of the enum and new entries must go at the bottom. Quoting Drew: "we can't touch enum KVM_RISCV_ISA_EXT_ID as that's UAPI. All new extensions must be added at the bottom. We originally also had to keep kvm_isa_ext_arr[] in that order, but commit 1b5cbb8733f9 ("RISC-V: KVM: Make ISA ext mappings explicit") allows us to list its elements in any order." > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 7c08567097f0..b060d26ab783 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -57,6 +57,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > [KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h, > [KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i, > [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, > + [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, > > KVM_ISA_EXT_ARR(SSTC), > KVM_ISA_EXT_ARR(SVINVAL), This one here is fine however. Thanks, Conor. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-27 20:44 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:15 ` Conor Dooley 2023-01-25 21:15 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:33 ` Conor Dooley 2023-01-25 21:33 ` Conor Dooley 2023-01-28 7:09 ` Guo Ren 2023-01-28 7:09 ` Guo Ren 2023-01-28 10:28 ` Conor Dooley 2023-01-28 10:28 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 22:16 ` Conor Dooley 2023-01-25 22:16 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 22:18 ` Conor Dooley 2023-01-25 22:18 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:51 ` Conor Dooley 2023-01-25 21:51 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:06 ` Conor Dooley 2023-01-26 21:06 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:24 ` Conor Dooley 2023-01-26 21:24 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:32 ` Conor Dooley 2023-01-26 21:32 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:44 ` Conor Dooley 2023-01-26 21:44 ` Conor Dooley 2023-01-31 2:55 ` Vineet Gupta 2023-01-31 2:55 ` Vineet Gupta 2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:11 ` Conor Dooley 2023-01-26 23:11 ` Conor Dooley 2023-02-06 12:00 ` Andy Chiu 2023-02-06 12:00 ` Andy Chiu 2023-02-06 13:40 ` Conor Dooley 2023-02-06 13:40 ` Conor Dooley 2023-02-10 12:00 ` Andy Chiu 2023-02-10 12:00 ` Andy Chiu 2023-02-07 14:36 ` Björn Töpel 2023-02-07 14:36 ` Björn Töpel 2023-02-13 22:54 ` Vineet Gupta 2023-02-13 22:54 ` Vineet Gupta 2023-02-14 6:43 ` Björn Töpel 2023-02-14 6:43 ` Björn Töpel 2023-02-14 15:36 ` Andy Chiu 2023-02-14 15:36 ` Andy Chiu 2023-02-14 16:50 ` Björn Töpel 2023-02-14 16:50 ` Björn Töpel 2023-02-14 17:24 ` Vineet Gupta 2023-02-14 17:24 ` Vineet Gupta 2023-02-15 7:14 ` Björn Töpel 2023-02-15 7:14 ` Björn Töpel 2023-02-15 14:39 ` Andy Chiu 2023-02-15 14:39 ` Andy Chiu 2023-02-07 21:18 ` Vineet Gupta 2023-02-07 21:18 ` Vineet Gupta 2023-02-08 9:20 ` Björn Töpel 2023-02-08 9:20 ` Björn Töpel 2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:19 ` Conor Dooley 2023-01-26 23:19 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:31 ` Conor Dooley 2023-01-27 20:31 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:43 ` Conor Dooley [this message] 2023-01-27 20:43 ` Conor Dooley 2023-01-30 9:58 ` Andy Chiu 2023-01-30 9:58 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 11:28 ` Anup Patel 2023-01-27 11:28 ` Anup Patel 2023-01-30 8:18 ` Andy Chiu 2023-01-30 8:18 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 22:24 ` Conor Dooley 2023-01-25 22:24 ` Conor Dooley 2023-01-30 6:38 ` Andy Chiu 2023-01-30 6:38 ` Andy Chiu 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 7:46 ` Andy Chiu 2023-01-30 7:46 ` Andy Chiu 2023-01-30 8:13 ` Conor Dooley 2023-01-30 8:13 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley
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