From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Anup Patel <apatel@ventanamicro.com>, Atish Patra <atishp@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Andrew Jones <ajones@ventanamicro.com>, Tsukasa OI <research_trasio@irq.a4lg.com>, Jisheng Zhang <jszhang@kernel.org> Subject: [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Date: Wed, 25 Jan 2023 14:20:44 +0000 [thread overview] Message-ID: <20230125142056.18356-8-andy.chiu@sifive.com> (raw) In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com> From: Greentime Hu <greentime.hu@sifive.com> This patch is used to detect the size of CPU vector registers and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. [guoren@linux.alibaba.com: add has_vector checking] Co-developed-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/include/asm/vector.h | 3 +++ arch/riscv/kernel/cpufeature.c | 12 +++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 0fda0faf5277..16cb4a1c1230 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -13,6 +13,8 @@ #include <asm/hwcap.h> #include <asm/csr.h> +extern unsigned long riscv_vsize; + static __always_inline bool has_vector(void) { return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]); @@ -31,6 +33,7 @@ static __always_inline void rvv_disable(void) #else /* ! CONFIG_RISCV_ISA_V */ static __always_inline bool has_vector(void) { return false; } +#define riscv_vsize (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c433899542ff..3aaae4e0b963 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -21,6 +21,7 @@ #include <asm/processor.h> #include <asm/smp.h> #include <asm/switch_to.h> +#include <asm/vector.h> #define NUM_ALPHA_EXTS ('z' - 'a' + 1) @@ -31,6 +32,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); EXPORT_SYMBOL(riscv_isa_ext_keys); +#ifdef CONFIG_RISCV_ISA_V +unsigned long riscv_vsize __read_mostly; +EXPORT_SYMBOL_GPL(riscv_vsize); +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -258,7 +263,12 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { -#ifndef CONFIG_RISCV_ISA_V +#ifdef CONFIG_RISCV_ISA_V + /* There are 32 vector registers with vlenb length. */ + rvv_enable(); + riscv_vsize = csr_read(CSR_VLENB) * 32; + rvv_disable(); +#else /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko.stuebner@vrull.eu>, Anup Patel <apatel@ventanamicro.com>, Atish Patra <atishp@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Andrew Jones <ajones@ventanamicro.com>, Tsukasa OI <research_trasio@irq.a4lg.com>, Jisheng Zhang <jszhang@kernel.org> Subject: [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Date: Wed, 25 Jan 2023 14:20:44 +0000 [thread overview] Message-ID: <20230125142056.18356-8-andy.chiu@sifive.com> (raw) In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com> From: Greentime Hu <greentime.hu@sifive.com> This patch is used to detect the size of CPU vector registers and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. [guoren@linux.alibaba.com: add has_vector checking] Co-developed-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/include/asm/vector.h | 3 +++ arch/riscv/kernel/cpufeature.c | 12 +++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 0fda0faf5277..16cb4a1c1230 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -13,6 +13,8 @@ #include <asm/hwcap.h> #include <asm/csr.h> +extern unsigned long riscv_vsize; + static __always_inline bool has_vector(void) { return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]); @@ -31,6 +33,7 @@ static __always_inline void rvv_disable(void) #else /* ! CONFIG_RISCV_ISA_V */ static __always_inline bool has_vector(void) { return false; } +#define riscv_vsize (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c433899542ff..3aaae4e0b963 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -21,6 +21,7 @@ #include <asm/processor.h> #include <asm/smp.h> #include <asm/switch_to.h> +#include <asm/vector.h> #define NUM_ALPHA_EXTS ('z' - 'a' + 1) @@ -31,6 +32,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); EXPORT_SYMBOL(riscv_isa_ext_keys); +#ifdef CONFIG_RISCV_ISA_V +unsigned long riscv_vsize __read_mostly; +EXPORT_SYMBOL_GPL(riscv_vsize); +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -258,7 +263,12 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { -#ifndef CONFIG_RISCV_ISA_V +#ifdef CONFIG_RISCV_ISA_V + /* There are 32 vector registers with vlenb length. */ + rvv_enable(); + riscv_vsize = csr_read(CSR_VLENB) * 32; + rvv_disable(); +#else /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-25 14:21 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:15 ` Conor Dooley 2023-01-25 21:15 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:33 ` Conor Dooley 2023-01-25 21:33 ` Conor Dooley 2023-01-28 7:09 ` Guo Ren 2023-01-28 7:09 ` Guo Ren 2023-01-28 10:28 ` Conor Dooley 2023-01-28 10:28 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 22:16 ` Conor Dooley 2023-01-25 22:16 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 22:18 ` Conor Dooley 2023-01-25 22:18 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:51 ` Conor Dooley 2023-01-25 21:51 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:06 ` Conor Dooley 2023-01-26 21:06 ` Conor Dooley 2023-01-25 14:20 ` Andy Chiu [this message] 2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu 2023-01-26 21:24 ` Conor Dooley 2023-01-26 21:24 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:32 ` Conor Dooley 2023-01-26 21:32 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:44 ` Conor Dooley 2023-01-26 21:44 ` Conor Dooley 2023-01-31 2:55 ` Vineet Gupta 2023-01-31 2:55 ` Vineet Gupta 2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:11 ` Conor Dooley 2023-01-26 23:11 ` Conor Dooley 2023-02-06 12:00 ` Andy Chiu 2023-02-06 12:00 ` Andy Chiu 2023-02-06 13:40 ` Conor Dooley 2023-02-06 13:40 ` Conor Dooley 2023-02-10 12:00 ` Andy Chiu 2023-02-10 12:00 ` Andy Chiu 2023-02-07 14:36 ` Björn Töpel 2023-02-07 14:36 ` Björn Töpel 2023-02-13 22:54 ` Vineet Gupta 2023-02-13 22:54 ` Vineet Gupta 2023-02-14 6:43 ` Björn Töpel 2023-02-14 6:43 ` Björn Töpel 2023-02-14 15:36 ` Andy Chiu 2023-02-14 15:36 ` Andy Chiu 2023-02-14 16:50 ` Björn Töpel 2023-02-14 16:50 ` Björn Töpel 2023-02-14 17:24 ` Vineet Gupta 2023-02-14 17:24 ` Vineet Gupta 2023-02-15 7:14 ` Björn Töpel 2023-02-15 7:14 ` Björn Töpel 2023-02-15 14:39 ` Andy Chiu 2023-02-15 14:39 ` Andy Chiu 2023-02-07 21:18 ` Vineet Gupta 2023-02-07 21:18 ` Vineet Gupta 2023-02-08 9:20 ` Björn Töpel 2023-02-08 9:20 ` Björn Töpel 2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:19 ` Conor Dooley 2023-01-26 23:19 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:31 ` Conor Dooley 2023-01-27 20:31 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:43 ` Conor Dooley 2023-01-27 20:43 ` Conor Dooley 2023-01-30 9:58 ` Andy Chiu 2023-01-30 9:58 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 11:28 ` Anup Patel 2023-01-27 11:28 ` Anup Patel 2023-01-30 8:18 ` Andy Chiu 2023-01-30 8:18 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 22:24 ` Conor Dooley 2023-01-25 22:24 ` Conor Dooley 2023-01-30 6:38 ` Andy Chiu 2023-01-30 6:38 ` Andy Chiu 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 7:46 ` Andy Chiu 2023-01-30 7:46 ` Andy Chiu 2023-01-30 8:13 ` Conor Dooley 2023-01-30 8:13 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley
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