From: Konrad Dybcio <konrad.dybcio@linaro.org> To: Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Akhil P Oommen <quic_akhilpo@quicinc.com>, Conor Dooley <conor+dt@kernel.org> Cc: Rob Clark <robdclark@chromium.org>, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio <konrad.dybcio@linaro.org>, Marijn Suijten <marijn.suijten@somainline.org>, freedreno@lists.freedesktop.org Subject: [PATCH v8 09/18] drm/msm/a6xx: Extend and explain UBWC config Date: Mon, 29 May 2023 15:52:28 +0200 [thread overview] Message-ID: <20230223-topic-gmuwrapper-v8-9-69c68206609e@linaro.org> (raw) In-Reply-To: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index dfde5fb65eed..58bf405b85d8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; - u32 amsbc = 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator = 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv = 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len = 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode = 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi = 0; + u32 hbb_lo = 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit = 3; + hbb_lo = 3; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; + hbb_lo = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) -- 2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Konrad Dybcio <konrad.dybcio@linaro.org> To: Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@somainline.org>, Akhil P Oommen <quic_akhilpo@quicinc.com>, Conor Dooley <conor+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark <robdclark@chromium.org>, Marijn Suijten <marijn.suijten@somainline.org>, Konrad Dybcio <konrad.dybcio@linaro.org> Subject: [PATCH v8 09/18] drm/msm/a6xx: Extend and explain UBWC config Date: Mon, 29 May 2023 15:52:28 +0200 [thread overview] Message-ID: <20230223-topic-gmuwrapper-v8-9-69c68206609e@linaro.org> (raw) In-Reply-To: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index dfde5fb65eed..58bf405b85d8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; - u32 amsbc = 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator = 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv = 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len = 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode = 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi = 0; + u32 hbb_lo = 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit = 3; + hbb_lo = 3; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; + hbb_lo = 1; amsbc = 1; rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) -- 2.40.1
next prev parent reply other threads:[~2023-05-29 13:52 UTC|newest] Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-29 13:52 [PATCH v8 00/18] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-05-29 13:52 ` [PATCH v8 01/18] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-05-30 12:26 ` Krzysztof Kozlowski 2023-05-30 12:26 ` Krzysztof Kozlowski 2023-05-30 13:35 ` Konrad Dybcio 2023-05-30 13:35 ` Konrad Dybcio 2023-06-08 20:58 ` Rob Herring 2023-06-08 20:58 ` Rob Herring 2023-06-09 9:12 ` Konrad Dybcio 2023-06-09 9:12 ` Konrad Dybcio 2023-06-08 21:00 ` Rob Herring 2023-06-08 21:00 ` Rob Herring 2023-05-29 13:52 ` [PATCH v8 02/18] dt-bindings: display/msm/gmu: Add GMU wrapper Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-05-29 13:52 ` [PATCH v8 03/18] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-05-29 13:52 ` [PATCH v8 04/18] drm/msm/a6xx: Move force keepalive vote removal to a6xx_gmu_force_off() Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-06 15:30 ` Akhil P Oommen 2023-06-06 15:30 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 05/18] drm/msm/a6xx: Move a6xx_bus_clear_pending_transactions to a6xx_gpu Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-06 15:35 ` Akhil P Oommen 2023-06-06 15:35 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 06/18] drm/msm/a6xx: Improve a6xx_bus_clear_pending_transactions() Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-06 17:09 ` Akhil P Oommen 2023-06-06 17:09 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 07/18] drm/msm/a6xx: Add a helper for software-resetting the GPU Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-06 17:18 ` Akhil P Oommen 2023-06-06 17:18 ` Akhil P Oommen 2023-06-15 10:34 ` Konrad Dybcio 2023-06-15 10:34 ` Konrad Dybcio 2023-06-15 20:11 ` Akhil P Oommen 2023-06-15 20:11 ` Akhil P Oommen 2023-06-15 20:59 ` Konrad Dybcio 2023-06-15 20:59 ` Konrad Dybcio 2023-06-15 21:17 ` Akhil P Oommen 2023-06-15 21:17 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 08/18] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-09 18:25 ` Akhil P Oommen 2023-06-09 18:25 ` Akhil P Oommen 2023-06-09 18:35 ` Konrad Dybcio 2023-06-09 18:35 ` Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio [this message] 2023-05-29 13:52 ` [PATCH v8 09/18] drm/msm/a6xx: Extend and explain UBWC config Konrad Dybcio 2023-06-09 18:41 ` Akhil P Oommen 2023-06-09 18:41 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 10/18] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-09 22:06 ` Akhil P Oommen 2023-06-09 22:06 ` Akhil P Oommen 2023-06-15 21:43 ` Konrad Dybcio 2023-06-15 21:43 ` Konrad Dybcio 2023-06-16 17:54 ` [Freedreno] " Akhil P Oommen 2023-06-16 17:54 ` Akhil P Oommen 2023-06-17 0:00 ` Konrad Dybcio 2023-06-17 0:00 ` Konrad Dybcio 2023-06-17 16:07 ` Akhil P Oommen 2023-06-17 16:07 ` Akhil P Oommen 2023-06-19 13:10 ` Konrad Dybcio 2023-06-19 13:10 ` Konrad Dybcio 2023-05-29 13:52 ` [PATCH v8 11/18] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-06 15:39 ` [Freedreno] " Akhil P Oommen 2023-06-06 15:39 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 12/18] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-05-29 13:52 ` [PATCH v8 13/18] drm/msm/a6xx: Add A610 support Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-14 19:41 ` Akhil P Oommen 2023-06-14 19:41 ` Akhil P Oommen 2023-06-15 10:02 ` Konrad Dybcio 2023-06-15 10:02 ` Konrad Dybcio 2023-05-29 13:52 ` [PATCH v8 14/18] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-14 19:44 ` Akhil P Oommen 2023-06-14 19:44 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 15/18] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-14 19:46 ` Akhil P Oommen 2023-06-14 19:46 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 16/18] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-14 19:50 ` Akhil P Oommen 2023-06-14 19:50 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 17/18] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-14 20:15 ` Akhil P Oommen 2023-06-14 20:15 ` Akhil P Oommen 2023-05-29 13:52 ` [PATCH v8 18/18] drm/msm/a6xx: Add A610 " Konrad Dybcio 2023-05-29 13:52 ` Konrad Dybcio 2023-06-14 20:18 ` Akhil P Oommen 2023-06-14 20:18 ` Akhil P Oommen 2023-06-15 10:04 ` Konrad Dybcio 2023-06-15 10:04 ` Konrad Dybcio 2023-05-31 12:14 ` [PATCH v8 00/18] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio 2023-05-31 12:14 ` Konrad Dybcio
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