* [U-Boot] mx31: Add board support for HALE TT-01
@ 2011-09-22 12:12 Helmut Raiger
2011-09-22 12:12 ` [U-Boot] [PATCH 1/2] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger
` (3 more replies)
0 siblings, 4 replies; 45+ messages in thread
From: Helmut Raiger @ 2011-09-22 12:12 UTC (permalink / raw)
To: u-boot
This adds support for HALE TT-01 (www.hale.at).
--
Scanned by MailScanner.
^ permalink raw reply [flat|nested] 45+ messages in thread* [U-Boot] [PATCH 1/2] mx31: define pins and init for UART2 and CSPI3 2011-09-22 12:12 [U-Boot] mx31: Add board support for HALE TT-01 Helmut Raiger @ 2011-09-22 12:12 ` Helmut Raiger 2011-09-22 12:12 ` [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 Helmut Raiger ` (2 subsequent siblings) 3 siblings, 0 replies; 45+ messages in thread From: Helmut Raiger @ 2011-09-22 12:12 UTC (permalink / raw) To: u-boot Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- arch/arm/cpu/arm1136/mx31/devices.c | 14 ++++++++++++++ arch/arm/include/asm/arch-mx31/clock.h | 1 + arch/arm/include/asm/arch-mx31/imx-regs.h | 16 ++++++++++++++++ 3 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 1e7d48f..ace48f4 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -38,7 +38,21 @@ void mx31_uart1_hw_init(void) } #endif +#ifdef CONFIG_SYS_MX31_UART2 +void mx31_uart2_hw_init(void) +{ + /* setup pins for UART2 */ + mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX); + mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX); + mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); + mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); +} +#endif + #ifdef CONFIG_MXC_SPI +/* note: putting several spi setups here makes no sense as they may differ + * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3) + */ void mx31_spi2_hw_init(void) { /* SPI2 */ diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index cc99a75..0270d96 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -38,6 +38,7 @@ extern void mx31_gpio_mux(unsigned long mode); extern void mx31_set_pad(enum iomux_pins pin, u32 config); void mx31_uart1_hw_init(void); +void mx31_uart2_hw_init(void); void mx31_spi2_hw_init(void); void mxc_hw_watchdog_enable(void); void mxc_hw_watchdog_reset(void); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 2064870..441dac4 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -597,12 +597,23 @@ enum iomux_pins { /* Register offsets based on IOMUXC_BASE */ /* 0x00 .. 0x7b */ +#define MUX_CTL_CSPI3_MISO 0x0c +#define MUX_CTL_CSPI3_SCLK 0x0d +#define MUX_CTL_CSPI3_SPI_RDY 0x0e +#define MUX_CTL_CSPI3_MOSI 0x13 + #define MUX_CTL_USBH2_DATA1 0x40 #define MUX_CTL_USBH2_DIR 0x44 #define MUX_CTL_USBH2_STP 0x45 #define MUX_CTL_USBH2_NXT 0x46 #define MUX_CTL_USBH2_DATA0 0x47 #define MUX_CTL_USBH2_CLK 0x4B + +#define MUX_CTL_TXD2 0x70 +#define MUX_CTL_RTS2 0x71 +#define MUX_CTL_CTS2 0x72 +#define MUX_CTL_RXD2 0x77 + #define MUX_CTL_RTS1 0x7c #define MUX_CTL_CTS1 0x7d #define MUX_CTL_DTR_DCE1 0x7e @@ -660,6 +671,11 @@ enum iomux_pins { #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) +#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) +#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) +#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) +#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) + #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 2011-09-22 12:12 [U-Boot] mx31: Add board support for HALE TT-01 Helmut Raiger 2011-09-22 12:12 ` [U-Boot] [PATCH 1/2] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger @ 2011-09-22 12:12 ` Helmut Raiger 2011-09-22 13:36 ` Fabio Estevam ` (2 more replies) 2011-10-14 8:05 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger 2011-10-27 11:31 ` [U-Boot] [PATCH V3 " Helmut Raiger 3 siblings, 3 replies; 45+ messages in thread From: Helmut Raiger @ 2011-09-22 12:12 UTC (permalink / raw) To: u-boot This adds basic board support for TT-01 based on the bluetechnix i.MX31 SOM. Currently only NOR-Flash boot is supported. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- Makefile | 4 + board/hale/tt01/Makefile | 53 +++++++++ board/hale/tt01/config.mk | 1 + board/hale/tt01/tt01.c | 98 ++++++++++++++++ include/configs/tt01.h | 283 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 439 insertions(+), 0 deletions(-) create mode 100644 board/hale/tt01/Makefile create mode 100644 board/hale/tt01/config.mk create mode 100644 board/hale/tt01/tt01.c create mode 100644 include/configs/tt01.h diff --git a/Makefile b/Makefile index e9ba6a4..aaed9e6 100644 --- a/Makefile +++ b/Makefile @@ -908,6 +908,10 @@ mx31pdk_nand_config : unconfig fi @$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31 +tt01_config : unconfig + @mkdir -p $(obj)include + @$(MKCONFIG) -n $@ -a tt01 arm arm1136 tt01 hale mx31 + ######################################################################### ## ARM1176 Systems ######################################################################### diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile new file mode 100644 index 0000000..18c83bb --- /dev/null +++ b/board/hale/tt01/Makefile @@ -0,0 +1,53 @@ +## +# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at> +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tt01.o +# reuse the mx31pdk low-level setup +SOBJS := ../../freescale/mx31pdk/lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/hale/tt01/config.mk b/board/hale/tt01/config.mk new file mode 100644 index 0000000..a7887ba --- /dev/null +++ b/board/hale/tt01/config.mk @@ -0,0 +1 @@ +CONFIG_SYS_TEXT_BASE = 0xa0000000 diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c new file mode 100644 index 0000000..3bae2b4 --- /dev/null +++ b/board/hale/tt01/tt01.c @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BOARD_STRING "Board: HALE TT-01" + +void tt01_spi3_hw_init(void) +{ + /* CSPI3 */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC)); + /* CSPI3, SS0 = Atlas */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1)); + + /* start CSPI3 clock (3 = always on except if PLL off) */ + writel(readl(CCM_CGR0) | (3 << 16), CCM_CGR0); +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +int board_early_init_f(void) +{ + /* CS4: FPGA incl. network controller */ + __REG(CSCR_U(4)) = 0x0000dcf6; + __REG(CSCR_L(4)) = 0x444A4541; + __REG(CSCR_A(4)) = 0x44443302; + + /* Setup UART2 and SPI3 pins */ + mx31_uart2_hw_init(); + tt01_spi3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* board id for linux, not in mach-types.h yet */ + gd->bd->bi_arch_number = 3726; /* MACH_TYPE_TT01 = 3726 */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + return 0; +} + +int checkboard(void) +{ + printf(BOARD_STRING "\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/include/configs/tt01.h b/include/configs/tt01.h new file mode 100644 index 0000000..22fb806 --- /dev/null +++ b/include/configs/tt01.h @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> + * + * Configuration settings for the HALE TT-01 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +/* High Level Configuration Options */ +#define CONFIG_ARM1136 +#define CONFIG_MX31 +#define CONFIG_MX31_HCLK_FREQ 26000000 +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/*----------------------------------------------------------------------- + * Physical Memory Map: + * CS settings are defined by i.MX31: + * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 + * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 + * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. + * + * HALE set-up of the bluetechnix board for now is: + * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface + * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 + * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) + * the flash chip is a mirrorbit S29WS256N ! + * - the PSRAM is hooked to CS5 (0xB6000000) + * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 + * - 64Mbit = 8MByte (will go away in the production set-up) + * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: + * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks + * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface + * + * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM + * is not used right now. We should be able to reduce the SOM to NAND flash + * only and boot from there. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + +/* default load address, 1MB up the road */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Size of malloc() pool, make sure possible frame buffer fits + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) +/* Bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* memtest works on all but the last 1MB (u-boot) and malloc area */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END \ + (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000)) + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_SPANSION_S29WS_N +/* TODO: bluetechnix did undefine these for some purpose + * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + * #define CONFIG_SYS_FLASH_PROTECTION + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ + +/*--------------------------------------------------------------------------- + * FLASH and environment organization, only the Spansion chip is supported: + * - it has 254 * 128kB + 8 * 32kB blocks + * - this setup uses 4*32k+128k as monitor space = 0xA000 0000 to 0xA003 FFFF + * and as environment 2 sections with 128k = + * A004 0000 to 0xA005 FFFF and 0xA006 0000 to 0xA007 FFFF + * - this could be less, but no-one is going to use the NOR flash anyway. + * + * Monitor is at the beginning of the NOR-Flash, 1MB reserved + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* S29WS256N (inside S71WS256ND0) has 4 32KiB small sectors at both ends. */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +/* Hardware drivers */ + +/* + * on TT-01 UART1 pins are used by Audio, so we use UART2 + * make sure that the transceiver is enabled during PL=1 for testing! + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX31_UART2 + +#define CONFIG_MXC_SPI +#define CONFIG_MXC_GPIO + +/* MC13783 connected to CSPI3 and SS0 */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 2 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) + +#define CONFIG_RTC_MC13783 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +/* console is UART2 on TT-01 */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* ethernet setup for the onboard smc9118 */ +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_SMC911X +/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */ +#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) +#define CONFIG_SMC911X_16_BIT + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +/* this is currently not supported, mxc_nand.c is too incomplete for it */ +#undef CONFIG_CMD_MTDPARTS + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_NAND +/* #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support + * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports + * a software locking scheme. + */ + +#define CONFIG_BOOTDELAY 3 + +/* currently a default setting for booting via script is implemented + * set user to login name and serverip to tftp host, define your + * boot behaviour in bootscript.loginname + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=dhcp bootscript.$(user); source\0" + +#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ +#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ + +/* + * Miscellaneous configurable options + */ +/* hush adds about 1kB in size */ +#define CONFIG_HUSH_PARSER +#define CONFIG_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "TT01> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_NAND_MXC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +/* actually this is nothing someone wants to configure! + * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init() + * is not used by the driver. + */ +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +#define CONFIG_MXC_NAND_HWECC + +/* the current u-boot driver does not use the nand flash setup! */ +#define CONFIG_SYS_NAND_LARGEPAGE +/* it's not 16 bit: + * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT + * the current u-boot mxc_nand.c tries to auto-detect, but this only + * reads the reset + */ + +/* Configuration of lowlevel_init.S (clocks and SDRAM) */ +#define CCM_CCMR_SETUP 0x074B0BF5 +#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ + PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ + PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ + PDR0_MCU_PODF(0)) +#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ + PLL_MFN(12)) + +#define ESDMISC_MDDR_SETUP 0x00000004 +#define ESDMISC_MDDR_RESET_DL 0x0000000c +/* decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below: + * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10 + * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + * note: all but tWTR (1), tRC (111) are reset defaults, + * the same values work in the jtag configuration + * + * bluetechnix setup has 0x75e73a (for 128MB) = + * 0b 0111 0101 1110 0111 0011 1010 + * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01 + * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + */ +#define ESDCFG0_MDDR_SETUP 0x006ac73a +#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) +#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ(2) | ESDCTL_BL(1)) +#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) +#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) +#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) +#define ESDCTL_RW ESDCTL_SETTINGS + +#endif /* __CONFIG_H */ -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 2011-09-22 12:12 ` [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 Helmut Raiger @ 2011-09-22 13:36 ` Fabio Estevam 2011-09-22 13:51 ` Stefano Babic 2011-09-22 14:08 ` Wolfgang Denk 2 siblings, 0 replies; 45+ messages in thread From: Fabio Estevam @ 2011-09-22 13:36 UTC (permalink / raw) To: u-boot On Thu, Sep 22, 2011 at 9:12 AM, Helmut Raiger <helmut.raiger@hale.at> wrote: > This adds basic board support for TT-01 based on > the bluetechnix i.MX31 SOM. Currently only NOR-Flash > boot is supported. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > ?Makefile ? ? ? ? ? ? ? ? ?| ? ?4 + > ?board/hale/tt01/Makefile ?| ? 53 +++++++++ > ?board/hale/tt01/config.mk | ? ?1 + > ?board/hale/tt01/tt01.c ? ?| ? 98 ++++++++++++++++ > ?include/configs/tt01.h ? ?| ?283 +++++++++++++++++++++++++++++++++++++++++++++ > ?5 files changed, 439 insertions(+), 0 deletions(-) > ?create mode 100644 board/hale/tt01/Makefile > ?create mode 100644 board/hale/tt01/config.mk > ?create mode 100644 board/hale/tt01/tt01.c > ?create mode 100644 include/configs/tt01.h You missed to add an entry to the MAINTAINERS file. ... > diff --git a/board/hale/tt01/config.mk b/board/hale/tt01/config.mk > new file mode 100644 > index 0000000..a7887ba > --- /dev/null > +++ b/board/hale/tt01/config.mk > @@ -0,0 +1 @@ > +CONFIG_SYS_TEXT_BASE = 0xa0000000 Do you really need to create one file to store a single line? You can place CONFIG_SYS_TEXT_BASE in the tt01.h > diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c > new file mode 100644 > index 0000000..3bae2b4 > --- /dev/null ... > + ? ? ? /* start CSPI3 clock (3 = always on except if PLL off) */ > + ? ? ? writel(readl(CCM_CGR0) | (3 << 16), CCM_CGR0); You can use setbits_le32 here. Regards, Fabio Estevam ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 2011-09-22 12:12 ` [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 Helmut Raiger 2011-09-22 13:36 ` Fabio Estevam @ 2011-09-22 13:51 ` Stefano Babic 2011-10-06 13:07 ` Helmut Raiger 2011-09-22 14:08 ` Wolfgang Denk 2 siblings, 1 reply; 45+ messages in thread From: Stefano Babic @ 2011-09-22 13:51 UTC (permalink / raw) To: u-boot On 09/22/2011 02:12 PM, Helmut Raiger wrote: > This adds basic board support for TT-01 based on > the bluetechnix i.MX31 SOM. Currently only NOR-Flash > boot is supported. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Hi Helmut, > --- > Makefile | 4 + > board/hale/tt01/Makefile | 53 +++++++++ > board/hale/tt01/config.mk | 1 + > board/hale/tt01/tt01.c | 98 ++++++++++++++++ > include/configs/tt01.h | 283 +++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 439 insertions(+), 0 deletions(-) > create mode 100644 board/hale/tt01/Makefile > create mode 100644 board/hale/tt01/config.mk > create mode 100644 board/hale/tt01/tt01.c > create mode 100644 include/configs/tt01.h Your entry in MAINTAINERS file is missing and you have not updated boards.cfg. > > diff --git a/Makefile b/Makefile > index e9ba6a4..aaed9e6 100644 > --- a/Makefile > +++ b/Makefile > @@ -908,6 +908,10 @@ mx31pdk_nand_config : unconfig > fi > @$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31 > > +tt01_config : unconfig > + @mkdir -p $(obj)include > + @$(MKCONFIG) -n $@ -a tt01 arm arm1136 tt01 hale mx31 > + There is no need anymore to change the main Makefile - new boards are added only to voards.cfg. > ######################################################################### > ## ARM1176 Systems > ######################################################################### > diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile > new file mode 100644 > index 0000000..18c83bb > --- /dev/null > +++ b/board/hale/tt01/Makefile > @@ -0,0 +1,53 @@ > +## Double # > +# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at> > +# (C) Copyright 2000-2006 > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS := tt01.o > +# reuse the mx31pdk low-level setup > +SOBJS := ../../freescale/mx31pdk/lowlevel_init.o It is always a good idea to reuse code, but taking it to another board seems hackish. Your board could become broken if the mx31pdk's maintainer change his code. Reading this file I do not see (except setting the AIPS) no good reason to write this part in assembly. Everything can be done for example in board_early_init_f, and even better we can rationalize this code and put it into arch/cpu/arm1136/mx31. > +######################################################################### > diff --git a/board/hale/tt01/config.mk b/board/hale/tt01/config.mk > new file mode 100644 > index 0000000..a7887ba > --- /dev/null > +++ b/board/hale/tt01/config.mk > @@ -0,0 +1 @@ > +CONFIG_SYS_TEXT_BASE = 0xa0000000 There is no need for a config.mk => move CONFIG_SYS_TEXT_BASE into tt01.h > +#include <common.h> > +#include <netdev.h> > +#include <command.h> > +#include <asm/arch/clock.h> > +#include <asm/io.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define BOARD_STRING "Board: HALE TT-01" > + > +void tt01_spi3_hw_init(void) > +{ > + /* CSPI3 */ > + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC)); > + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC)); > + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC)); > + /* CSPI3, SS0 = Atlas */ ^-spaces instead of TAB > + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1)); > + > + /* start CSPI3 clock (3 = always on except if PLL off) */ > + writel(readl(CCM_CGR0) | (3 << 16), CCM_CGR0); > +} > + > +int dram_init(void) > +{ > + /* dram_init must store complete ramsize in gd->ram_size */ > + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, > + PHYS_SDRAM_1_SIZE); > + return 0; > +} > + > +void dram_init_banksize(void) > +{ > + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; > + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; > +} If, as in your case, you have only one bank and CONFIG_SYS_SDRAM_BASE = PHYS_SDRAM_1, you can drop completely this function. This is a weak function, and your code duplicates the "standard" behavior in arch/arm/lib/board.c > + > +int board_early_init_f(void) > +{ > + /* CS4: FPGA incl. network controller */ > + __REG(CSCR_U(4)) = 0x0000dcf6; > + __REG(CSCR_L(4)) = 0x444A4541; > + __REG(CSCR_A(4)) = 0x44443302; Time to fix access to WEIM. As access via __REG are not allowed for new code, please add a structure for WEIM and use accessors to write these registers. > + > +int board_init(void) > +{ > + /* board id for linux, not in mach-types.h yet */ > + gd->bd->bi_arch_number = 3726; /* MACH_TYPE_TT01 = 3726 */ Then define CONFIG_MACH_TYPE into tt01.h and drop the previous lines. The MACH-ID is automatically set by common code if CONFIG_MACH_TYPE is set. > diff --git a/include/configs/tt01.h b/include/configs/tt01.h > new file mode 100644 > index 0000000..22fb806 > --- /dev/null > +++ b/include/configs/tt01.h > @@ -0,0 +1,283 @@ > +/* > + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> > + * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> > + * > + * Configuration settings for the HALE TT-01 board. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include <asm/arch/imx-regs.h> > + > +/* High Level Configuration Options */ > +#define CONFIG_ARM1136 > +#define CONFIG_MX31 > +#define CONFIG_MX31_HCLK_FREQ 26000000 > +#define CONFIG_MX31_CLK32 32768 > + > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > + > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_INITRD_TAG > + > +/*----------------------------------------------------------------------- > + * Physical Memory Map: > + * CS settings are defined by i.MX31: > + * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 > + * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 > + * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. > + * > + * HALE set-up of the bluetechnix board for now is: > + * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface > + * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 > + * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) > + * the flash chip is a mirrorbit S29WS256N ! > + * - the PSRAM is hooked to CS5 (0xB6000000) > + * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 > + * - 64Mbit = 8MByte (will go away in the production set-up) > + * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: > + * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks > + * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface > + * > + * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM > + * is not used right now. We should be able to reduce the SOM to NAND flash > + * only and boot from there. Ok, understood. You will use the SPL framework later. > + */ > +#define CONFIG_NR_DRAM_BANKS 1 > +#define PHYS_SDRAM_1 CSD0_BASE > +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) > + > +#define CONFIG_BOARD_EARLY_INIT_F > + > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 > +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR > +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE > +#define CONFIG_SYS_GBL_DATA_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) > + > +/* default load address, 1MB up the road */ > +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) > + > +/*----------------------------------------------------------------------- > + * Stack sizes > + * > + * The stack sizes are set up in start.S using the settings below > + */ > +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ > + > +/* > + * Size of malloc() pool, make sure possible frame buffer fits > + */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) 10 MB for heap in bootloader ? Is it ok ? I am only asking if it is really wanted. > +/* Bytes reserved for initial data */ > +#define CONFIG_SYS_GBL_DATA_SIZE 128 This is automatically generated. You should not set it. > +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ > +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ > +#define CONFIG_FLASH_SPANSION_S29WS_N > +/* TODO: bluetechnix did undefine these for some purpose if you do not need to undefine, you can drop this comment. Maybe there is no issues with lock/unlock mechanism with the flash you have chosen. > +#define CONFIG_SYS_FLASH_BASE CS0_BASE > +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ > +#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ > + > +/*--------------------------------------------------------------------------- > + * FLASH and environment organization, only the Spansion chip is supported: > + * - it has 254 * 128kB + 8 * 32kB blocks > + * - this setup uses 4*32k+128k as monitor space = 0xA000 0000 to 0xA003 FFFF > + * and as environment 2 sections with 128k = > + * A004 0000 to 0xA005 FFFF and 0xA006 0000 to 0xA007 FFFF > + * - this could be less, but no-one is going to use the NOR flash anyway. > + * > + * Monitor is at the beginning of the NOR-Flash, 1MB reserved > + */ > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE > +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) > + > +#define CONFIG_ENV_IS_IN_FLASH 1 > +#define CONFIG_ENV_SECT_SIZE (128 * 1024) > +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE Regarding your previous comment: you could set CONFIG_ENV_SIZE to a smaller value as CONFIG_ENV_SECT_SIZE, and this can speed up get/set of the environment. Or you could save the environment in tha last (smaller) sectors. > + > +/* S29WS256N (inside S71WS256ND0) has 4 32KiB small sectors at both ends. */ > +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) The comment is correct, but it has nothing to do with the defines, because you are not putting the env in the 32KiB sectors. > + > +/* Hardware drivers */ > + > +/* > + * on TT-01 UART1 pins are used by Audio, so we use UART2 > + * make sure that the transceiver is enabled during PL=1 for testing! What does it mean PL=1 ? > +/*********************************************************** > + * Command definition > + ***********************************************************/ > + > +#include <config_cmd_default.h> > + > +/* this is currently not supported, mxc_nand.c is too incomplete for it */ Only for my understanding: Which is the issue with mxc_nand.c ? At the moment, we have several boards using it, and I wonder it is incomplete. What do you mean ? > +/* currently a default setting for booting via script is implemented > + * set user to login name and serverip to tftp host, define your > + * boot behaviour in bootscript.loginname > + */ Wrong multiline comment. This must be fixed globally. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 2011-09-22 13:51 ` Stefano Babic @ 2011-10-06 13:07 ` Helmut Raiger 2011-10-06 13:27 ` Stefano Babic 0 siblings, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-10-06 13:07 UTC (permalink / raw) To: u-boot Hi Stefano, >> +include $(TOPDIR)/config.mk >> + >> +LIB = $(obj)lib$(BOARD).o >> + >> +COBJS := tt01.o >> +# reuse the mx31pdk low-level setup >> +SOBJS := ../../freescale/mx31pdk/lowlevel_init.o > It is always a good idea to reuse code, but taking it to another board > seems hackish. Your board could become broken if the mx31pdk's > maintainer change his code. > > Reading this file I do not see (except setting the AIPS) no good reason > to write this part in assembly. Everything can be done for example in > board_early_init_f, and even better we can rationalize this code and put > it into arch/cpu/arm1136/mx31. As far as I understood this is called from arch/arm/cpu/arm1136/start.S before stack is setup. I don't know much about C-calling convention on the arm1136, but this might be the reason why it's done in assembly. I'd rather not touch start.S, so I'll copy the file over from mx31pdk? >> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) > 10 MB for heap in bootloader ? Is it ok ? I am only asking if it is > really wanted. We are about to display large compressed bitmaps in u-boot, that's why the heap is that large. The frame buffer driver patch http://patchwork.ozlabs.org/patch/113341/ is still being reviewed, that is why I left it out here (but kept the heap size). Additionally I don't care much about time and space here. The production units will boot from NAND and we'll use a different setup there. That's why I reserved 1MB for u-boot, I simply didn't want it to overwrite my environment when being reprogrammed. >> +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ >> +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ >> +#define CONFIG_FLASH_SPANSION_S29WS_N >> +/* TODO: bluetechnix did undefine these for some purpose > if you do not need to undefine, you can drop this comment. Maybe there > is no issues with lock/unlock mechanism with the flash you have chosen. Bluetechnix is the supplier of the SOM we are using. Their original version of u-boot (1.2 or so) defined these values. So the flash is definitely the same. I'd like to review this later, therefore the TODO. >> +#define CONFIG_ENV_SECT_SIZE (128 * 1024) >> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE > Regarding your previous comment: you could set CONFIG_ENV_SIZE to a > smaller value as CONFIG_ENV_SECT_SIZE, and this can speed up get/set of > the environment. Or you could save the environment in tha last (smaller) > sectors. > I'll look into the speed change, but as described above I don't really care about size. >> + * on TT-01 UART1 pins are used by Audio, so we use UART2 >> + * make sure that the transceiver is enabled during PL=1 for testing! > What does it mean PL=1 ? > Nothing that concerns u-boot, it means P(ower)L(evel)=1. The TT-01 implements a hardware that turns off components depending on the said power level. In PL=1 the RS232 transceiver is usually off. >> +/* this is currently not supported, mxc_nand.c is too incomplete for it */ > Only for my understanding: Which is the issue with mxc_nand.c ? At the > moment, we have several boards using it, and I wonder it is incomplete. > What do you mean ? Part of this whole mess is, that I actually wrote this board support 2 years ago and simply rebased to finally contribute the stuff. Probably there is no issue with mxc_nand.c any more (and I don't remember what was the problem). Thanks for your thorough review, I'll pass along V2 when we come to a solution about low_level.S Helmut -- Scanned by MailScanner. ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 2011-10-06 13:07 ` Helmut Raiger @ 2011-10-06 13:27 ` Stefano Babic 0 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-06 13:27 UTC (permalink / raw) To: u-boot On 10/06/2011 03:07 PM, Helmut Raiger wrote: > Hi Stefano, > Hi Helmut, >> >> Reading this file I do not see (except setting the AIPS) no good reason >> to write this part in assembly. Everything can be done for example in >> board_early_init_f, and even better we can rationalize this code and put >> it into arch/cpu/arm1136/mx31. > > As far as I understood this is called from arch/arm/cpu/arm1136/start.S > before stack is setup. I don't know much about C-calling convention > on the arm1136, but this might be the reason why it's done in assembly. > I'd rather not touch start.S, so I'll copy the file over from mx31pdk? A way I used in the past is to set up the stack in the lowlevel_init assembly routine and then calling my own C function. Again, probably is not needed anymore, but you can check this. The assembly start.S ends calling board_init_f(), and this runs before relocation. At this point, the stack pointer is already set. The board_init_f() then calls board_early_init_f(), if CONFIG_BOARD_EARLY_INIT_F is set, and you can add your specific initialization here. You can take a look at the patches I sent last month for the flea3 board. I factorized code for the mx35. I know, this does not help for mx31, but it is very similar and both arm1136. I have not touched start.S from the arm1136 drirectory(this is general code), and the DRAM setup is done in C code. > We are about to display large compressed bitmaps in u-boot, that's why > the heap is that large. The frame buffer driver patch > http://patchwork.ozlabs.org/patch/113341/ is still being reviewed, > that is why I left it out here (but kept the heap size). Ok, agreed. > Additionally I don't care much about time and space here. The production > units will boot from NAND and we'll use a different setup there. > That's why I reserved 1MB for u-boot, I simply didn't want it to overwrite > my environment when being reprogrammed. Ok, understood, thanks for clarification. > >>> +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ >>> +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ >>> +#define CONFIG_FLASH_SPANSION_S29WS_N >>> +/* TODO: bluetechnix did undefine these for some purpose >> if you do not need to undefine, you can drop this comment. Maybe there >> is no issues with lock/unlock mechanism with the flash you have chosen. > > Bluetechnix is the supplier of the SOM we are using. Their original > version of u-boot (1.2 or so) defined these values. So the flash is > definitely the same. I'd like to review this later, therefore the TODO. Ok, thanks. Probably it is worth you add this explanation to the comment, so nobody will ask you again ;-) >>> + * on TT-01 UART1 pins are used by Audio, so we use UART2 >>> + * make sure that the transceiver is enabled during PL=1 for testing! >> What does it mean PL=1 ? >> > Nothing that concerns u-boot, it means P(ower)L(evel)=1. The TT-01 > implements a hardware that turns off components depending on > the said power level. In PL=1 the RS232 transceiver is usually off. Understood. Add simply these line to the comment, they complete the explanation. > >>> +/* this is currently not supported, mxc_nand.c is too incomplete for >>> it */ >> Only for my understanding: Which is the issue with mxc_nand.c ? At the >> moment, we have several boards using it, and I wonder it is incomplete. >> What do you mean ? > > Part of this whole mess is, that I actually wrote this board support 2 > years ago and simply rebased to finally contribute the stuff. Probably > there is no issue with mxc_nand.c any more (and I don't remember > what was the problem). Ok. Probably you need only to retest NAND again, and check if there are open issues. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 2011-09-22 12:12 ` [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 Helmut Raiger 2011-09-22 13:36 ` Fabio Estevam 2011-09-22 13:51 ` Stefano Babic @ 2011-09-22 14:08 ` Wolfgang Denk 2011-09-28 12:48 ` [U-Boot] mx31: Approach for WEIM CS accessors Helmut Raiger 2 siblings, 1 reply; 45+ messages in thread From: Wolfgang Denk @ 2011-09-22 14:08 UTC (permalink / raw) To: u-boot Dear Helmut Raiger, In message <1316693575-20726-3-git-send-email-helmut.raiger@hale.at> you wrote: > This adds basic board support for TT-01 based on > the bluetechnix i.MX31 SOM. Currently only NOR-Flash > boot is supported. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > Makefile | 4 + > board/hale/tt01/Makefile | 53 +++++++++ > board/hale/tt01/config.mk | 1 + > board/hale/tt01/tt01.c | 98 ++++++++++++++++ > include/configs/tt01.h | 283 +++++++++++++++++++++++++++++++++++++++++++++ > 5 files changed, 439 insertions(+), 0 deletions(-) > create mode 100644 board/hale/tt01/Makefile > create mode 100644 board/hale/tt01/config.mk > create mode 100644 board/hale/tt01/tt01.c > create mode 100644 include/configs/tt01.h Entry to MAINTAINERS missing. > diff --git a/Makefile b/Makefile > index e9ba6a4..aaed9e6 100644 > --- a/Makefile > +++ b/Makefile > @@ -908,6 +908,10 @@ mx31pdk_nand_config : unconfig > fi > @$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31 > > +tt01_config : unconfig > + @mkdir -p $(obj)include > + @$(MKCONFIG) -n $@ -a tt01 arm arm1136 tt01 hale mx31 We don't add boards to Makefile any more. Please add instead to boards.cfg ... > + /* start CSPI3 clock (3 = always on except if PLL off) */ > + writel(readl(CCM_CGR0) | (3 << 16), CCM_CGR0); Please use setbits() instead. > +int board_early_init_f(void) > +{ > + /* CS4: FPGA incl. network controller */ > + __REG(CSCR_U(4)) = 0x0000dcf6; > + __REG(CSCR_L(4)) = 0x444A4541; > + __REG(CSCR_A(4)) = 0x44443302; We don't allow such accesses any more. Please use proper I/O accessors instead. And please introduce some symbolic constants for the magic numbers, and add comments whatthese are. > +int board_init(void) > +{ > + /* board id for linux, not in mach-types.h yet */ > + gd->bd->bi_arch_number = 3726; /* MACH_TYPE_TT01 = 3726 */ NAK. Please use standard approach for handling the mach_id. > +/*----------------------------------------------------------------------- > + * Physical Memory Map: ... Incorrect multiline comment style. Please fix globally. ... > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE > +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) Are you really, really sure about this? I doubt it... > +#define CONFIG_ENV_IS_IN_FLASH 1 Please do not define values for macros that select features only. Please fix globally. > +#include <config_cmd_default.h> > + > +/* this is currently not supported, mxc_nand.c is too incomplete for it */ > +#undef CONFIG_CMD_MTDPARTS Please do not undef what is not defined in the first place. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de You go slow, be gentle. It's no one-way street -- you know how you feel and that's all. It's how the girl feels too. Don't press. If the girl feels anything for you at all, you'll know. -- Kirk, "Charlie X", stardate 1535.8 ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] mx31: Approach for WEIM CS accessors 2011-09-22 14:08 ` Wolfgang Denk @ 2011-09-28 12:48 ` Helmut Raiger 2011-09-28 12:48 ` [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor Helmut Raiger 0 siblings, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-09-28 12:48 UTC (permalink / raw) To: u-boot I tried to fix the magic numbers used by ALL mx31 boards (except one CS in qong.c) by using some macros. I stayed away from bitfields as it would have resulted in a very verbose change (something like the setup of CS 3 in qong.c). To verify the code I used this helper: -------------- cut ----------- #include <stdio.h> typedef unsigned int uint; /* 13 fields of the upper CS control register */ #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ cnc, wsc, ew, wws, edc) \ ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ (wws) << 4 | (edc) << 0) /* 12 fields of the lower CS control register */ #define CSCR_L(oea, oen, ebwa, ebwn, \ csa, ebc, dsz, csn, psr, cre, wrap, csen) \ ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) /* 14 fields of the additional CS control register */ #define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ wwu, age, cnc2, fce) \ ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ (age) << 2 | (cnc2) << 1 | (fce) << 0) void decode(unsigned int u, unsigned int l, unsigned int a) { /* 13 fields of the upper CS control register */ uint sp = (u >> 31) & 1; uint wp = (u >> 30) & 1; uint bcd = (u >> 28) & 1; uint bcs = (u >> 24) & 15; uint psz = (u >> 22) & 3; uint pme = (u >> 21) & 1; uint sync = (u >> 20) & 1; uint dol = (u >> 16) & 15; uint cnc = (u >> 14) & 3; uint wsc = (u >> 8) & 31; uint ew = (u >> 7) & 1; uint wws = (u >> 4) & 7; uint edc = (u >> 0) & 15; /* 12 fields of the lower CS control register */ uint oea = (l >> 28) & 15; uint oen = (l >> 24) & 15; uint ebwa = (l >> 20) & 15; uint ebwn = (l >> 16) & 15; uint csa = (l >> 12) & 15; uint ebc = (l >> 11) & 1; uint dsz = (l >> 8) & 7; uint csn = (l >> 4) & 15; uint psr = (l >> 3) & 1; uint cre = (l >> 2) & 1; uint wrap = (l >> 1) & 1; uint csen = (l >> 0) & 1; /* 14 fields of the additional CS control register */ uint ebra = (a >> 28) & 15; uint ebrn = (a >> 24) & 15; uint rwa = (a >> 20) & 15; uint rwn = (a >> 16) & 15; uint mum = (a >> 15) & 1; uint lah = (a >> 13) & 3; uint lbn = (a >> 10) & 7; uint lba = (a >> 8) & 3; uint dww = (a >> 6) & 3; uint dct = (a >> 4) & 3; uint wwu = (a >> 3) & 1; uint age = (a >> 2) & 1; uint cnc2 = (a >> 1) & 1; uint fce = (a >> 0) & 1; printf("---- decode(0x%08x, 0x%08x, 0x%08x):\n", u, l, a); printf("/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */\n"); printf("CSCR_U(%2u,%2u,%3u,%3u,%3u,%3u,%4u,%3u,%3u,%3u,%2u,%3u,%3u)\n", sp, wp, bcd, bcs, psz, pme, sync, dol, cnc, wsc, ew, wws, edc); if(CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, cnc, wsc, ew, wws, edc) != u) printf("U is wrong\n"); printf("/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */\n"); printf("CSCR_L(%3u,%3u,%4u,%4u,%3u,%3u,%3u,%3u,%3u,%3u,%4u,%4u)\n", oea, oen, ebwa, ebwn, csa, ebc, dsz, csn, psr, cre, wrap, csen); if(CSCR_L(oea, oen, ebwa, ebwn, csa, ebc, dsz, csn, psr, cre, wrap, csen) != l) printf("L is wrong\n"); printf("/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce */\n"); printf("CSCR_A(%2u,%4u,%3u,%3u,%3u,%3u,%3u,%3u,%3u,%3u,%3u,%3u,%4u,%3u)\n", ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, wwu, age, cnc2, fce); if(CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, wwu, age, cnc2, fce) != a) printf("A is wrong\n"); } int main(void) { printf("qong: CS1 "); decode(0x00000A01, 0x20040501, 0x04020C00); printf("qong: CS3 "); decode(0x00004f00, 0x20013b31, 0x00020800); printf("tt01: CS4 "); decode(0x0000dcf6, 0x444A4541, 0x44443302); printf("pdk: CS5 "); decode(0x0000d843, 0x22252521, 0x22220a00); printf("ads: CS0 "); decode(0x00000f00, 0x10000D03, 0x00720900); printf("phycore: CS0 "); decode(0x0000cf03, 0x10000d03, 0x00720900); printf("phycore: CS1 "); decode(0x0000df06, 0x444a4541, 0x44443302); printf("phycore: CS4 "); decode(0x0000d843, 0x22252521, 0x22220a00); printf("litekit: CS0 "); decode(0x0000cf03, 0xa0330d01, 0x00220800); printf("litekit: CS4 "); decode(0x0000dcf6, 0x444a4541, 0x44443302); } -------------------- cut -------------------- -- Scanned by MailScanner. ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor 2011-09-28 12:48 ` [U-Boot] mx31: Approach for WEIM CS accessors Helmut Raiger @ 2011-09-28 12:48 ` Helmut Raiger 2011-09-28 15:14 ` Stefano Babic ` (2 more replies) 0 siblings, 3 replies; 45+ messages in thread From: Helmut Raiger @ 2011-09-28 12:48 UTC (permalink / raw) To: u-boot Some macros are added to support the setup for i.MX31 WEIM chip selects. As a compromise between verbosity and readability an ASCII-art'ish bit comment is used instead of bitfields. All i.MX31 boards have been patched to use this approach using a helper program to verify the changes. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- arch/arm/include/asm/arch-mx31/imx-regs.h | 38 ++++++++++++- board/davedenx/qong/qong.c | 79 +++++++++------------------ board/freescale/mx31ads/mx31ads.c | 13 +++-- board/freescale/mx31pdk/mx31pdk.c | 11 +++- board/imx31_phycore/imx31_phycore.c | 36 +++++++++--- board/logicpd/imx31_litekit/imx31_litekit.c | 24 ++++++-- 6 files changed, 123 insertions(+), 78 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 2064870..d535830 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -25,6 +25,7 @@ #define __ASM_ARCH_MX31_IMX_REGS_H #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/io.h> #include <asm/types.h> /* Clock control module registers */ @@ -534,10 +535,41 @@ enum iomux_pins { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +/* 13 fields of the upper CS control register */ +#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ + (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ + (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + #define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +#define WEIM_CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define WEIM_CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define WEIM_CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) + +#ifndef __ASSEMBLER__ +static inline void mx31_setup_weimcs(int cs, + unsigned int upper, unsigned int lower, unsigned int add) +{ + writel(upper, WEIM_CSCR_U(cs)); + writel(lower, WEIM_CSCR_L(cs)); + writel(add, WEIM_CSCR_A(cs)); +} +#endif + #define IOMUXC_BASE 0x43FAC000 #define IOMUXC_GPR (IOMUXC_BASE + 0x8) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 99432ed..6cd9e10 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -25,7 +25,6 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <asm/io.h> #include <nand.h> #include <fsl_pmic.h> #include <asm/gpio.h> @@ -61,11 +60,15 @@ static void qong_fpga_reset(void) int board_early_init_f (void) { #ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO */ - /* 16-bit, no DTACK */ - __REG(CSCR_U(1)) = 0x00000A01; - __REG(CSCR_L(1)) = 0x20040501; - __REG(CSCR_A(1)) = 0x04020C00; + /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ + mx31_setup_weimcs(1, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) + ); /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); @@ -146,50 +149,14 @@ int board_init (void) /* Chip selects */ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ - __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ - (0 << 30) | /* WP */ - (0 << 28) | /* BCD */ - (0 << 24) | /* BCS */ - (0 << 22) | /* PSZ */ - (0 << 21) | /* PME */ - (0 << 20) | /* SYNC */ - (0 << 16) | /* DOL */ - (3 << 14) | /* CNC */ - (21 << 8) | /* WSC */ - (0 << 7) | /* EW */ - (0 << 4) | /* WWS */ - (6 << 0) /* EDC */ - ); - - __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ - (1 << 24) | /* OEN */ - (3 << 20) | /* EBWA */ - (3 << 16) | /* EBWN */ - (1 << 12) | /* CSA */ - (1 << 11) | /* EBC */ - (5 << 8) | /* DSZ */ - (1 << 4) | /* CSN */ - (0 << 3) | /* PSR */ - (0 << 2) | /* CRE */ - (0 << 1) | /* WRAP */ - (1 << 0) /* CSEN */ - ); - - __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ - (1 << 24) | /* EBRN */ - (2 << 20) | /* RWA */ - (2 << 16) | /* RWN */ - (0 << 15) | /* MUM */ - (0 << 13) | /* LAH */ - (2 << 10) | /* LBN */ - (0 << 8) | /* LBA */ - (0 << 6) | /* DWW */ - (0 << 4) | /* DCT */ - (0 << 3) | /* WWU */ - (0 << 2) | /* AGE */ - (0 << 1) | /* CNC2 */ - (0 << 0) /* FCE */ - ); + mx31_setup_weimcs(0, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + ); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; @@ -249,9 +216,15 @@ static void board_nand_setup(void) { /* CS3: NAND 8-bit */ - __REG(CSCR_U(3)) = 0x00004f00; - __REG(CSCR_L(3)) = 0x20013b31; - __REG(CSCR_A(3)) = 0x00020800; + mx31_setup_weimcs(3, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + ); + __REG(IOMUXC_GPR) |= 1 << 13; mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 7637c92..eafb57c 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -22,7 +22,6 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> @@ -54,9 +53,15 @@ int board_early_init_f(void) * the only non-zero field "Wait State Control" is set to half the * default value. */ - __REG(CSCR_U(0)) = 0x00000f00; - __REG(CSCR_L(0)) = 0x10000D03; - __REG(CSCR_A(0)) = 0x00720900; + mx31_setup_weimcs(0, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + ); + /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index f6e190a..3d5e312 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -56,9 +56,14 @@ void dram_init_banksize(void) int board_early_init_f(void) { /* CS5: CPLD incl. network controller */ - __REG(CSCR_U(5)) = 0x0000d843; - __REG(CSCR_L(5)) = 0x22252521; - __REG(CSCR_A(5)) = 0x22220a00; + mx31_setup_weimcs(5, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + ); /* Setup UART1 and SPI2 pins */ mx31_uart1_hw_init(); diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 773900e..f4ad681 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -49,17 +49,35 @@ int board_init(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; - - __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ - __REG(CSCR_L(1)) = 0x444a4541; - __REG(CSCR_A(1)) = 0x44443302; - - __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ - __REG(CSCR_L(4)) = 0x22252521; - __REG(CSCR_A(4)) = 0x22220a00; + /* CS0: Nor Flash */ + mx31_setup_weimcs(0, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + ); + + /* CS1: Network Controller */ + mx31_setup_weimcs(1, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + ); + + /* CS4: SRAM */ + mx31_setup_weimcs(4, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + ); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index 09cc9c5..2805cfe 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -45,13 +45,25 @@ void dram_init_banksize(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0xa0330d01; - __REG(CSCR_A(0)) = 0x00220800; + /* CS0: Nor Flash */ + mx31_setup_weimcs(0, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + ); - __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */ - __REG(CSCR_L(4)) = 0x444a4541; - __REG(CSCR_A(4)) = 0x44443302; + /* CS4: Network Controller */ + mx31_setup_weimcs(4, + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + ); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor 2011-09-28 12:48 ` [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor Helmut Raiger @ 2011-09-28 15:14 ` Stefano Babic 2011-09-29 6:32 ` Helmut Raiger 2011-09-29 7:30 ` Helmut Raiger 2011-09-29 12:19 ` [U-Boot] [PATCH V2] " Helmut Raiger 2011-09-29 12:25 ` [U-Boot] [Resend PATCH V2 (forgot generic.c)] " Helmut Raiger 2 siblings, 2 replies; 45+ messages in thread From: Stefano Babic @ 2011-09-28 15:14 UTC (permalink / raw) To: u-boot On 09/28/2011 02:48 PM, Helmut Raiger wrote: > Some macros are added to support the setup for i.MX31 WEIM > chip selects. As a compromise between verbosity and readability > an ASCII-art'ish bit comment is used instead of bitfields. > All i.MX31 boards have been patched to use this approach using a helper > program to verify the changes. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Hi Helmut, > --- > arch/arm/include/asm/arch-mx31/imx-regs.h | 38 ++++++++++++- > board/davedenx/qong/qong.c | 79 +++++++++------------------ > board/freescale/mx31ads/mx31ads.c | 13 +++-- > board/freescale/mx31pdk/mx31pdk.c | 11 +++- > board/imx31_phycore/imx31_phycore.c | 36 +++++++++--- > board/logicpd/imx31_litekit/imx31_litekit.c | 24 ++++++-- > 6 files changed, 123 insertions(+), 78 deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h > index 2064870..d535830 100644 > --- a/arch/arm/include/asm/arch-mx31/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h > @@ -25,6 +25,7 @@ > #define __ASM_ARCH_MX31_IMX_REGS_H > > #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) > +#include <asm/io.h> > #include <asm/types.h> > > /* Clock control module registers */ > @@ -534,10 +535,41 @@ enum iomux_pins { > #define ESDCTL_BL(x) ((x) << 7) > #define ESDCTL_PRCT(x) ((x) << 0) > > +/* 13 fields of the upper CS control register */ > +#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ > + cnc, wsc, ew, wws, edc) \ > + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ > + (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ > + (wws) << 4 | (edc) << 0) > +/* 12 fields of the lower CS control register */ > +#define CSCR_L(oea, oen, ebwa, ebwn, \ > + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ > + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ > + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ > + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) > +/* 14 fields of the additional CS control register */ > +#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ > + wwu, age, cnc2, fce) \ > + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ > + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ > + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ > + (age) << 2 | (cnc2) << 1 | (fce) << 0) > + > #define WEIM_BASE 0xb8002000 > -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) > -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) > -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) > +#define WEIM_CSCR_U(x) (WEIM_BASE + (x) * 0x10) > +#define WEIM_CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) > +#define WEIM_CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) > + > +#ifndef __ASSEMBLER__ > +static inline void mx31_setup_weimcs(int cs, Is there a reason to embed this function in imx-regs.h ? Why not in ./arch/arm/cpu/arm1136/mx31/generic.c, where I think this function belongs ? We are trying to get consistency among the several i.MX SOCs. For this reason, a general function should not have a specific SOC prefix. You introduce now a new accessor to set up the WEIM registers. We have not yet such as function, but we can have then for other SOCs, too. Rename your function as mxc_setup_weimcs(), and when an accessor will be supplied for MX5 (or MX*), the same name must be used. > + unsigned int upper, unsigned int lower, unsigned int add) > +{ > + writel(upper, WEIM_CSCR_U(cs)); > + writel(lower, WEIM_CSCR_L(cs)); > + writel(add, WEIM_CSCR_A(cs)); > +} You are using offests to access registers. Why not to set a structure as: struct weim_regs { u32 upper; u32 lower; u32 adder; u32 reserved; } and then : struct weim { struct weim_regs cs[6]; }; ...or something like that. Passing the register values to the function makes the accessor too striclty bound to the mx31. But if you pass a struct weim*, that is void mxc_setup_weimcs(struct weim *), we can have the same accessor (with a different implementation, of course) for the other SOCs, too. I can imagine we can have MX5 (at the moment I see only the mx53ard) using the same way to set up the WEIM interface. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor 2011-09-28 15:14 ` Stefano Babic @ 2011-09-29 6:32 ` Helmut Raiger 2011-09-29 6:59 ` Stefano Babic 2011-09-29 7:30 ` Helmut Raiger 1 sibling, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 6:32 UTC (permalink / raw) To: u-boot On 09/28/2011 05:14 PM, Stefano Babic wrote >> Is there a reason to embed this function in imx-regs.h ? Why not in >> ./arch/arm/cpu/arm1136/mx31/generic.c, where I think this function >> belongs ? >> I took it from the kernel where it is done that way and didn't ask why. I'll move it. >> We are trying to get consistency among the several i.MX SOCs. For this >> reason, a general function should not have a specific SOC prefix. >> You introduce now a new accessor to set up the WEIM registers. We have >> not yet such as function, but we can have then for other SOCs, too. >> Rename your function as mxc_setup_weimcs(), and when an accessor will be >> supplied for MX5 (or MX*), the same name must be used. >> >> + unsigned int upper, unsigned int lower, unsigned int add) >> +{ >> + writel(upper, WEIM_CSCR_U(cs)); >> + writel(lower, WEIM_CSCR_L(cs)); >> + writel(add, WEIM_CSCR_A(cs)); >> +} > You are using offests to access registers. Why not to set a structure as: > > struct weim_regs { > u32 upper; > u32 lower; > u32 adder; > u32 reserved; > } > > and then : > > struct weim { > struct weim_regs cs[6]; > }; > > ...or something like that. > > Passing the register values to the function makes the accessor too > striclty bound to the mx31. But if you pass a struct weim*, that is void > mxc_setup_weimcs(struct weim *), we can have the same accessor (with a > different implementation, of course) for the other SOCs, too. I can > imagine we can have MX5 (at the moment I see only the mx53ard) using the > same way to set up the WEIM interface. I used the writel register access to assure correct memory barriers, but this might not be a problem with the CS registers. However passing the complete set of chip selects wouldn't work, as only a few will be setup in the function, while others aren't touched (we could pass a bitmap to select which ones should be set, but this seems flamboyant). What about: void mxc_setup_weimcs(int cs, const struct mxc_weimcs *cs) { ... } void some_board_init_func(void) { /* CS5: CPLD incl. network controller */ static const struct mxc_weimcs cs5 = { /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) }; mxc_setup_weimcs(5, &cs5); } This should still work for different SOCs (with different struct mxc_weimcs). CSCR_U et al. will be mx31 specific defines. Helmut -- Scanned by MailScanner. ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor 2011-09-29 6:32 ` Helmut Raiger @ 2011-09-29 6:59 ` Stefano Babic 0 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-09-29 6:59 UTC (permalink / raw) To: u-boot On 09/29/2011 08:32 AM, Helmut Raiger wrote: > On 09/28/2011 05:14 PM, Stefano Babic wrote >>> Is there a reason to embed this function in imx-regs.h ? Why not in >>> ./arch/arm/cpu/arm1136/mx31/generic.c, where I think this function >>> belongs ? >>> > I took it from the kernel where it is done that way and didn't ask why. > I'll move it. > >>> We are trying to get consistency among the several i.MX SOCs. For this >>> reason, a general function should not have a specific SOC prefix. >>> You introduce now a new accessor to set up the WEIM registers. We have >>> not yet such as function, but we can have then for other SOCs, too. >>> Rename your function as mxc_setup_weimcs(), and when an accessor will be >>> supplied for MX5 (or MX*), the same name must be used. >>> >>> + unsigned int upper, unsigned int lower, unsigned int add) >>> +{ >>> + writel(upper, WEIM_CSCR_U(cs)); >>> + writel(lower, WEIM_CSCR_L(cs)); >>> + writel(add, WEIM_CSCR_A(cs)); >>> +} >> You are using offests to access registers. Why not to set a structure as: >> >> struct weim_regs { >> u32 upper; >> u32 lower; >> u32 adder; >> u32 reserved; >> } >> >> and then : >> >> struct weim { >> struct weim_regs cs[6]; >> }; >> >> ...or something like that. >> >> Passing the register values to the function makes the accessor too >> striclty bound to the mx31. But if you pass a struct weim*, Note: I understand now the misunderstanding. I want to pass a struct weim_regs *, not weim*. > that is void >> mxc_setup_weimcs(struct weim *), we can have the same accessor (with a >> different implementation, of course) for the other SOCs, too. I can >> imagine we can have MX5 (at the moment I see only the mx53ard) using the >> same way to set up the WEIM interface. > > I used the writel register access to assure correct memory barriers, This is ok > but > this might not be a problem with the CS registers. However passing the > complete set of chip selects wouldn't work, This is not what I meant. I want that the function change only one chipselect, not all chipselects in one shot. > as only a few will be setup > in the function, while others aren't touched (we could pass a bitmap to > select which ones should be set, but this seems flamboyant). No bitmap please... > > What about: > > void mxc_setup_weimcs(int cs, const struct mxc_weimcs *cs) > { > ... > } This is what I meant ! Only to check the names: mxc_weimcs is what I described as weim_regs, right ? And this structure can be specified for each SOC. > > void some_board_init_func(void) > { > /* CS5: CPLD incl. network controller */ > static const struct mxc_weimcs cs5 = { > /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ > CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), > /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ > CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), > /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ > CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) > }; > > mxc_setup_weimcs(5, &cs5); Yes, right > } > > This should still work for different SOCs (with different struct > mxc_weimcs). Exactly. > CSCR_U et al. will be mx31 specific defines. This is not a problem - other SOCc have or can have a different layout. It is correct to define these macro into imx-regs.h, as you already did. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor 2011-09-28 15:14 ` Stefano Babic 2011-09-29 6:32 ` Helmut Raiger @ 2011-09-29 7:30 ` Helmut Raiger 2011-09-29 9:17 ` Stefano Babic 1 sibling, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 7:30 UTC (permalink / raw) To: u-boot On 09/28/2011 05:14 PM, Stefano Babic wrote: >> +#ifndef __ASSEMBLER__ >> +static inline void mx31_setup_weimcs(int cs, > Is there a reason to embed this function in imx-regs.h ? Why not in > ./arch/arm/cpu/arm1136/mx31/generic.c, where I think this function > belongs ? > I re-checked, it makes a lot of sense to inline this function as it results into 3 simple register writes (addresses are compile time calculated if 'cs' is a constant)! Helmut -- Scanned by MailScanner. ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor 2011-09-29 7:30 ` Helmut Raiger @ 2011-09-29 9:17 ` Stefano Babic 0 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-09-29 9:17 UTC (permalink / raw) To: u-boot On 09/29/2011 09:30 AM, Helmut Raiger wrote: > On 09/28/2011 05:14 PM, Stefano Babic wrote: >>> +#ifndef __ASSEMBLER__ >>> +static inline void mx31_setup_weimcs(int cs, >> Is there a reason to embed this function in imx-regs.h ? Why not in >> ./arch/arm/cpu/arm1136/mx31/generic.c, where I think this function >> belongs ? >> > > I re-checked, it makes a lot of sense to inline this function as it > results into 3 simple register writes (addresses are compile time > calculated if 'cs' is a constant)! Well, this is correct, but I wonder if this is the right function to be optimized. I cannot imagine that this function runs a lot of times. It is used to initialize the chipselects, and it is normally called not more as one time for each chip select, or less. For the i.MX31, not more as 6 times. What I am trying in any case to avoid is that the code becomes messy. And I am trying to have the code as consistent as possible among the several i.MX SOCs. The i.MX31 is the older, and only part of code was cleaned up. You see for example a lot of accesses using the __REG macro inside the i.MX31 code, and this is not accepted for new code.So there are some "unwritten" rules, that can be acquired reading the code for the i.MX processors. - each i.MX SOC has a imx-regs.h file, where the registers and the layout of the SOC is described. Neither functions nor prototypes must be inserted here. - for clock related defines, a crm_regs.h file is defined - common prototypes are put in sys_proto.h (same name as other ARM SOCs, see OMAP/TI/s5p). So please do not put inline functions inside imx-regs.h, and feel free to add a sys_proto.h (check for the same file for MX35/MX5) for your purposes. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2] mx31: provide readable WEIM CS accessor 2011-09-28 12:48 ` [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor Helmut Raiger 2011-09-28 15:14 ` Stefano Babic @ 2011-09-29 12:19 ` Helmut Raiger 2011-09-29 12:25 ` [U-Boot] [Resend PATCH V2 (forgot generic.c)] " Helmut Raiger 2 siblings, 0 replies; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 12:19 UTC (permalink / raw) To: u-boot mxc_setup_weimcs() and some macros are added to support the setup for i.MX31 WEIM chip selects. As a compromise between verbosity and readability an ASCII-art'ish bit comment is used instead of bitfields. All i.MX31 boards have been patched to use this approach using a helper program to verify the changes. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: added sys_proto.h for mx31 introduced mxc_setup_weimcs(), which is SOC independent not inlined any more (codesize increased by 60-90 bytes) --- arch/arm/include/asm/arch-mx31/imx-regs.h | 26 +++++++- arch/arm/include/asm/arch-mx31/sys_proto.h | 35 +++++++++++ board/davedenx/qong/qong.c | 87 ++++++++++----------------- board/freescale/mx31ads/mx31ads.c | 15 ++++- board/freescale/mx31pdk/mx31pdk.c | 14 ++++- board/imx31_phycore/imx31_phycore.c | 41 ++++++++++--- board/logicpd/imx31_litekit/imx31_litekit.c | 28 +++++++-- 7 files changed, 167 insertions(+), 79 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx31/sys_proto.h diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 2064870..d631a10 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -534,10 +534,30 @@ enum iomux_pins { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +/* 13 fields of the upper CS control register */ +#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ + (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ + (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + #define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +#define WEIM_CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define WEIM_CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define WEIM_CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) #define IOMUXC_BASE 0x43FAC000 #define IOMUXC_GPR (IOMUXC_BASE + 0x8) diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h new file mode 100644 index 0000000..7600303 --- /dev/null +++ b/arch/arm/include/asm/arch-mx31/sys_proto.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2011 + * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +struct mxc_weimcs { + u32 upper; + u32 lower; + u32 additional; +}; + +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); + +#endif diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 99432ed..b9133bc 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -25,7 +25,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <asm/io.h> +#include <asm/arch/sys_proto.h> #include <nand.h> #include <fsl_pmic.h> #include <asm/gpio.h> @@ -61,11 +61,17 @@ static void qong_fpga_reset(void) int board_early_init_f (void) { #ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO */ - /* 16-bit, no DTACK */ - __REG(CSCR_U(1)) = 0x00000A01; - __REG(CSCR_L(1)) = 0x20040501; - __REG(CSCR_A(1)) = 0x04020C00; + /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(1, &cs1); /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); @@ -146,50 +152,16 @@ int board_init (void) /* Chip selects */ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ - __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ - (0 << 30) | /* WP */ - (0 << 28) | /* BCD */ - (0 << 24) | /* BCS */ - (0 << 22) | /* PSZ */ - (0 << 21) | /* PME */ - (0 << 20) | /* SYNC */ - (0 << 16) | /* DOL */ - (3 << 14) | /* CNC */ - (21 << 8) | /* WSC */ - (0 << 7) | /* EW */ - (0 << 4) | /* WWS */ - (6 << 0) /* EDC */ - ); - - __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ - (1 << 24) | /* OEN */ - (3 << 20) | /* EBWA */ - (3 << 16) | /* EBWN */ - (1 << 12) | /* CSA */ - (1 << 11) | /* EBC */ - (5 << 8) | /* DSZ */ - (1 << 4) | /* CSN */ - (0 << 3) | /* PSR */ - (0 << 2) | /* CRE */ - (0 << 1) | /* WRAP */ - (1 << 0) /* CSEN */ - ); - - __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ - (1 << 24) | /* EBRN */ - (2 << 20) | /* RWA */ - (2 << 16) | /* RWN */ - (0 << 15) | /* MUM */ - (0 << 13) | /* LAH */ - (2 << 10) | /* LBN */ - (0 << 8) | /* LBA */ - (0 << 6) | /* DWW */ - (0 << 4) | /* DCT */ - (0 << 3) | /* WWU */ - (0 << 2) | /* AGE */ - (0 << 1) | /* CNC2 */ - (0 << 0) /* FCE */ - ); + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; @@ -247,11 +219,18 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) static void board_nand_setup(void) { - /* CS3: NAND 8-bit */ - __REG(CSCR_U(3)) = 0x00004f00; - __REG(CSCR_L(3)) = 0x20013b31; - __REG(CSCR_A(3)) = 0x00020800; + static const struct mxc_weimcs cs3 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(3, &cs3); + __REG(IOMUXC_GPR) |= 1 << 13; mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 7637c92..6cf3a8a 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -22,9 +22,9 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -54,9 +54,16 @@ int board_early_init_f(void) * the only non-zero field "Wait State Control" is set to half the * default value. */ - __REG(CSCR_U(0)) = 0x00000f00; - __REG(CSCR_L(0)) = 0x10000D03; - __REG(CSCR_A(0)) = 0x00720900; + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index f6e190a..1bcf1fb 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -28,6 +28,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,9 +57,16 @@ void dram_init_banksize(void) int board_early_init_f(void) { /* CS5: CPLD incl. network controller */ - __REG(CSCR_U(5)) = 0x0000d843; - __REG(CSCR_L(5)) = 0x22252521; - __REG(CSCR_A(5)) = 0x22220a00; + static const struct mxc_weimcs cs5 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(5, &cs5); /* Setup UART1 and SPI2 pins */ mx31_uart1_hw_init(); diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 773900e..a697e47 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -49,17 +50,39 @@ int board_init(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + /* CS1: Network Controller */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; - __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ - __REG(CSCR_L(1)) = 0x444a4541; - __REG(CSCR_A(1)) = 0x44443302; + /* CS4: SRAM */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ - __REG(CSCR_L(4)) = 0x22252521; - __REG(CSCR_A(4)) = 0x22220a00; + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(1, &cs1); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index 09cc9c5..0615215 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -26,6 +26,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,13 +46,28 @@ void dram_init_banksize(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0xa0330d01; - __REG(CSCR_A(0)) = 0x00220800; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */ - __REG(CSCR_L(4)) = 0x444a4541; - __REG(CSCR_A(4)) = 0x44443302; + /* CS4: Network Controller */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V2 (forgot generic.c)] mx31: provide readable WEIM CS accessor 2011-09-28 12:48 ` [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor Helmut Raiger 2011-09-28 15:14 ` Stefano Babic 2011-09-29 12:19 ` [U-Boot] [PATCH V2] " Helmut Raiger @ 2011-09-29 12:25 ` Helmut Raiger 2011-09-29 13:21 ` Stefano Babic 2 siblings, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 12:25 UTC (permalink / raw) To: u-boot setup_weimcs() and some macros are added to support the setup for i.MX31 WEIM chip selects. As a compromise between verbosity and readability an ASCII-art'ish bit comment is used instead of bitfields. All i.MX31 boards have been patched to use this approach using a helper program to verify the changes. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: added sys_proto.h for mx31 introduced mxc_setup_weimcs(), which is SOC independent not inlined any more (codesize increased by 60-90 bytes) --- arch/arm/cpu/arm1136/mx31/generic.c | 9 +++ arch/arm/include/asm/arch-mx31/imx-regs.h | 26 +++++++- arch/arm/include/asm/arch-mx31/sys_proto.h | 35 +++++++++++ board/davedenx/qong/qong.c | 87 ++++++++++----------------- board/freescale/mx31ads/mx31ads.c | 15 ++++- board/freescale/mx31pdk/mx31pdk.c | 14 ++++- board/imx31_phycore/imx31_phycore.c | 41 ++++++++++--- board/logicpd/imx31_litekit/imx31_litekit.c | 28 +++++++-- 8 files changed, 176 insertions(+), 79 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx31/sys_proto.h diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index e3a4d1b..29af156 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -25,6 +25,8 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/io.h> +#include <asm/arch/sys_proto.h> + static u32 mx31_decode_pll(u32 reg, u32 infreq) { @@ -126,6 +128,13 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) +{ + writel(weimcs->upper, WEIM_CSCR_U(cs)); + writel(weimcs->lower, WEIM_CSCR_L(cs)); + writel(weimcs->additional, WEIM_CSCR_A(cs)); +} + struct mx3_cpu_type mx31_cpu_type[] = { { .srev = 0x00, .v = 0x10 }, { .srev = 0x10, .v = 0x11 }, diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 2064870..d631a10 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -534,10 +534,30 @@ enum iomux_pins { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +/* 13 fields of the upper CS control register */ +#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ + (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ + (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + #define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) +#define WEIM_CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define WEIM_CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define WEIM_CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) #define IOMUXC_BASE 0x43FAC000 #define IOMUXC_GPR (IOMUXC_BASE + 0x8) diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h new file mode 100644 index 0000000..7600303 --- /dev/null +++ b/arch/arm/include/asm/arch-mx31/sys_proto.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2011 + * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +struct mxc_weimcs { + u32 upper; + u32 lower; + u32 additional; +}; + +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); + +#endif diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 99432ed..b9133bc 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -25,7 +25,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <asm/io.h> +#include <asm/arch/sys_proto.h> #include <nand.h> #include <fsl_pmic.h> #include <asm/gpio.h> @@ -61,11 +61,17 @@ static void qong_fpga_reset(void) int board_early_init_f (void) { #ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO */ - /* 16-bit, no DTACK */ - __REG(CSCR_U(1)) = 0x00000A01; - __REG(CSCR_L(1)) = 0x20040501; - __REG(CSCR_A(1)) = 0x04020C00; + /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(1, &cs1); /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); @@ -146,50 +152,16 @@ int board_init (void) /* Chip selects */ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ - __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ - (0 << 30) | /* WP */ - (0 << 28) | /* BCD */ - (0 << 24) | /* BCS */ - (0 << 22) | /* PSZ */ - (0 << 21) | /* PME */ - (0 << 20) | /* SYNC */ - (0 << 16) | /* DOL */ - (3 << 14) | /* CNC */ - (21 << 8) | /* WSC */ - (0 << 7) | /* EW */ - (0 << 4) | /* WWS */ - (6 << 0) /* EDC */ - ); - - __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ - (1 << 24) | /* OEN */ - (3 << 20) | /* EBWA */ - (3 << 16) | /* EBWN */ - (1 << 12) | /* CSA */ - (1 << 11) | /* EBC */ - (5 << 8) | /* DSZ */ - (1 << 4) | /* CSN */ - (0 << 3) | /* PSR */ - (0 << 2) | /* CRE */ - (0 << 1) | /* WRAP */ - (1 << 0) /* CSEN */ - ); - - __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ - (1 << 24) | /* EBRN */ - (2 << 20) | /* RWA */ - (2 << 16) | /* RWN */ - (0 << 15) | /* MUM */ - (0 << 13) | /* LAH */ - (2 << 10) | /* LBN */ - (0 << 8) | /* LBA */ - (0 << 6) | /* DWW */ - (0 << 4) | /* DCT */ - (0 << 3) | /* WWU */ - (0 << 2) | /* AGE */ - (0 << 1) | /* CNC2 */ - (0 << 0) /* FCE */ - ); + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; @@ -247,11 +219,18 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) static void board_nand_setup(void) { - /* CS3: NAND 8-bit */ - __REG(CSCR_U(3)) = 0x00004f00; - __REG(CSCR_L(3)) = 0x20013b31; - __REG(CSCR_A(3)) = 0x00020800; + static const struct mxc_weimcs cs3 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(3, &cs3); + __REG(IOMUXC_GPR) |= 1 << 13; mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 7637c92..6cf3a8a 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -22,9 +22,9 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -54,9 +54,16 @@ int board_early_init_f(void) * the only non-zero field "Wait State Control" is set to half the * default value. */ - __REG(CSCR_U(0)) = 0x00000f00; - __REG(CSCR_L(0)) = 0x10000D03; - __REG(CSCR_A(0)) = 0x00720900; + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index f6e190a..1bcf1fb 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -28,6 +28,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,9 +57,16 @@ void dram_init_banksize(void) int board_early_init_f(void) { /* CS5: CPLD incl. network controller */ - __REG(CSCR_U(5)) = 0x0000d843; - __REG(CSCR_L(5)) = 0x22252521; - __REG(CSCR_A(5)) = 0x22220a00; + static const struct mxc_weimcs cs5 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(5, &cs5); /* Setup UART1 and SPI2 pins */ mx31_uart1_hw_init(); diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 773900e..a697e47 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -49,17 +50,39 @@ int board_init(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + /* CS1: Network Controller */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; - __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ - __REG(CSCR_L(1)) = 0x444a4541; - __REG(CSCR_A(1)) = 0x44443302; + /* CS4: SRAM */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ - __REG(CSCR_L(4)) = 0x22252521; - __REG(CSCR_A(4)) = 0x22220a00; + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(1, &cs1); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index 09cc9c5..0615215 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -26,6 +26,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,13 +46,28 @@ void dram_init_banksize(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0xa0330d01; - __REG(CSCR_A(0)) = 0x00220800; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */ - __REG(CSCR_L(4)) = 0x444a4541; - __REG(CSCR_A(4)) = 0x44443302; + /* CS4: Network Controller */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V2 (forgot generic.c)] mx31: provide readable WEIM CS accessor 2011-09-29 12:25 ` [U-Boot] [Resend PATCH V2 (forgot generic.c)] " Helmut Raiger @ 2011-09-29 13:21 ` Stefano Babic 2011-09-29 14:01 ` Helmut Raiger 0 siblings, 1 reply; 45+ messages in thread From: Stefano Babic @ 2011-09-29 13:21 UTC (permalink / raw) To: u-boot On 09/29/2011 02:25 PM, Helmut Raiger wrote: > setup_weimcs() and some macros are added to support the setup > for i.MX31 WEIM chip selects. As a compromise between verbosity > and readability an ASCII-art'ish bit comment is used instead of > bitfields. > All i.MX31 boards have been patched to use this approach using a > helper program to verify the changes. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: > added sys_proto.h for mx31 > introduced mxc_setup_weimcs(), which is SOC independent > not inlined any more (codesize increased by 60-90 bytes) > --- > arch/arm/cpu/arm1136/mx31/generic.c | 9 +++ Ah, ok, I now I can find the implementation ;-) I have only a couple of open points... > arch/arm/include/asm/arch-mx31/imx-regs.h | 26 +++++++- > arch/arm/include/asm/arch-mx31/sys_proto.h | 35 +++++++++++ > board/davedenx/qong/qong.c | 87 ++++++++++----------------- > board/freescale/mx31ads/mx31ads.c | 15 ++++- > board/freescale/mx31pdk/mx31pdk.c | 14 ++++- > board/imx31_phycore/imx31_phycore.c | 41 ++++++++++--- > board/logicpd/imx31_litekit/imx31_litekit.c | 28 +++++++-- > 8 files changed, 176 insertions(+), 79 deletions(-) > create mode 100644 arch/arm/include/asm/arch-mx31/sys_proto.h > > diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c > index e3a4d1b..29af156 100644 > --- a/arch/arm/cpu/arm1136/mx31/generic.c > +++ b/arch/arm/cpu/arm1136/mx31/generic.c > @@ -25,6 +25,8 @@ > #include <asm/arch/imx-regs.h> > #include <asm/arch/clock.h> > #include <asm/io.h> > +#include <asm/arch/sys_proto.h> > + Drop newline > > static u32 mx31_decode_pll(u32 reg, u32 infreq) > { > @@ -126,6 +128,13 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) > > } > > +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) > +{ > + writel(weimcs->upper, WEIM_CSCR_U(cs)); > + writel(weimcs->lower, WEIM_CSCR_L(cs)); > + writel(weimcs->additional, WEIM_CSCR_A(cs)); > +} Even if more hidden, the access is always made with base + offset, instead of defining a structure. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V2 (forgot generic.c)] mx31: provide readable WEIM CS accessor 2011-09-29 13:21 ` Stefano Babic @ 2011-09-29 14:01 ` Helmut Raiger 2011-09-29 14:16 ` Stefano Babic 2011-09-29 17:32 ` [U-Boot] [Resend PATCH V2 (forgot generic.c)] " Wolfgang Denk 0 siblings, 2 replies; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 14:01 UTC (permalink / raw) To: u-boot On 09/29/2011 03:21 PM, Stefano Babic wrote: > >> >> static u32 mx31_decode_pll(u32 reg, u32 infreq) >> { >> @@ -126,6 +128,13 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) >> >> } >> >> +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) >> +{ >> + writel(weimcs->upper, WEIM_CSCR_U(cs)); >> + writel(weimcs->lower, WEIM_CSCR_L(cs)); >> + writel(weimcs->additional, WEIM_CSCR_A(cs)); >> +} > Even if more hidden, the access is always made with base + offset, > instead of defining a structure. > Do you really thing this is more readable: ------------ in imx_regs.h ----------- struct mx31_weim_cscr { u32 upper; u32 lower; u32 additional; u32 reserved; }; struct mx31_weim { struct mx31_weim_cscr cscr[6]; }; -------------- in generic.c -------------- void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) { struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE; struct mx31_weim_cscr *cscr = &weim->cscr[cs]; writel(weimcs->upper, &cscr->upper); writel(weimcs->lower, &cscr->lower); writel(weimcs->additional, &cscr->additional); } It seems pretty clumsy to me, but for sure a matter of taste. Helmut -- Scanned by MailScanner. ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V2 (forgot generic.c)] mx31: provide readable WEIM CS accessor 2011-09-29 14:01 ` Helmut Raiger @ 2011-09-29 14:16 ` Stefano Babic 2011-09-29 14:55 ` [U-Boot] [PATCH V3] " Helmut Raiger 2011-09-29 15:45 ` [U-Boot] [Resend PATCH " Helmut Raiger 2011-09-29 17:32 ` [U-Boot] [Resend PATCH V2 (forgot generic.c)] " Wolfgang Denk 1 sibling, 2 replies; 45+ messages in thread From: Stefano Babic @ 2011-09-29 14:16 UTC (permalink / raw) To: u-boot On 09/29/2011 04:01 PM, Helmut Raiger wrote: > On 09/29/2011 03:21 PM, Stefano Babic wrote: >> >>> >>> static u32 mx31_decode_pll(u32 reg, u32 infreq) >>> { >>> @@ -126,6 +128,13 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) >>> >>> } >>> >>> +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) >>> +{ >>> + writel(weimcs->upper, WEIM_CSCR_U(cs)); >>> + writel(weimcs->lower, WEIM_CSCR_L(cs)); >>> + writel(weimcs->additional, WEIM_CSCR_A(cs)); >>> +} >> Even if more hidden, the access is always made with base + offset, >> instead of defining a structure. >> > > Do you really thing this is more readable: > > ------------ in imx_regs.h ----------- > > struct mx31_weim_cscr { > u32 upper; > u32 lower; > u32 additional; > u32 reserved; > }; > > struct mx31_weim { > struct mx31_weim_cscr cscr[6]; > }; > > -------------- in generic.c -------------- > > void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) > { > struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE; > struct mx31_weim_cscr *cscr = &weim->cscr[cs]; > > writel(weimcs->upper, &cscr->upper); > writel(weimcs->lower, &cscr->lower); > writel(weimcs->additional, &cscr->additional); > } > > > It seems pretty clumsy to me, but for sure a matter of taste. > Helmut Check in the ML and also in code - more as a question of taste, this is a coding style rule in u-boot. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3] mx31: provide readable WEIM CS accessor 2011-09-29 14:16 ` Stefano Babic @ 2011-09-29 14:55 ` Helmut Raiger 2011-09-29 15:11 ` Helmut Raiger 2011-09-29 15:45 ` [U-Boot] [Resend PATCH " Helmut Raiger 1 sibling, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 14:55 UTC (permalink / raw) To: u-boot setup_weimcs() and some macros are added to support the setup for i.MX31 WEIM chip selects. As a compromise between verbosity and readability an ASCII-art'ish bit comment is used instead of bitfields. All i.MX31 boards have been patched to use this approach using a helper program to verify the changes. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: added sys_proto.h for mx31 introduced mxc_setup_weimcs(), which is SOC independent not inlined any more (codesize increased by 60-90 bytes) V3: modified register access according to the coding style --- arch/arm/cpu/arm1136/mx31/generic.c | 9 +++ arch/arm/include/asm/arch-mx31/imx-regs.h | 35 ++++++++++- arch/arm/include/asm/arch-mx31/sys_proto.h | 35 +++++++++++ board/davedenx/qong/qong.c | 87 ++++++++++----------------- board/freescale/mx31ads/mx31ads.c | 15 ++++- board/freescale/mx31pdk/mx31pdk.c | 14 ++++- board/imx31_phycore/imx31_phycore.c | 41 ++++++++++--- board/logicpd/imx31_litekit/imx31_litekit.c | 28 +++++++-- 8 files changed, 185 insertions(+), 79 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx31/sys_proto.h diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index e3a4d1b..29af156 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -25,6 +25,8 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/io.h> +#include <asm/arch/sys_proto.h> + static u32 mx31_decode_pll(u32 reg, u32 infreq) { @@ -126,6 +128,13 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) +{ + writel(weimcs->upper, WEIM_CSCR_U(cs)); + writel(weimcs->lower, WEIM_CSCR_L(cs)); + writel(weimcs->additional, WEIM_CSCR_A(cs)); +} + struct mx3_cpu_type mx31_cpu_type[] = { { .srev = 0x00, .v = 0x10 }, { .srev = 0x10, .v = 0x11 }, diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 2064870..02b471f 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -470,6 +470,18 @@ enum iomux_pins { #define CCM_RCSR_NF16B (1 << 31) #define CCM_RCSR_NFMS (1 << 30) +/* WEIM CS control registers */ +struct mx31_weim_cscr { + u32 upper; + u32 lower; + u32 additional; + u32 reserved; +}; + +struct mx31_weim { + struct mx31_weim_cscr cscr[6]; +}; + #endif #define __REG(x) (*((volatile u32 *)(x))) @@ -534,10 +546,27 @@ enum iomux_pins { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +/* 13 fields of the upper CS control register */ +#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ + (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ + (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + #define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) #define IOMUXC_BASE 0x43FAC000 #define IOMUXC_GPR (IOMUXC_BASE + 0x8) diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h new file mode 100644 index 0000000..7600303 --- /dev/null +++ b/arch/arm/include/asm/arch-mx31/sys_proto.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2011 + * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +struct mxc_weimcs { + u32 upper; + u32 lower; + u32 additional; +}; + +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); + +#endif diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 99432ed..b9133bc 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -25,7 +25,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <asm/io.h> +#include <asm/arch/sys_proto.h> #include <nand.h> #include <fsl_pmic.h> #include <asm/gpio.h> @@ -61,11 +61,17 @@ static void qong_fpga_reset(void) int board_early_init_f (void) { #ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO */ - /* 16-bit, no DTACK */ - __REG(CSCR_U(1)) = 0x00000A01; - __REG(CSCR_L(1)) = 0x20040501; - __REG(CSCR_A(1)) = 0x04020C00; + /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(1, &cs1); /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); @@ -146,50 +152,16 @@ int board_init (void) /* Chip selects */ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ - __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ - (0 << 30) | /* WP */ - (0 << 28) | /* BCD */ - (0 << 24) | /* BCS */ - (0 << 22) | /* PSZ */ - (0 << 21) | /* PME */ - (0 << 20) | /* SYNC */ - (0 << 16) | /* DOL */ - (3 << 14) | /* CNC */ - (21 << 8) | /* WSC */ - (0 << 7) | /* EW */ - (0 << 4) | /* WWS */ - (6 << 0) /* EDC */ - ); - - __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ - (1 << 24) | /* OEN */ - (3 << 20) | /* EBWA */ - (3 << 16) | /* EBWN */ - (1 << 12) | /* CSA */ - (1 << 11) | /* EBC */ - (5 << 8) | /* DSZ */ - (1 << 4) | /* CSN */ - (0 << 3) | /* PSR */ - (0 << 2) | /* CRE */ - (0 << 1) | /* WRAP */ - (1 << 0) /* CSEN */ - ); - - __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ - (1 << 24) | /* EBRN */ - (2 << 20) | /* RWA */ - (2 << 16) | /* RWN */ - (0 << 15) | /* MUM */ - (0 << 13) | /* LAH */ - (2 << 10) | /* LBN */ - (0 << 8) | /* LBA */ - (0 << 6) | /* DWW */ - (0 << 4) | /* DCT */ - (0 << 3) | /* WWU */ - (0 << 2) | /* AGE */ - (0 << 1) | /* CNC2 */ - (0 << 0) /* FCE */ - ); + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; @@ -247,11 +219,18 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) static void board_nand_setup(void) { - /* CS3: NAND 8-bit */ - __REG(CSCR_U(3)) = 0x00004f00; - __REG(CSCR_L(3)) = 0x20013b31; - __REG(CSCR_A(3)) = 0x00020800; + static const struct mxc_weimcs cs3 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(3, &cs3); + __REG(IOMUXC_GPR) |= 1 << 13; mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 7637c92..6cf3a8a 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -22,9 +22,9 @@ #include <common.h> #include <netdev.h> -#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -54,9 +54,16 @@ int board_early_init_f(void) * the only non-zero field "Wait State Control" is set to half the * default value. */ - __REG(CSCR_U(0)) = 0x00000f00; - __REG(CSCR_L(0)) = 0x10000D03; - __REG(CSCR_A(0)) = 0x00720900; + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index f6e190a..1bcf1fb 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -28,6 +28,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,9 +57,16 @@ void dram_init_banksize(void) int board_early_init_f(void) { /* CS5: CPLD incl. network controller */ - __REG(CSCR_U(5)) = 0x0000d843; - __REG(CSCR_L(5)) = 0x22252521; - __REG(CSCR_A(5)) = 0x22220a00; + static const struct mxc_weimcs cs5 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(5, &cs5); /* Setup UART1 and SPI2 pins */ mx31_uart1_hw_init(); diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 773900e..a697e47 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -49,17 +50,39 @@ int board_init(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + /* CS1: Network Controller */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; - __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ - __REG(CSCR_L(1)) = 0x444a4541; - __REG(CSCR_A(1)) = 0x44443302; + /* CS4: SRAM */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ - __REG(CSCR_L(4)) = 0x22252521; - __REG(CSCR_A(4)) = 0x22220a00; + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(1, &cs1); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index 09cc9c5..0615215 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -26,6 +26,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,13 +46,28 @@ void dram_init_banksize(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0xa0330d01; - __REG(CSCR_A(0)) = 0x00220800; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */ - __REG(CSCR_L(4)) = 0x444a4541; - __REG(CSCR_A(4)) = 0x44443302; + /* CS4: Network Controller */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3] mx31: provide readable WEIM CS accessor 2011-09-29 14:55 ` [U-Boot] [PATCH V3] " Helmut Raiger @ 2011-09-29 15:11 ` Helmut Raiger 2011-09-29 15:19 ` Stefano Babic 0 siblings, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 15:11 UTC (permalink / raw) To: u-boot forget the patch, I'll resend. ... clearly a matter of under caffeination. Helmut -- Scanned by MailScanner. ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3] mx31: provide readable WEIM CS accessor 2011-09-29 15:11 ` Helmut Raiger @ 2011-09-29 15:19 ` Stefano Babic 0 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-09-29 15:19 UTC (permalink / raw) To: u-boot On 09/29/2011 05:11 PM, Helmut Raiger wrote: > > forget the patch, I'll resend. > > ... clearly a matter of under caffeination. > Do not worry, I have the same problem... Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V3] mx31: provide readable WEIM CS accessor 2011-09-29 14:16 ` Stefano Babic 2011-09-29 14:55 ` [U-Boot] [PATCH V3] " Helmut Raiger @ 2011-09-29 15:45 ` Helmut Raiger 2011-09-30 7:32 ` Stefano Babic 2011-10-05 11:51 ` Stefano Babic 1 sibling, 2 replies; 45+ messages in thread From: Helmut Raiger @ 2011-09-29 15:45 UTC (permalink / raw) To: u-boot setup_weimcs() and some macros are added to support the setup for i.MX31 WEIM chip selects. As a compromise between verbosity and readability an ASCII-art'ish bit comment is used instead of bitfields. All i.MX31 boards have been patched to use this approach using a helper program to verify the changes. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: added sys_proto.h for mx31 introduced mxc_setup_weimcs(), which is SOC independent not inlined any more (codesize increased by 60-90 bytes) V3: modified register access according to the coding style --- arch/arm/cpu/arm1136/mx31/generic.c | 11 ++++ arch/arm/include/asm/arch-mx31/imx-regs.h | 35 ++++++++++- arch/arm/include/asm/arch-mx31/sys_proto.h | 35 +++++++++++ board/davedenx/qong/qong.c | 86 ++++++++++---------------- board/freescale/mx31ads/mx31ads.c | 14 ++++- board/freescale/mx31pdk/mx31pdk.c | 14 ++++- board/imx31_phycore/imx31_phycore.c | 41 ++++++++++--- board/logicpd/imx31_litekit/imx31_litekit.c | 28 +++++++-- 8 files changed, 187 insertions(+), 77 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx31/sys_proto.h diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index e3a4d1b..32e8f23 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -25,6 +25,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/io.h> +#include <asm/arch/sys_proto.h> static u32 mx31_decode_pll(u32 reg, u32 infreq) { @@ -126,6 +127,16 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) +{ + struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE; + struct mx31_weim_cscr *cscr = &weim->cscr[cs]; + + writel(weimcs->upper, &cscr->upper); + writel(weimcs->lower, &cscr->lower); + writel(weimcs->additional, &cscr->additional); +} + struct mx3_cpu_type mx31_cpu_type[] = { { .srev = 0x00, .v = 0x10 }, { .srev = 0x10, .v = 0x11 }, diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 2064870..02b471f 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -470,6 +470,18 @@ enum iomux_pins { #define CCM_RCSR_NF16B (1 << 31) #define CCM_RCSR_NFMS (1 << 30) +/* WEIM CS control registers */ +struct mx31_weim_cscr { + u32 upper; + u32 lower; + u32 additional; + u32 reserved; +}; + +struct mx31_weim { + struct mx31_weim_cscr cscr[6]; +}; + #endif #define __REG(x) (*((volatile u32 *)(x))) @@ -534,10 +546,27 @@ enum iomux_pins { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +/* 13 fields of the upper CS control register */ +#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ + cnc, wsc, ew, wws, edc) \ + ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ + (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ + (wws) << 4 | (edc) << 0) +/* 12 fields of the lower CS control register */ +#define CSCR_L(oea, oen, ebwa, ebwn, \ + csa, ebc, dsz, csn, psr, cre, wrap, csen) \ + ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ + (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ + (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) +/* 14 fields of the additional CS control register */ +#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ + wwu, age, cnc2, fce) \ + ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ + (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ + (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ + (age) << 2 | (cnc2) << 1 | (fce) << 0) + #define WEIM_BASE 0xb8002000 -#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) -#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) -#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) #define IOMUXC_BASE 0x43FAC000 #define IOMUXC_GPR (IOMUXC_BASE + 0x8) diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h new file mode 100644 index 0000000..7600303 --- /dev/null +++ b/arch/arm/include/asm/arch-mx31/sys_proto.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2011 + * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +struct mxc_weimcs { + u32 upper; + u32 lower; + u32 additional; +}; + +void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); + +#endif diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 99432ed..9fca1f8 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -25,6 +25,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> #include <nand.h> #include <fsl_pmic.h> @@ -61,11 +62,17 @@ static void qong_fpga_reset(void) int board_early_init_f (void) { #ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO */ - /* 16-bit, no DTACK */ - __REG(CSCR_U(1)) = 0x00000A01; - __REG(CSCR_L(1)) = 0x20040501; - __REG(CSCR_A(1)) = 0x04020C00; + /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(1, &cs1); /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); @@ -146,50 +153,16 @@ int board_init (void) /* Chip selects */ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ - __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ - (0 << 30) | /* WP */ - (0 << 28) | /* BCD */ - (0 << 24) | /* BCS */ - (0 << 22) | /* PSZ */ - (0 << 21) | /* PME */ - (0 << 20) | /* SYNC */ - (0 << 16) | /* DOL */ - (3 << 14) | /* CNC */ - (21 << 8) | /* WSC */ - (0 << 7) | /* EW */ - (0 << 4) | /* WWS */ - (6 << 0) /* EDC */ - ); - - __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ - (1 << 24) | /* OEN */ - (3 << 20) | /* EBWA */ - (3 << 16) | /* EBWN */ - (1 << 12) | /* CSA */ - (1 << 11) | /* EBC */ - (5 << 8) | /* DSZ */ - (1 << 4) | /* CSN */ - (0 << 3) | /* PSR */ - (0 << 2) | /* CRE */ - (0 << 1) | /* WRAP */ - (1 << 0) /* CSEN */ - ); - - __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ - (1 << 24) | /* EBRN */ - (2 << 20) | /* RWA */ - (2 << 16) | /* RWN */ - (0 << 15) | /* MUM */ - (0 << 13) | /* LAH */ - (2 << 10) | /* LBN */ - (0 << 8) | /* LBA */ - (0 << 6) | /* DWW */ - (0 << 4) | /* DCT */ - (0 << 3) | /* WWU */ - (0 << 2) | /* AGE */ - (0 << 1) | /* CNC2 */ - (0 << 0) /* FCE */ - ); + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; @@ -247,11 +220,18 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) static void board_nand_setup(void) { - /* CS3: NAND 8-bit */ - __REG(CSCR_U(3)) = 0x00004f00; - __REG(CSCR_L(3)) = 0x20013b31; - __REG(CSCR_A(3)) = 0x00020800; + static const struct mxc_weimcs cs3 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(3, &cs3); + __REG(IOMUXC_GPR) |= 1 << 13; mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 7637c92..1f3d570 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -54,9 +55,16 @@ int board_early_init_f(void) * the only non-zero field "Wait State Control" is set to half the * default value. */ - __REG(CSCR_U(0)) = 0x00000f00; - __REG(CSCR_L(0)) = 0x10000D03; - __REG(CSCR_A(0)) = 0x00720900; + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index f6e190a..1bcf1fb 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -28,6 +28,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,9 +57,16 @@ void dram_init_banksize(void) int board_early_init_f(void) { /* CS5: CPLD incl. network controller */ - __REG(CSCR_U(5)) = 0x0000d843; - __REG(CSCR_L(5)) = 0x22252521; - __REG(CSCR_A(5)) = 0x22220a00; + static const struct mxc_weimcs cs5 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(5, &cs5); /* Setup UART1 and SPI2 pins */ mx31_uart1_hw_init(); diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 773900e..a697e47 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -49,17 +50,39 @@ int board_init(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0x10000d03; - __REG(CSCR_A(0)) = 0x00720900; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + /* CS1: Network Controller */ + static const struct mxc_weimcs cs1 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; - __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ - __REG(CSCR_L(1)) = 0x444a4541; - __REG(CSCR_A(1)) = 0x44443302; + /* CS4: SRAM */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ - __REG(CSCR_L(4)) = 0x22252521; - __REG(CSCR_A(4)) = 0x22220a00; + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(1, &cs1); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index 09cc9c5..0615215 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -26,6 +26,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,13 +46,28 @@ void dram_init_banksize(void) int board_early_init_f(void) { - __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ - __REG(CSCR_L(0)) = 0xa0330d01; - __REG(CSCR_A(0)) = 0x00220800; + /* CS0: Nor Flash */ + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0) + }; - __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */ - __REG(CSCR_L(4)) = 0x444a4541; - __REG(CSCR_A(4)) = 0x44443302; + /* CS4: Network Controller */ + static const struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + mxc_setup_weimcs(0, &cs0); + mxc_setup_weimcs(4, &cs4); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V3] mx31: provide readable WEIM CS accessor 2011-09-29 15:45 ` [U-Boot] [Resend PATCH " Helmut Raiger @ 2011-09-30 7:32 ` Stefano Babic 2011-10-05 11:51 ` Stefano Babic 1 sibling, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-09-30 7:32 UTC (permalink / raw) To: u-boot On 09/29/2011 05:45 PM, Helmut Raiger wrote: > setup_weimcs() and some macros are added to support the setup > for i.MX31 WEIM chip selects. As a compromise between verbosity > and readability an ASCII-art'ish bit comment is used instead of > bitfields. > All i.MX31 boards have been patched to use this approach using a > helper program to verify the changes. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: > added sys_proto.h for mx31 > introduced mxc_setup_weimcs(), which is SOC independent > not inlined any more (codesize increased by 60-90 bytes) > V3: > modified register access according to the coding style > --- Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V3] mx31: provide readable WEIM CS accessor 2011-09-29 15:45 ` [U-Boot] [Resend PATCH " Helmut Raiger 2011-09-30 7:32 ` Stefano Babic @ 2011-10-05 11:51 ` Stefano Babic 1 sibling, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-05 11:51 UTC (permalink / raw) To: u-boot On 09/29/2011 05:45 PM, Helmut Raiger wrote: > setup_weimcs() and some macros are added to support the setup > for i.MX31 WEIM chip selects. As a compromise between verbosity > and readability an ASCII-art'ish bit comment is used instead of > bitfields. > All i.MX31 boards have been patched to use this approach using a > helper program to verify the changes. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: > added sys_proto.h for mx31 > introduced mxc_setup_weimcs(), which is SOC independent > not inlined any more (codesize increased by 60-90 bytes) > V3: > modified register access according to the coding style > --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [Resend PATCH V2 (forgot generic.c)] mx31: provide readable WEIM CS accessor 2011-09-29 14:01 ` Helmut Raiger 2011-09-29 14:16 ` Stefano Babic @ 2011-09-29 17:32 ` Wolfgang Denk 1 sibling, 0 replies; 45+ messages in thread From: Wolfgang Denk @ 2011-09-29 17:32 UTC (permalink / raw) To: u-boot Dear Helmut Raiger, In message <4E847A4E.5000602@hale.at> you wrote: > > Do you really thing this is more readable: Not only that, butthe compiler has much better chances for type checking, too. > It seems pretty clumsy to me, but for sure a matter of taste. Then please go on and fix. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Roses are red Violets are blue Some poems rhyme ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 2011-09-22 12:12 [U-Boot] mx31: Add board support for HALE TT-01 Helmut Raiger 2011-09-22 12:12 ` [U-Boot] [PATCH 1/2] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger 2011-09-22 12:12 ` [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 Helmut Raiger @ 2011-10-14 8:05 ` Helmut Raiger 2011-10-14 8:05 ` [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers Helmut Raiger ` (2 more replies) 2011-10-27 11:31 ` [U-Boot] [PATCH V3 " Helmut Raiger 3 siblings, 3 replies; 45+ messages in thread From: Helmut Raiger @ 2011-10-14 8:05 UTC (permalink / raw) To: u-boot Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: no changes since V1 arch/arm/cpu/arm1136/mx31/devices.c | 14 ++++++++++++++ arch/arm/include/asm/arch-mx31/clock.h | 1 + arch/arm/include/asm/arch-mx31/imx-regs.h | 16 ++++++++++++++++ 3 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 1e7d48f..ace48f4 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -38,7 +38,21 @@ void mx31_uart1_hw_init(void) } #endif +#ifdef CONFIG_SYS_MX31_UART2 +void mx31_uart2_hw_init(void) +{ + /* setup pins for UART2 */ + mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX); + mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX); + mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); + mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); +} +#endif + #ifdef CONFIG_MXC_SPI +/* note: putting several spi setups here makes no sense as they may differ + * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3) + */ void mx31_spi2_hw_init(void) { /* SPI2 */ diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index cc99a75..0270d96 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -38,6 +38,7 @@ extern void mx31_gpio_mux(unsigned long mode); extern void mx31_set_pad(enum iomux_pins pin, u32 config); void mx31_uart1_hw_init(void); +void mx31_uart2_hw_init(void); void mx31_spi2_hw_init(void); void mxc_hw_watchdog_enable(void); void mxc_hw_watchdog_reset(void); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index fa06ae9..40abc34 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -628,12 +628,23 @@ struct mx31_weim { /* Register offsets based on IOMUXC_BASE */ /* 0x00 .. 0x7b */ +#define MUX_CTL_CSPI3_MISO 0x0c +#define MUX_CTL_CSPI3_SCLK 0x0d +#define MUX_CTL_CSPI3_SPI_RDY 0x0e +#define MUX_CTL_CSPI3_MOSI 0x13 + #define MUX_CTL_USBH2_DATA1 0x40 #define MUX_CTL_USBH2_DIR 0x44 #define MUX_CTL_USBH2_STP 0x45 #define MUX_CTL_USBH2_NXT 0x46 #define MUX_CTL_USBH2_DATA0 0x47 #define MUX_CTL_USBH2_CLK 0x4B + +#define MUX_CTL_TXD2 0x70 +#define MUX_CTL_RTS2 0x71 +#define MUX_CTL_CTS2 0x72 +#define MUX_CTL_RXD2 0x77 + #define MUX_CTL_RTS1 0x7c #define MUX_CTL_CTS1 0x7d #define MUX_CTL_DTR_DCE1 0x7e @@ -691,6 +702,11 @@ struct mx31_weim { #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) +#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) +#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) +#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) +#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) + #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers 2011-10-14 8:05 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger @ 2011-10-14 8:05 ` Helmut Raiger 2011-10-14 13:29 ` Stefano Babic 2011-10-14 8:05 ` [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger 2011-10-14 10:04 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Stefano Babic 2 siblings, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-10-14 8:05 UTC (permalink / raw) To: u-boot This allows to initialize DDR memory in C code. Currently all mx31 boards use assembler code (lowlevel_init.S) Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: new in V2 arch/arm/include/asm/arch-mx31/imx-regs.h | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 40abc34..f7a39f1 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -484,6 +484,17 @@ struct mx31_weim { struct mx31_weim_cscr cscr[6]; }; +/* ESD control registers */ +struct esdc_regs { + u32 ctl0; + u32 cfg0; + u32 ctl1; + u32 cfg1; + u32 misc; + u32 dly[5]; + u32 dlyl; +}; + #endif #define __REG(x) (*((volatile u32 *)(x))) @@ -548,6 +559,8 @@ struct mx31_weim { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +#define ESDCTL_BASE_ADDR 0xB8001000 + /* 13 fields of the upper CS control register */ #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ cnc, wsc, ew, wws, edc) \ -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers 2011-10-14 8:05 ` [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers Helmut Raiger @ 2011-10-14 13:29 ` Stefano Babic 0 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-14 13:29 UTC (permalink / raw) To: u-boot On 10/14/2011 10:05 AM, Helmut Raiger wrote: > This allows to initialize DDR memory in C code. > Currently all mx31 boards use assembler code (lowlevel_init.S) > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: new in V2 > > arch/arm/include/asm/arch-mx31/imx-regs.h | 13 +++++++++++++ > 1 files changed, 13 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h > index 40abc34..f7a39f1 100644 > --- a/arch/arm/include/asm/arch-mx31/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h > @@ -484,6 +484,17 @@ struct mx31_weim { > struct mx31_weim_cscr cscr[6]; > }; > > +/* ESD control registers */ > +struct esdc_regs { > + u32 ctl0; > + u32 cfg0; > + u32 ctl1; > + u32 cfg1; > + u32 misc; > + u32 dly[5]; > + u32 dlyl; > +}; > + > #endif > > #define __REG(x) (*((volatile u32 *)(x))) > @@ -548,6 +559,8 @@ struct mx31_weim { > #define ESDCTL_BL(x) ((x) << 7) > #define ESDCTL_PRCT(x) ((x) << 0) > > +#define ESDCTL_BASE_ADDR 0xB8001000 > + > /* 13 fields of the upper CS control register */ > #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ > cnc, wsc, ew, wws, edc) \ Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 2011-10-14 8:05 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger 2011-10-14 8:05 ` [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers Helmut Raiger @ 2011-10-14 8:05 ` Helmut Raiger 2011-10-14 11:04 ` Stefano Babic 2011-10-14 10:04 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Stefano Babic 2 siblings, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-10-14 8:05 UTC (permalink / raw) To: u-boot This adds basic board support for TT-01 based on the bluetechnix i.MX31 SOM. Currently only NOR-Flash boot is implemented. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: - MAINTAINER updated and used board.cfg instead of Makefile change - eliminated config.mk - replaced __REG accessors (WEIM and ESD), this patch depends on http://patchwork.ozlabs.org/patch/116978/ - MACH_TYPE_TT01 setup standardized - removed dependency on mx31pdk low level code - reduced lowlevel_init.S to its minimum (AIPS setup only), moved DDR and clock setup to board_early_init_f() - some mulitiline comment cosmetics - added some comments to clarify the board setup (SYS_MONITOR_LEN, SYS_MALLOC_LEN) - removed definition of CONFIG_SYS_GBL_DATA_SIZE MAINTAINERS | 4 + board/hale/tt01/Makefile | 51 ++++++++ board/hale/tt01/lowlevel_init.S | 32 +++++ board/hale/tt01/tt01.c | 187 +++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/tt01.h | 249 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 524 insertions(+), 0 deletions(-) create mode 100644 board/hale/tt01/Makefile create mode 100644 board/hale/tt01/lowlevel_init.S create mode 100644 board/hale/tt01/tt01.c create mode 100644 include/configs/tt01.h diff --git a/MAINTAINERS b/MAINTAINERS index bb95e6d..f01eeff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -749,6 +749,10 @@ Sandeep Paulraj <s-paulraj@ti.com> davinci_dm365evm ARM926EJS davinci_dm6467evm ARM926EJS +Helmut Raiger <helmut.raiger@hale.at> + + tt01 i.MX31 + Linus Walleij <linus.walleij@linaro.org> integratorap various integratorcp various diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile new file mode 100644 index 0000000..f6b2854 --- /dev/null +++ b/board/hale/tt01/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at> +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o +COBJS := tt01.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S new file mode 100644 index 0000000..6e9dc80 --- /dev/null +++ b/board/hale/tt01/lowlevel_init.S @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <asm/arch/imx-regs.h> +#include <asm/macro.h> + +.globl lowlevel_init +lowlevel_init: + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + mov pc, lr diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c new file mode 100644 index 0000000..ecade40 --- /dev/null +++ b/board/hale/tt01/tt01.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <command.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BOARD_STRING "Board: HALE TT-01" + +/* Clock configuration */ +#define CCM_CCMR_SETUP 0x074B0BF5 + +static void board_setup_clocks(void) +{ + struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE; + volatile int wait = 0x10000; + + writel(CCM_CCMR_SETUP, &ccm->ccmr); + while (wait--) ; + + writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr); + writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); + + /* Set up clock to 532MHz */ + writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | + PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | + PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | + PDR0_MCU_PODF(0), &ccm->pdr0); + writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12), + &ccm->mpctl); + writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1), + &ccm->spctl); +} + +/* DRAM configuration */ + +#define ESDMISC_MDDR_SETUP 0x00000004 +#define ESDMISC_MDDR_RESET_DL 0x0000000c +/* + * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below: + * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10 + * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + * note: all but tWTR (1), tRC (111) are reset defaults, + * the same values work in the jtag configuration + * + * Bluetechnix setup has 0x75e73a (for 128MB) = + * 0b 0111 0101 1110 0111 0011 1010 + * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01 + * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + */ +#define ESDCFG0_MDDR_SETUP 0x006ac73a +#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) +#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ(2) | ESDCTL_BL(1)) +#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) +#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) +#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) +#define ESDCTL_RW ESDCTL_SETTINGS + +static void board_setup_sdram(void) +{ + u32 *pad; + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + + /* + * setup pad control for the controller pins + * no loopback, no pull, no keeper, no open drain, + * standard input, standard drive, slow slew rate + */ + for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B; + pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++) + *pad = 0; + + /* set up MX31 DDR Memory Controller */ + writel(ESDMISC_MDDR_SETUP, &esdc->misc); + writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0); + + /* perform DDR init sequence for CSD0 */ + writel(ESDCTL_PRECHARGE, &esdc->ctl0); + writel(0x12344321, CSD0_BASE+0x0f00); + writel(ESDCTL_AUTOREFRESH, &esdc->ctl0); + writel(0x12344321, CSD0_BASE); + writel(0x12344321, CSD0_BASE); + writel(ESDCTL_LOADMODEREG, &esdc->ctl0); + writeb(0xda, CSD0_BASE+0x33); + writeb(0xff, CSD0_BASE+0x1000000); + writel(ESDCTL_RW, &esdc->ctl0); + writel(0xDEADBEEF, CSD0_BASE); + writel(ESDMISC_MDDR_RESET_DL, &esdc->misc); +} + +static void tt01_spi3_hw_init(void) +{ + /* CSPI3 */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC)); + /* CSPI3, SS0 = Atlas */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1)); + + /* start CSPI3 clock (3 = always on except if PLL off) */ + setbits_le32(CCM_CGR0, 3 << 16); +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +int board_early_init_f(void) +{ + /* CS4: FPGA incl. network controller */ + struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + /* this seems essential, won't start without, but why? */ + writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF); + + board_setup_clocks(); + board_setup_sdram(); + mxc_setup_weimcs(4, &cs4); + + /* Setup UART2 and SPI3 pins */ + mx31_uart2_hw_init(); + tt01_spi3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + return 0; +} + +int checkboard(void) +{ + printf(BOARD_STRING "\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/boards.cfg b/boards.cfg index d3d610d..239c04e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -44,6 +44,7 @@ imx31_phycore_eet arm arm1136 imx31_phycore - mx31pdk_nand arm arm1136 mx31pdk freescale mx31 mx31pdk:NAND_U_BOOT mx31pdk arm arm1136 - freescale mx31 mx31pdk:SKIP_LOWLEVEL_INIT mx35pdk arm arm1136 - freescale mx35 +tt01 arm arm1136 - hale mx31 omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x integratorap_cm720t arm arm720t integrator armltd - integratorap diff --git a/include/configs/tt01.h b/include/configs/tt01.h new file mode 100644 index 0000000..ac4b1c5 --- /dev/null +++ b/include/configs/tt01.h @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> + * + * Configuration settings for the HALE TT-01 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +/* High Level Configuration Options */ +#define CONFIG_ARM1136 +#define CONFIG_MX31 +#define CONFIG_MX31_HCLK_FREQ 26000000 +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */ +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + + +/* + * Physical Memory Map: + * CS settings are defined by i.MX31: + * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 + * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 + * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. + * + * HALE set-up of the bluetechnix board for now is: + * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface + * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 + * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) + * the flash chip is a mirrorbit S29WS256N ! + * - the PSRAM is hooked to CS5 (0xB6000000) + * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 + * - 64Mbit = 8MByte (will go away in the production set-up) + * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: + * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks + * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface + * + * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM + * is not used right now. We should be able to reduce the SOM to NAND flash + * only and boot from there. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + +/* default load address, 1MB up the road */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) + +/* The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Size of malloc() pool, make sure possible frame buffer fits */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) + +/* memtest works on all but the last 1MB (u-boot) and malloc area */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END \ + (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000)) + +/* CFI FLASH driver setup */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_SPANSION_S29WS_N +/* + * TODO: Bluetechnix (the supplier of the SOM) did define these values + * in their original version of u-boot (1.2 or so). This should be + * reviewed. + * + * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + * #define CONFIG_SYS_FLASH_PROTECTION + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ + +/* + * FLASH and environment organization, only the Spansion chip is supported: + * - it has 254 * 128kB + 8 * 32kB blocks + * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF + * and 2 sectors with 128k as environment = + * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF + * - this could be less, but this is only for developer versions of the board + * and no-one is going to use the NOR flash anyway. + * + * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is + * way to large, but it avoids ENV overwrite (when updating u-boot) in case + * size breaks the next boundary (as it has with 128k). + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) /* smaller for faster access */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +/* Hardware drivers */ + +/* + * on TT-01 UART1 pins are used by Audio, so we use UART2 + * TT-01 implements a hardware that turns off components depending on + * the power level. In PL=1 the RS232 transceiver is usually off, + * make sure that the transceiver is enabled during PL=1 for testing! + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX31_UART2 + +#define CONFIG_MXC_SPI +#define CONFIG_MXC_GPIO + +/* MC13783 connected to CSPI3 and SS0 */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 2 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) + +#define CONFIG_RTC_MC13783 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +/* console is UART2 on TT-01 */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* ethernet setup for the onboard smc9118 */ +#define CONFIG_MII +#define CONFIG_SMC911X +/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */ +#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) +#define CONFIG_SMC911X_16_BIT + +/* + * Command definition + */ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_NAND +/* + * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support + * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports + * a software locking scheme. + */ + +#define CONFIG_BOOTDELAY 3 + +/* + * currently a default setting for booting via script is implemented + * set user to login name and serverip to tftp host, define your + * boot behaviour in bootscript.loginname + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=dhcp bootscript.$(user); source\0" + +#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ +#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ + +/* Miscellaneous configurable options */ +#define CONFIG_HUSH_PARSER +#define CONFIG_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "TT01> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_NAND_MXC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +/* + * actually this is nothing someone wants to configure! + * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init() + * is not used by the driver. + */ +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +#define CONFIG_MXC_NAND_HWECC + +/* the current u-boot driver does not use the nand flash setup! */ +#define CONFIG_SYS_NAND_LARGEPAGE +/* + * it's not 16 bit: + * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT + * the current u-boot mxc_nand.c tries to auto-detect, but this only + * reads the boot settings during reset (which might be wrong) + */ + +#endif /* __CONFIG_H */ -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 2011-10-14 8:05 ` [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger @ 2011-10-14 11:04 ` Stefano Babic 2011-10-14 21:14 ` Wolfgang Denk 0 siblings, 1 reply; 45+ messages in thread From: Stefano Babic @ 2011-10-14 11:04 UTC (permalink / raw) To: u-boot On 10/14/2011 10:05 AM, Helmut Raiger wrote: > This adds basic board support for TT-01 based on > the bluetechnix i.MX31 SOM. Currently only NOR-Flash > boot is implemented. > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > > V2: > - MAINTAINER updated and used board.cfg instead of Makefile change > - eliminated config.mk > - replaced __REG accessors (WEIM and ESD), > this patch depends on http://patchwork.ozlabs.org/patch/116978/ > - MACH_TYPE_TT01 setup standardized > - removed dependency on mx31pdk low level code > - reduced lowlevel_init.S to its minimum (AIPS setup only), moved > DDR and clock setup to board_early_init_f() > - some mulitiline comment cosmetics > - added some comments to clarify the board setup > (SYS_MONITOR_LEN, SYS_MALLOC_LEN) > - removed definition of CONFIG_SYS_GBL_DATA_SIZE > > MAINTAINERS | 4 + > board/hale/tt01/Makefile | 51 ++++++++ > board/hale/tt01/lowlevel_init.S | 32 +++++ > board/hale/tt01/tt01.c | 187 +++++++++++++++++++++++++++++ > boards.cfg | 1 + > include/configs/tt01.h | 249 +++++++++++++++++++++++++++++++++++++++ > 6 files changed, 524 insertions(+), 0 deletions(-) > create mode 100644 board/hale/tt01/Makefile > create mode 100644 board/hale/tt01/lowlevel_init.S > create mode 100644 board/hale/tt01/tt01.c > create mode 100644 include/configs/tt01.h > > diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c > new file mode 100644 > index 0000000..ecade40 > --- /dev/null > +++ b/board/hale/tt01/tt01.c > @@ -0,0 +1,187 @@ > +/* > + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> > + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> > + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <netdev.h> > +#include <command.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/io.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define BOARD_STRING "Board: HALE TT-01" > + > +/* Clock configuration */ > +#define CCM_CCMR_SETUP 0x074B0BF5 > + > +static void board_setup_clocks(void) > +{ > + struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE; > + volatile int wait = 0x10000; > + > + writel(CCM_CCMR_SETUP, &ccm->ccmr); > + while (wait--) ; I had the same problem - a udelay() before relocation. However, there is a sdelay() in armv7 (syslib.c), and I sent a patch to move this stuff into arm/lib to make this and the other functions available to all ARM SOCs http://patchwork.ozlabs.org/patch/114909/ Albert, what do you think about ? > +/* DRAM configuration */ > + > +#define ESDMISC_MDDR_SETUP 0x00000004 > +#define ESDMISC_MDDR_RESET_DL 0x0000000c > +/* > + * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below: > + * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10 > + * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11 > + * tRCD = 011, tRC = 010 > + * note: all but tWTR (1), tRC (111) are reset defaults, > + * the same values work in the jtag configuration > + * > + * Bluetechnix setup has 0x75e73a (for 128MB) = > + * 0b 0111 0101 1110 0111 0011 1010 > + * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01 > + * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11 > + * tRCD = 011, tRC = 010 > + */ Ok, values are good explained ! > +static void board_setup_sdram(void) > +{ > + u32 *pad; > + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; > + > + /* > + * setup pad control for the controller pins > + * no loopback, no pull, no keeper, no open drain, > + * standard input, standard drive, slow slew rate > + */ > + for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B; > + pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++) > + *pad = 0; > + > + /* set up MX31 DDR Memory Controller */ > + writel(ESDMISC_MDDR_SETUP, &esdc->misc); > + writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0); > + > + /* perform DDR init sequence for CSD0 */ > + writel(ESDCTL_PRECHARGE, &esdc->ctl0); > + writel(0x12344321, CSD0_BASE+0x0f00); > + writel(ESDCTL_AUTOREFRESH, &esdc->ctl0); > + writel(0x12344321, CSD0_BASE); > + writel(0x12344321, CSD0_BASE); > + writel(ESDCTL_LOADMODEREG, &esdc->ctl0); > + writeb(0xda, CSD0_BASE+0x33); > + writeb(0xff, CSD0_BASE+0x1000000); > + writel(ESDCTL_RW, &esdc->ctl0); > + writel(0xDEADBEEF, CSD0_BASE); > + writel(ESDMISC_MDDR_RESET_DL, &esdc->misc); I have supposed that the last thing to do is to set the ctl0 register to normal mode, and that is. I wonder that you issue at the end a DL_RESET, but I do not know your RAM. It is in any case different as explained in manual (19.4.5.6). > + > + /* this seems essential, won't start without, but why? */ > + writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF); I cannot help - It seems related to yiour board, because I have not seen the same issue on other i.MX31 targets. > + > +int checkboard(void) > +{ > + printf(BOARD_STRING "\n"); Replace with "puts". > +/* MC13783 connected to CSPI3 and SS0 */ > +#define CONFIG_FSL_PMIC There are changes for PMIC. There is now a common PMIC core to support PMICs from different manufacturers, not only Freescale. The old driver is dropped - I sent patches to adapt the current boards, and I have merged them on u-boot-imx. Not yet pulled, but with the old driver your board will not be built. You need to set (instead of CONFIG_FSL_PMIC): #define CONFIG_PMIC #define CONFIG_PMIC_SPI #define CONFIG_PMIC_FSL > +#define CONFIG_FSL_PMIC_BUS 2 > +#define CONFIG_FSL_PMIC_CS 0 > +#define CONFIG_FSL_PMIC_CLK 1000000 > +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) These are ok - special SPI setup have maintained the name. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 2011-10-14 11:04 ` Stefano Babic @ 2011-10-14 21:14 ` Wolfgang Denk 2011-10-15 5:40 ` stefano babic 0 siblings, 1 reply; 45+ messages in thread From: Wolfgang Denk @ 2011-10-14 21:14 UTC (permalink / raw) To: u-boot Dear Stefano Babic, In message <4E981741.6050809@denx.de> you wrote: > > > + while (wait--) ; Checkpatch is supposed to complain about this; the semicolon goes on the next line. > > I had the same problem - a udelay() before relocation. This should be no problem. udelay() is supposed to work fine very early - ling before relocation. > However, there is a sdelay() in armv7 (syslib.c), and I sent a patch to > move this stuff into arm/lib to make this and the other functions > available to all ARM SOCs What the hell is sdelay()? Please let us not introduce arbitrary new functions without need. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Brontosaurus Principle: Organizations can grow faster than their brains can manage them in relation to their environment and to their own physiology: when this occurs, they are an endangered species. - Thomas K. Connellan ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 2011-10-14 21:14 ` Wolfgang Denk @ 2011-10-15 5:40 ` stefano babic 2011-10-15 8:52 ` Wolfgang Denk 0 siblings, 1 reply; 45+ messages in thread From: stefano babic @ 2011-10-15 5:40 UTC (permalink / raw) To: u-boot Am 14/10/2011 23:14, schrieb Wolfgang Denk: > Dear Stefano Babic, > > In message <4E981741.6050809@denx.de> you wrote: >> >>> + while (wait--) ; > > Checkpatch is supposed to complain about this; the semicolon goes on > the next line. You're right. >> I had the same problem - a udelay() before relocation. > > This should be no problem. udelay() is supposed to work fine very > early - ling before relocation. Maybe I should be more clearer - we need a way to wait some time when even PLL or clock module (for i.MX) are not yet programmed. > >> However, there is a sdelay() in armv7 (syslib.c), and I sent a patch to >> move this stuff into arm/lib to make this and the other functions >> available to all ARM SOCs > > What the hell is sdelay()? > > Please let us not introduce arbitrary new functions without need. This is *not* a new function. I see it was introduced for OMAP3 since a lot of time ago. I do not want to introduce another function, I will reuse what is already available for other SOCs. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 2011-10-15 5:40 ` stefano babic @ 2011-10-15 8:52 ` Wolfgang Denk 2011-10-15 11:11 ` Stefano Babic 0 siblings, 1 reply; 45+ messages in thread From: Wolfgang Denk @ 2011-10-15 8:52 UTC (permalink / raw) To: u-boot Dear stefano babic, In message <4E991CC3.5010205@denx.de> you wrote: > > > This should be no problem. udelay() is supposed to work fine very > > early - ling before relocation. > > Maybe I should be more clearer - we need a way to wait some time when > even PLL or clock module (for i.MX) are not yet programmed. > > What the hell is sdelay()? > > > > Please let us not introduce arbitrary new functions without need. > > This is *not* a new function. I see it was introduced for OMAP3 since a > lot of time ago. I do not want to introduce another function, I will > reuse what is already available for other SOCs. The fact that some private function was allowed (or rather not objected durign the reviews) for s specific implementation does not mean that it is a good idea to generalize this code for other boards or architectures - if we do something like that, we should discuss it first, and put it in context with the (Not yet complete) discussion about the new Timer API. I definitely do not want to see this function spread uncontrolled and undiscussed. If we find it's useful, it should be made really general. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Imagination is more important than knowledge. -- Albert Einstein ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 2011-10-15 8:52 ` Wolfgang Denk @ 2011-10-15 11:11 ` Stefano Babic 0 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-15 11:11 UTC (permalink / raw) To: u-boot On 10/15/2011 10:52 AM, Wolfgang Denk wrote: > - if we do something like that, we should discuss it > first, and put it in context with the (Not yet complete) discussion > about the new Timer API. Agree, you're right - this should be part of the Timer API > I definitely do not want to see this function spread uncontrolled and > undiscussed. If we find it's useful, it should be made really > general. Understood, you convinced me ;-). Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 2011-10-14 8:05 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger 2011-10-14 8:05 ` [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers Helmut Raiger 2011-10-14 8:05 ` [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger @ 2011-10-14 10:04 ` Stefano Babic 2 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-14 10:04 UTC (permalink / raw) To: u-boot On 10/14/2011 10:05 AM, Helmut Raiger wrote: > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: no changes since V1 > Hi Helmut, > #ifdef CONFIG_MXC_SPI > +/* note: putting several spi setups here makes no sense as they may differ > + * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3) > + */ Wrong multiline comment, please fix it. Sorry, not seen in first review. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 1/3] mx31: define pins and init for UART2 and CSPI3 2011-09-22 12:12 [U-Boot] mx31: Add board support for HALE TT-01 Helmut Raiger ` (2 preceding siblings ...) 2011-10-14 8:05 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger @ 2011-10-27 11:31 ` Helmut Raiger 2011-10-27 11:31 ` [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers Helmut Raiger ` (3 more replies) 3 siblings, 4 replies; 45+ messages in thread From: Helmut Raiger @ 2011-10-27 11:31 UTC (permalink / raw) To: u-boot Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: no changes since V1 V3: fixed multiline comment, rebased to u-boot-imx arch/arm/cpu/arm1136/mx31/devices.c | 15 +++++++++++++++ arch/arm/include/asm/arch-mx31/clock.h | 1 + arch/arm/include/asm/arch-mx31/imx-regs.h | 16 ++++++++++++++++ 3 files changed, 32 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 1e7d48f..b42dac3 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -38,7 +38,22 @@ void mx31_uart1_hw_init(void) } #endif +#ifdef CONFIG_SYS_MX31_UART2 +void mx31_uart2_hw_init(void) +{ + /* setup pins for UART2 */ + mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX); + mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX); + mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); + mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); +} +#endif + #ifdef CONFIG_MXC_SPI +/* + * Note: putting several spi setups here makes no sense as they may differ + * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3) + */ void mx31_spi2_hw_init(void) { /* SPI2 */ diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 3e22d9a..253a0e1 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -40,6 +40,7 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config); extern void mx31_set_gpr(enum iomux_gp_func gp, char en); void mx31_uart1_hw_init(void); +void mx31_uart2_hw_init(void); void mx31_spi2_hw_init(void); void mxc_hw_watchdog_enable(void); void mxc_hw_watchdog_reset(void); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 6ce008d..f487975 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -680,12 +680,23 @@ struct mx31_weim { /* Register offsets based on IOMUXC_BASE */ /* 0x00 .. 0x7b */ +#define MUX_CTL_CSPI3_MISO 0x0c +#define MUX_CTL_CSPI3_SCLK 0x0d +#define MUX_CTL_CSPI3_SPI_RDY 0x0e +#define MUX_CTL_CSPI3_MOSI 0x13 + #define MUX_CTL_USBH2_DATA1 0x40 #define MUX_CTL_USBH2_DIR 0x44 #define MUX_CTL_USBH2_STP 0x45 #define MUX_CTL_USBH2_NXT 0x46 #define MUX_CTL_USBH2_DATA0 0x47 #define MUX_CTL_USBH2_CLK 0x4B + +#define MUX_CTL_TXD2 0x70 +#define MUX_CTL_RTS2 0x71 +#define MUX_CTL_CTS2 0x72 +#define MUX_CTL_RXD2 0x77 + #define MUX_CTL_RTS1 0x7c #define MUX_CTL_CTS1 0x7d #define MUX_CTL_DTR_DCE1 0x7e @@ -743,6 +754,11 @@ struct mx31_weim { #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) +#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) +#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) +#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) +#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) + #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers 2011-10-27 11:31 ` [U-Boot] [PATCH V3 " Helmut Raiger @ 2011-10-27 11:31 ` Helmut Raiger 2011-10-27 12:49 ` Stefano Babic 2011-10-28 8:28 ` Stefano Babic 2011-10-27 11:31 ` [U-Boot] [PATCH V3 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger ` (2 subsequent siblings) 3 siblings, 2 replies; 45+ messages in thread From: Helmut Raiger @ 2011-10-27 11:31 UTC (permalink / raw) To: u-boot This allows to initialize DDR memory in C code. Currently all mx31 boards use assembler code (lowlevel_init.S) Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: new in V2 V3: no changes arch/arm/include/asm/arch-mx31/imx-regs.h | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index f487975..afdaa1c 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -522,6 +522,17 @@ struct mx31_weim { struct mx31_weim_cscr cscr[6]; }; +/* ESD control registers */ +struct esdc_regs { + u32 ctl0; + u32 cfg0; + u32 ctl1; + u32 cfg1; + u32 misc; + u32 dly[5]; + u32 dlyl; +}; + #endif #define __REG(x) (*((volatile u32 *)(x))) @@ -600,6 +611,8 @@ struct mx31_weim { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +#define ESDCTL_BASE_ADDR 0xB8001000 + /* 13 fields of the upper CS control register */ #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ cnc, wsc, ew, wws, edc) \ -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers 2011-10-27 11:31 ` [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers Helmut Raiger @ 2011-10-27 12:49 ` Stefano Babic 2011-10-28 8:28 ` Stefano Babic 1 sibling, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-27 12:49 UTC (permalink / raw) To: u-boot On 10/27/2011 01:31 PM, Helmut Raiger wrote: > This allows to initialize DDR memory in C code. > Currently all mx31 boards use assembler code (lowlevel_init.S) > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: new in V2 > V3: no changes > > arch/arm/include/asm/arch-mx31/imx-regs.h | 13 +++++++++++++ > 1 files changed, 13 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h > index f487975..afdaa1c 100644 > --- a/arch/arm/include/asm/arch-mx31/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h > @@ -522,6 +522,17 @@ struct mx31_weim { > struct mx31_weim_cscr cscr[6]; > }; > > +/* ESD control registers */ > +struct esdc_regs { > + u32 ctl0; > + u32 cfg0; > + u32 ctl1; > + u32 cfg1; > + u32 misc; > + u32 dly[5]; > + u32 dlyl; > +}; > + > #endif > > #define __REG(x) (*((volatile u32 *)(x))) > @@ -600,6 +611,8 @@ struct mx31_weim { > #define ESDCTL_BL(x) ((x) << 7) > #define ESDCTL_PRCT(x) ((x) << 0) > > +#define ESDCTL_BASE_ADDR 0xB8001000 > + > /* 13 fields of the upper CS control register */ > #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ > cnc, wsc, ew, wws, edc) \ Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers 2011-10-27 11:31 ` [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers Helmut Raiger 2011-10-27 12:49 ` Stefano Babic @ 2011-10-28 8:28 ` Stefano Babic 1 sibling, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-28 8:28 UTC (permalink / raw) To: u-boot On 10/27/2011 01:31 PM, Helmut Raiger wrote: > This allows to initialize DDR memory in C code. > Currently all mx31 boards use assembler code (lowlevel_init.S) > > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: new in V2 > V3: no changes > > arch/arm/include/asm/arch-mx31/imx-regs.h | 13 +++++++++++++ > 1 files changed, 13 insertions(+), 0 deletions(-) > Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 3/3] mx31: Add board support for HALE TT-01 2011-10-27 11:31 ` [U-Boot] [PATCH V3 " Helmut Raiger 2011-10-27 11:31 ` [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers Helmut Raiger @ 2011-10-27 11:31 ` Helmut Raiger 2011-10-27 12:59 ` Stefano Babic 2011-10-27 12:49 ` [U-Boot] [PATCH V3 1/3] mx31: define pins and init for UART2 and CSPI3 Stefano Babic 2011-10-28 8:28 ` Stefano Babic 3 siblings, 1 reply; 45+ messages in thread From: Helmut Raiger @ 2011-10-27 11:31 UTC (permalink / raw) To: u-boot This adds basic board support for TT-01 based on the Bluetechnix i.MX31 SOM. Currently only NOR-Flash boot is implemented. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> --- V2: - MAINTAINER updated and used board.cfg instead of Makefile change - eliminated config.mk - replaced __REG accessors (WEIM and ESD), this patch depends on http://patchwork.ozlabs.org/patch/116978/ - MACH_TYPE_TT01 setup standardized - removed dependency on mx31pdk low level code - reduced lowlevel_init.S to its minimum (AIPS setup only), moved DDR and clock setup to board_early_init_f() - some mulitiline comment cosmetics - added some comments to clarify the board setup (SYS_MONITOR_LEN, SYS_MALLOC_LEN) - removed definition of CONFIG_SYS_GBL_DATA_SIZE V3: - change to the new pmic interface, added board_late_init() for it. - use CONFIG_RTC_MC13XXX - minor cosmetic changes I've not investigated the DDR setup any further, it's pretty old and works. We'll re-check with the new hardware setup (currently under developement) which has a new RAM chip. MAINTAINERS | 4 + board/hale/tt01/Makefile | 51 ++++++++ board/hale/tt01/lowlevel_init.S | 32 +++++ board/hale/tt01/tt01.c | 200 ++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/tt01.h | 254 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 542 insertions(+), 0 deletions(-) create mode 100644 board/hale/tt01/Makefile create mode 100644 board/hale/tt01/lowlevel_init.S create mode 100644 board/hale/tt01/tt01.c create mode 100644 include/configs/tt01.h diff --git a/MAINTAINERS b/MAINTAINERS index cd0dd91..62e016d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -757,6 +757,10 @@ Sandeep Paulraj <s-paulraj@ti.com> davinci_dm365evm ARM926EJS davinci_dm6467evm ARM926EJS +Helmut Raiger <helmut.raiger@hale.at> + + tt01 i.MX31 + Linus Walleij <linus.walleij@linaro.org> integratorap various integratorcp various diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile new file mode 100644 index 0000000..f6b2854 --- /dev/null +++ b/board/hale/tt01/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at> +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o +COBJS := tt01.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S new file mode 100644 index 0000000..6e9dc80 --- /dev/null +++ b/board/hale/tt01/lowlevel_init.S @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <asm/arch/imx-regs.h> +#include <asm/macro.h> + +.globl lowlevel_init +lowlevel_init: + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + mov pc, lr diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c new file mode 100644 index 0000000..2995c8f --- /dev/null +++ b/board/hale/tt01/tt01.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <command.h> +#include <pmic.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BOARD_STRING "Board: HALE TT-01" + +/* Clock configuration */ +#define CCM_CCMR_SETUP 0x074B0BF5 + +static void board_setup_clocks(void) +{ + struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE; + volatile int wait = 0x10000; + + writel(CCM_CCMR_SETUP, &ccm->ccmr); + while (wait--) + ; + + writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr); + writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); + + /* Set up clock to 532MHz */ + writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | + PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | + PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | + PDR0_MCU_PODF(0), &ccm->pdr0); + writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12), + &ccm->mpctl); + writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1), + &ccm->spctl); +} + +/* DRAM configuration */ + +#define ESDMISC_MDDR_SETUP 0x00000004 +#define ESDMISC_MDDR_RESET_DL 0x0000000c +/* + * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below: + * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10 + * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + * note: all but tWTR (1), tRC (111) are reset defaults, + * the same values work in the jtag configuration + * + * Bluetechnix setup has 0x75e73a (for 128MB) = + * 0b 0111 0101 1110 0111 0011 1010 + * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01 + * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + */ +#define ESDCFG0_MDDR_SETUP 0x006ac73a +#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) +#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ(2) | ESDCTL_BL(1)) +#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) +#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) +#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) +#define ESDCTL_RW ESDCTL_SETTINGS + +static void board_setup_sdram(void) +{ + u32 *pad; + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + + /* + * setup pad control for the controller pins + * no loopback, no pull, no keeper, no open drain, + * standard input, standard drive, slow slew rate + */ + for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B; + pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++) + *pad = 0; + + /* set up MX31 DDR Memory Controller */ + writel(ESDMISC_MDDR_SETUP, &esdc->misc); + writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0); + + /* perform DDR init sequence for CSD0 */ + writel(ESDCTL_PRECHARGE, &esdc->ctl0); + writel(0x12344321, CSD0_BASE+0x0f00); + writel(ESDCTL_AUTOREFRESH, &esdc->ctl0); + writel(0x12344321, CSD0_BASE); + writel(0x12344321, CSD0_BASE); + writel(ESDCTL_LOADMODEREG, &esdc->ctl0); + writeb(0xda, CSD0_BASE+0x33); + writeb(0xff, CSD0_BASE+0x1000000); + writel(ESDCTL_RW, &esdc->ctl0); + writel(0xDEADBEEF, CSD0_BASE); + writel(ESDMISC_MDDR_RESET_DL, &esdc->misc); +} + +static void tt01_spi3_hw_init(void) +{ + /* CSPI3 */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC)); + /* CSPI3, SS0 = Atlas */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1)); + + /* start CSPI3 clock (3 = always on except if PLL off) */ + setbits_le32(CCM_CGR0, 3 << 16); +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +int board_early_init_f(void) +{ + /* CS4: FPGA incl. network controller */ + struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + /* this seems essential, won't start without, but why? */ + writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF); + + board_setup_clocks(); + board_setup_sdram(); + mxc_setup_weimcs(4, &cs4); + + /* Setup UART2 and SPI3 pins */ + mx31_uart2_hw_init(); + tt01_spi3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + return 0; +} + +int board_late_init(void) +{ + pmic_init(); + +#ifdef CONFIG_HW_WATCHDOG + mxc_hw_watchdog_enable(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts(BOARD_STRING "\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/boards.cfg b/boards.cfg index 0de08a1..4e43b00 100644 --- a/boards.cfg +++ b/boards.cfg @@ -43,6 +43,7 @@ imx31_phycore arm arm1136 - - imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT mx35pdk arm arm1136 - freescale mx35 +tt01 arm arm1136 - hale mx31 omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x integratorap_cm720t arm arm720t integrator armltd - integratorap diff --git a/include/configs/tt01.h b/include/configs/tt01.h new file mode 100644 index 0000000..4d7c7f4 --- /dev/null +++ b/include/configs/tt01.h @@ -0,0 +1,254 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> + * + * Configuration settings for the HALE TT-01 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +/* High Level Configuration Options */ +#define CONFIG_ARM1136 +#define CONFIG_MX31 +#define CONFIG_MX31_HCLK_FREQ 26000000 +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */ +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + + +/* + * Physical Memory Map: + * CS settings are defined by i.MX31: + * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000 + * - CS0 and CS1 are 128MB each, at A0000000 and A8000000 + * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6.. + * + * HALE set-up of the bluetechnix board for now is: + * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface + * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0 + * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM) + * the flash chip is a mirrorbit S29WS256N ! + * - the PSRAM is hooked to CS5 (0xB6000000) + * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1 + * - 64Mbit = 8MByte (will go away in the production set-up) + * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC: + * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks + * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface + * + * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM + * is not used right now. We should be able to reduce the SOM to NAND flash + * only and boot from there. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define BOARD_LATE_INIT + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + +/* default load address, 1MB up the road */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000) + +/* The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Size of malloc() pool, make sure possible frame buffer fits */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024) + +/* memtest works on all but the last 1MB (u-boot) and malloc area */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END \ + (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000)) + +/* CFI FLASH driver setup */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_SPANSION_S29WS_N +/* + * TODO: Bluetechnix (the supplier of the SOM) did define these values + * in their original version of u-boot (1.2 or so). This should be + * reviewed. + * + * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + * #define CONFIG_SYS_FLASH_PROTECTION + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */ + +/* + * FLASH and environment organization, only the Spansion chip is supported: + * - it has 254 * 128kB + 8 * 32kB blocks + * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF + * and 2 sectors with 128k as environment = + * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF + * - this could be less, but this is only for developer versions of the board + * and no-one is going to use the NOR flash anyway. + * + * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is + * way to large, but it avoids ENV overwrite (when updating u-boot) in case + * size breaks the next boundary (as it has with 128k). + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) /* smaller for faster access */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +/* Hardware drivers */ + +/* + * on TT-01 UART1 pins are used by Audio, so we use UART2 + * TT-01 implements a hardware that turns off components depending on + * the power level. In PL=1 the RS232 transceiver is usually off, + * make sure that the transceiver is enabled during PL=1 for testing! + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX31_UART2 + +#define CONFIG_MXC_SPI +#define CONFIG_MXC_GPIO + +/* MC13783 connected to CSPI3 and SS0 */ +#define CONFIG_PMIC +#define CONFIG_PMIC_SPI +#define CONFIG_PMIC_FSL + +#define CONFIG_FSL_PMIC_BUS 2 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_BITLEN 32 + +#define CONFIG_RTC_MC13XXX + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +/* console is UART2 on TT-01 */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* ethernet setup for the onboard smc9118 */ +#define CONFIG_MII +#define CONFIG_SMC911X +/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */ +#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) +#define CONFIG_SMC911X_16_BIT + +/* + * Command definition + */ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_NAND +/* + * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support + * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports + * a software locking scheme. + */ + +#define CONFIG_BOOTDELAY 3 + +/* + * currently a default setting for booting via script is implemented + * set user to login name and serverip to tftp host, define your + * boot behaviour in bootscript.loginname + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=dhcp bootscript.$(user); source\0" + +#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */ +#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */ + +/* Miscellaneous configurable options */ +#define CONFIG_HUSH_PARSER +#define CONFIG_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "TT01> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_NAND_MXC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +/* + * actually this is nothing someone wants to configure! + * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init() + * is not used by the driver. + */ +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +#define CONFIG_MXC_NAND_HWECC + +/* the current u-boot driver does not use the nand flash setup! */ +#define CONFIG_SYS_NAND_LARGEPAGE +/* + * it's not 16 bit: + * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT + * the current u-boot mxc_nand.c tries to auto-detect, but this only + * reads the boot settings during reset (which might be wrong) + */ + +#endif /* __CONFIG_H */ -- 1.7.4.4 -- Scanned by MailScanner. ^ permalink raw reply related [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 3/3] mx31: Add board support for HALE TT-01 2011-10-27 11:31 ` [U-Boot] [PATCH V3 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger @ 2011-10-27 12:59 ` Stefano Babic 0 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-27 12:59 UTC (permalink / raw) To: u-boot On 10/27/2011 01:31 PM, Helmut Raiger wrote: > This adds basic board support for TT-01 based on > the Bluetechnix i.MX31 SOM. Currently only NOR-Flash > boot is implemented. > Hi Helmut, > diff --git a/boards.cfg b/boards.cfg > index 0de08a1..4e43b00 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -43,6 +43,7 @@ imx31_phycore arm arm1136 - - > imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET > mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT > mx35pdk arm arm1136 - freescale mx35 > +tt01 arm arm1136 - hale mx31 your entry is not sorted. I think the order for the sort is CPU, then SOC and target. You do not need to repost (if there are no other comments), I have another board to merge and I will fix it myself. Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 1/3] mx31: define pins and init for UART2 and CSPI3 2011-10-27 11:31 ` [U-Boot] [PATCH V3 " Helmut Raiger 2011-10-27 11:31 ` [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers Helmut Raiger 2011-10-27 11:31 ` [U-Boot] [PATCH V3 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger @ 2011-10-27 12:49 ` Stefano Babic 2011-10-28 8:28 ` Stefano Babic 3 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-27 12:49 UTC (permalink / raw) To: u-boot On 10/27/2011 01:31 PM, Helmut Raiger wrote: > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: no changes since V1 > V3: fixed multiline comment, rebased to u-boot-imx > > arch/arm/cpu/arm1136/mx31/devices.c | 15 +++++++++++++++ > arch/arm/include/asm/arch-mx31/clock.h | 1 + > arch/arm/include/asm/arch-mx31/imx-regs.h | 16 ++++++++++++++++ > 3 files changed, 32 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c > index 1e7d48f..b42dac3 100644 > --- a/arch/arm/cpu/arm1136/mx31/devices.c > +++ b/arch/arm/cpu/arm1136/mx31/devices.c > @@ -38,7 +38,22 @@ void mx31_uart1_hw_init(void) > } > #endif > Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
* [U-Boot] [PATCH V3 1/3] mx31: define pins and init for UART2 and CSPI3 2011-10-27 11:31 ` [U-Boot] [PATCH V3 " Helmut Raiger ` (2 preceding siblings ...) 2011-10-27 12:49 ` [U-Boot] [PATCH V3 1/3] mx31: define pins and init for UART2 and CSPI3 Stefano Babic @ 2011-10-28 8:28 ` Stefano Babic 3 siblings, 0 replies; 45+ messages in thread From: Stefano Babic @ 2011-10-28 8:28 UTC (permalink / raw) To: u-boot On 10/27/2011 01:31 PM, Helmut Raiger wrote: > Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> > --- > V2: no changes since V1 > V3: fixed multiline comment, rebased to u-boot-imx > > arch/arm/cpu/arm1136/mx31/devices.c | 15 +++++++++++++++ > arch/arm/include/asm/arch-mx31/clock.h | 1 + > arch/arm/include/asm/arch-mx31/imx-regs.h | 16 ++++++++++++++++ > 3 files changed, 32 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c > index 1e7d48f..b42dac3 100644 > --- a/arch/arm/cpu/arm1136/mx31/devices.c > +++ b/arch/arm/cpu/arm1136/mx31/devices.c > @@ -38,7 +38,22 @@ void mx31_uart1_hw_init(void) > } > #endif Applied to u-boot-imx, thanks. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 45+ messages in thread
end of thread, other threads:[~2011-10-28 8:28 UTC | newest] Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-09-22 12:12 [U-Boot] mx31: Add board support for HALE TT-01 Helmut Raiger 2011-09-22 12:12 ` [U-Boot] [PATCH 1/2] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger 2011-09-22 12:12 ` [U-Boot] [PATCH 2/2] TT-01: add basic board support for HALE TT-01 Helmut Raiger 2011-09-22 13:36 ` Fabio Estevam 2011-09-22 13:51 ` Stefano Babic 2011-10-06 13:07 ` Helmut Raiger 2011-10-06 13:27 ` Stefano Babic 2011-09-22 14:08 ` Wolfgang Denk 2011-09-28 12:48 ` [U-Boot] mx31: Approach for WEIM CS accessors Helmut Raiger 2011-09-28 12:48 ` [U-Boot] [PATCH] mx31: provide readable WEIM CS accessor Helmut Raiger 2011-09-28 15:14 ` Stefano Babic 2011-09-29 6:32 ` Helmut Raiger 2011-09-29 6:59 ` Stefano Babic 2011-09-29 7:30 ` Helmut Raiger 2011-09-29 9:17 ` Stefano Babic 2011-09-29 12:19 ` [U-Boot] [PATCH V2] " Helmut Raiger 2011-09-29 12:25 ` [U-Boot] [Resend PATCH V2 (forgot generic.c)] " Helmut Raiger 2011-09-29 13:21 ` Stefano Babic 2011-09-29 14:01 ` Helmut Raiger 2011-09-29 14:16 ` Stefano Babic 2011-09-29 14:55 ` [U-Boot] [PATCH V3] " Helmut Raiger 2011-09-29 15:11 ` Helmut Raiger 2011-09-29 15:19 ` Stefano Babic 2011-09-29 15:45 ` [U-Boot] [Resend PATCH " Helmut Raiger 2011-09-30 7:32 ` Stefano Babic 2011-10-05 11:51 ` Stefano Babic 2011-09-29 17:32 ` [U-Boot] [Resend PATCH V2 (forgot generic.c)] " Wolfgang Denk 2011-10-14 8:05 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Helmut Raiger 2011-10-14 8:05 ` [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers Helmut Raiger 2011-10-14 13:29 ` Stefano Babic 2011-10-14 8:05 ` [U-Boot] [PATCH V2 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger 2011-10-14 11:04 ` Stefano Babic 2011-10-14 21:14 ` Wolfgang Denk 2011-10-15 5:40 ` stefano babic 2011-10-15 8:52 ` Wolfgang Denk 2011-10-15 11:11 ` Stefano Babic 2011-10-14 10:04 ` [U-Boot] [PATCH V2 1/3] mx31: define pins and init for UART2 and CSPI3 Stefano Babic 2011-10-27 11:31 ` [U-Boot] [PATCH V3 " Helmut Raiger 2011-10-27 11:31 ` [U-Boot] [PATCH V3 2/3] mx31: add ESD control registers Helmut Raiger 2011-10-27 12:49 ` Stefano Babic 2011-10-28 8:28 ` Stefano Babic 2011-10-27 11:31 ` [U-Boot] [PATCH V3 3/3] mx31: Add board support for HALE TT-01 Helmut Raiger 2011-10-27 12:59 ` Stefano Babic 2011-10-27 12:49 ` [U-Boot] [PATCH V3 1/3] mx31: define pins and init for UART2 and CSPI3 Stefano Babic 2011-10-28 8:28 ` Stefano Babic
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.