* [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v4)
@ 2013-10-04 16:56 Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 1/4] Fix coding style Fabien Chouteau
` (3 more replies)
0 siblings, 4 replies; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-04 16:56 UTC (permalink / raw)
Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
Another attempt. I think this is the best I can do to fulfil all comments.
Fabien Chouteau (4):
Fix coding style
Improve Monitor disas with symbol lookup
Refactoring MonitorDef array
Add ARM registers definitions for Monitor commands
disas.c | 19 +-
include/monitor/monitor_def.h | 18 ++
include/qemu/typedefs.h | 1 +
include/qom/cpu.h | 3 +
monitor.c | 396 +----------------------------------------
target-arm/Makefile.objs | 2 +-
target-arm/cpu.c | 7 +
target-arm/monitor.c | 40 +++++
target-i386/Makefile.objs | 2 +-
target-i386/cpu-qom.h | 1 +
target-i386/cpu.c | 7 +
target-i386/monitor.c | 62 +++++++
target-ppc/Makefile.objs | 2 +-
target-ppc/monitor.c | 234 ++++++++++++++++++++++++
target-ppc/translate_init.c | 8 +
target-sparc/Makefile.objs | 2 +-
target-sparc/cpu-qom.h | 1 -
target-sparc/cpu.c | 7 +
target-sparc/monitor.c | 138 ++++++++++++++
19 files changed, 552 insertions(+), 398 deletions(-)
create mode 100644 include/monitor/monitor_def.h
create mode 100644 target-arm/monitor.c
create mode 100644 target-i386/monitor.c
create mode 100644 target-ppc/monitor.c
create mode 100644 target-sparc/monitor.c
--
1.7.9.5
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 1/4] Fix coding style
2013-10-04 16:56 [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v4) Fabien Chouteau
@ 2013-10-04 16:57 ` Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 2/4] Improve Monitor disas with symbol lookup Fabien Chouteau
` (2 subsequent siblings)
3 siblings, 0 replies; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-04 16:57 UTC (permalink / raw)
Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
disas.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/disas.c b/disas.c
index 0203ef2..32407de 100644
--- a/disas.c
+++ b/disas.c
@@ -506,12 +506,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env,
return;
#endif
- for(i = 0; i < nb_insn; i++) {
- monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
+ for (i = 0; i < nb_insn; i++) {
+ monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
count = print_insn(pc, &s.info);
- monitor_printf(mon, "\n");
- if (count < 0)
- break;
+ monitor_printf(mon, "\n");
+ if (count < 0) {
+ break;
+ }
pc += count;
}
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 2/4] Improve Monitor disas with symbol lookup
2013-10-04 16:56 [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v4) Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 1/4] Fix coding style Fabien Chouteau
@ 2013-10-04 16:57 ` Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands Fabien Chouteau
3 siblings, 0 replies; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-04 16:57 UTC (permalink / raw)
Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
disas.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/disas.c b/disas.c
index 32407de..c83bf5b 100644
--- a/disas.c
+++ b/disas.c
@@ -507,7 +507,15 @@ void monitor_disas(Monitor *mon, CPUArchState *env,
#endif
for (i = 0; i < nb_insn; i++) {
- monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
+ const char *sym = lookup_symbol(pc);
+
+ monitor_printf(mon, "0x" TARGET_FMT_lx, pc);
+ if (sym[0] != '\0') {
+ monitor_printf(mon, " <%s>: ", sym);
+ } else {
+ monitor_printf(mon, ": ");
+ }
+
count = print_insn(pc, &s.info);
monitor_printf(mon, "\n");
if (count < 0) {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-04 16:56 [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v4) Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 1/4] Fix coding style Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 2/4] Improve Monitor disas with symbol lookup Fabien Chouteau
@ 2013-10-04 16:57 ` Fabien Chouteau
2013-10-04 17:49 ` Peter Maydell
2013-10-04 16:57 ` [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands Fabien Chouteau
3 siblings, 1 reply; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-04 16:57 UTC (permalink / raw)
Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
Everything has been moved to cpu specific directories (SPARC, PPC,
i386).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
include/monitor/monitor_def.h | 18 ++
include/qemu/typedefs.h | 1 +
include/qom/cpu.h | 3 +
monitor.c | 396 +----------------------------------------
target-i386/Makefile.objs | 2 +-
target-i386/cpu-qom.h | 1 +
target-i386/cpu.c | 7 +
target-i386/monitor.c | 62 +++++++
target-ppc/Makefile.objs | 2 +-
target-ppc/monitor.c | 234 ++++++++++++++++++++++++
target-ppc/translate_init.c | 8 +
target-sparc/Makefile.objs | 2 +-
target-sparc/cpu-qom.h | 1 -
target-sparc/cpu.c | 7 +
target-sparc/monitor.c | 138 ++++++++++++++
15 files changed, 490 insertions(+), 392 deletions(-)
create mode 100644 include/monitor/monitor_def.h
create mode 100644 target-i386/monitor.c
create mode 100644 target-ppc/monitor.c
create mode 100644 target-sparc/monitor.c
diff --git a/include/monitor/monitor_def.h b/include/monitor/monitor_def.h
new file mode 100644
index 0000000..7d4e3b6
--- /dev/null
+++ b/include/monitor/monitor_def.h
@@ -0,0 +1,18 @@
+#ifndef _MONITOR_DEF_H_
+#define _MONITOR_DEF_H_
+
+#include "cpu.h"
+
+CPUArchState *mon_get_cpu(void);
+
+#define MD_TLONG 0
+#define MD_I32 1
+
+typedef struct MonitorDef {
+ const char *name;
+ int offset;
+ target_long (*get_value)(const struct MonitorDef *md, int val);
+ int type;
+} MonitorDef;
+
+#endif /* ! _MONITOR_DEF_H_ */
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 3205540..4465fe8 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -13,6 +13,7 @@ typedef struct AioContext AioContext;
struct Monitor;
typedef struct Monitor Monitor;
typedef struct MigrationParams MigrationParams;
+typedef struct MonitorDef MonitorDef;
typedef struct Property Property;
typedef struct PropertyInfo PropertyInfo;
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 7739e00..07ad3ee 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -156,6 +156,7 @@ struct kvm_run;
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
* @next_cpu: Next CPU sharing TB cache.
* @kvm_fd: vCPU file descriptor for KVM.
+ * @monitor_defs array of register definitions for monitor functions
*
* State of one CPU core or thread.
*/
@@ -198,6 +199,8 @@ struct CPUState {
struct KVMState *kvm_state;
struct kvm_run *kvm_run;
+ const MonitorDef *monitor_defs;
+
/* TODO Move common fields from CPUArchState here. */
int cpu_index; /* used by alpha TCG */
uint32_t halted; /* used by alpha, cris, ppc TCG */
diff --git a/monitor.c b/monitor.c
index 74f3f1b..ce2c2af 100644
--- a/monitor.c
+++ b/monitor.c
@@ -37,6 +37,7 @@
#include "ui/qemu-spice.h"
#include "sysemu/sysemu.h"
#include "monitor/monitor.h"
+#include "monitor/monitor_def.h"
#include "monitor/readline.h"
#include "ui/console.h"
#include "sysemu/blockdev.h"
@@ -1096,7 +1097,7 @@ int monitor_set_cpu(int cpu_index)
return 0;
}
-static CPUArchState *mon_get_cpu(void)
+CPUArchState *mon_get_cpu(void)
{
if (!cur_mon->mon_cpu) {
monitor_set_cpu(0);
@@ -2969,392 +2970,6 @@ static const mon_cmd_t qmp_cmds[] = {
static const char *pch;
static sigjmp_buf expr_env;
-#define MD_TLONG 0
-#define MD_I32 1
-
-typedef struct MonitorDef {
- const char *name;
- int offset;
- target_long (*get_value)(const struct MonitorDef *md, int val);
- int type;
-} MonitorDef;
-
-#if defined(TARGET_I386)
-static target_long monitor_get_pc (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->eip + env->segs[R_CS].base;
-}
-#endif
-
-#if defined(TARGET_PPC)
-static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- unsigned int u;
- int i;
-
- u = 0;
- for (i = 0; i < 8; i++)
- u |= env->crf[i] << (32 - (4 * i));
-
- return u;
-}
-
-static target_long monitor_get_msr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->msr;
-}
-
-static target_long monitor_get_xer (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->xer;
-}
-
-static target_long monitor_get_decr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return cpu_ppc_load_decr(env);
-}
-
-static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return cpu_ppc_load_tbu(env);
-}
-
-static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return cpu_ppc_load_tbl(env);
-}
-#endif
-
-#if defined(TARGET_SPARC)
-#ifndef TARGET_SPARC64
-static target_long monitor_get_psr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
-
- return cpu_get_psr(env);
-}
-#endif
-
-static target_long monitor_get_reg(const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->regwptr[val];
-}
-#endif
-
-static const MonitorDef monitor_defs[] = {
-#ifdef TARGET_I386
-
-#define SEG(name, seg) \
- { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
- { name ".base", offsetof(CPUX86State, segs[seg].base) },\
- { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
-
- { "eax", offsetof(CPUX86State, regs[0]) },
- { "ecx", offsetof(CPUX86State, regs[1]) },
- { "edx", offsetof(CPUX86State, regs[2]) },
- { "ebx", offsetof(CPUX86State, regs[3]) },
- { "esp|sp", offsetof(CPUX86State, regs[4]) },
- { "ebp|fp", offsetof(CPUX86State, regs[5]) },
- { "esi", offsetof(CPUX86State, regs[6]) },
- { "edi", offsetof(CPUX86State, regs[7]) },
-#ifdef TARGET_X86_64
- { "r8", offsetof(CPUX86State, regs[8]) },
- { "r9", offsetof(CPUX86State, regs[9]) },
- { "r10", offsetof(CPUX86State, regs[10]) },
- { "r11", offsetof(CPUX86State, regs[11]) },
- { "r12", offsetof(CPUX86State, regs[12]) },
- { "r13", offsetof(CPUX86State, regs[13]) },
- { "r14", offsetof(CPUX86State, regs[14]) },
- { "r15", offsetof(CPUX86State, regs[15]) },
-#endif
- { "eflags", offsetof(CPUX86State, eflags) },
- { "eip", offsetof(CPUX86State, eip) },
- SEG("cs", R_CS)
- SEG("ds", R_DS)
- SEG("es", R_ES)
- SEG("ss", R_SS)
- SEG("fs", R_FS)
- SEG("gs", R_GS)
- { "pc", 0, monitor_get_pc, },
-#elif defined(TARGET_PPC)
- /* General purpose registers */
- { "r0", offsetof(CPUPPCState, gpr[0]) },
- { "r1", offsetof(CPUPPCState, gpr[1]) },
- { "r2", offsetof(CPUPPCState, gpr[2]) },
- { "r3", offsetof(CPUPPCState, gpr[3]) },
- { "r4", offsetof(CPUPPCState, gpr[4]) },
- { "r5", offsetof(CPUPPCState, gpr[5]) },
- { "r6", offsetof(CPUPPCState, gpr[6]) },
- { "r7", offsetof(CPUPPCState, gpr[7]) },
- { "r8", offsetof(CPUPPCState, gpr[8]) },
- { "r9", offsetof(CPUPPCState, gpr[9]) },
- { "r10", offsetof(CPUPPCState, gpr[10]) },
- { "r11", offsetof(CPUPPCState, gpr[11]) },
- { "r12", offsetof(CPUPPCState, gpr[12]) },
- { "r13", offsetof(CPUPPCState, gpr[13]) },
- { "r14", offsetof(CPUPPCState, gpr[14]) },
- { "r15", offsetof(CPUPPCState, gpr[15]) },
- { "r16", offsetof(CPUPPCState, gpr[16]) },
- { "r17", offsetof(CPUPPCState, gpr[17]) },
- { "r18", offsetof(CPUPPCState, gpr[18]) },
- { "r19", offsetof(CPUPPCState, gpr[19]) },
- { "r20", offsetof(CPUPPCState, gpr[20]) },
- { "r21", offsetof(CPUPPCState, gpr[21]) },
- { "r22", offsetof(CPUPPCState, gpr[22]) },
- { "r23", offsetof(CPUPPCState, gpr[23]) },
- { "r24", offsetof(CPUPPCState, gpr[24]) },
- { "r25", offsetof(CPUPPCState, gpr[25]) },
- { "r26", offsetof(CPUPPCState, gpr[26]) },
- { "r27", offsetof(CPUPPCState, gpr[27]) },
- { "r28", offsetof(CPUPPCState, gpr[28]) },
- { "r29", offsetof(CPUPPCState, gpr[29]) },
- { "r30", offsetof(CPUPPCState, gpr[30]) },
- { "r31", offsetof(CPUPPCState, gpr[31]) },
- /* Floating point registers */
- { "f0", offsetof(CPUPPCState, fpr[0]) },
- { "f1", offsetof(CPUPPCState, fpr[1]) },
- { "f2", offsetof(CPUPPCState, fpr[2]) },
- { "f3", offsetof(CPUPPCState, fpr[3]) },
- { "f4", offsetof(CPUPPCState, fpr[4]) },
- { "f5", offsetof(CPUPPCState, fpr[5]) },
- { "f6", offsetof(CPUPPCState, fpr[6]) },
- { "f7", offsetof(CPUPPCState, fpr[7]) },
- { "f8", offsetof(CPUPPCState, fpr[8]) },
- { "f9", offsetof(CPUPPCState, fpr[9]) },
- { "f10", offsetof(CPUPPCState, fpr[10]) },
- { "f11", offsetof(CPUPPCState, fpr[11]) },
- { "f12", offsetof(CPUPPCState, fpr[12]) },
- { "f13", offsetof(CPUPPCState, fpr[13]) },
- { "f14", offsetof(CPUPPCState, fpr[14]) },
- { "f15", offsetof(CPUPPCState, fpr[15]) },
- { "f16", offsetof(CPUPPCState, fpr[16]) },
- { "f17", offsetof(CPUPPCState, fpr[17]) },
- { "f18", offsetof(CPUPPCState, fpr[18]) },
- { "f19", offsetof(CPUPPCState, fpr[19]) },
- { "f20", offsetof(CPUPPCState, fpr[20]) },
- { "f21", offsetof(CPUPPCState, fpr[21]) },
- { "f22", offsetof(CPUPPCState, fpr[22]) },
- { "f23", offsetof(CPUPPCState, fpr[23]) },
- { "f24", offsetof(CPUPPCState, fpr[24]) },
- { "f25", offsetof(CPUPPCState, fpr[25]) },
- { "f26", offsetof(CPUPPCState, fpr[26]) },
- { "f27", offsetof(CPUPPCState, fpr[27]) },
- { "f28", offsetof(CPUPPCState, fpr[28]) },
- { "f29", offsetof(CPUPPCState, fpr[29]) },
- { "f30", offsetof(CPUPPCState, fpr[30]) },
- { "f31", offsetof(CPUPPCState, fpr[31]) },
- { "fpscr", offsetof(CPUPPCState, fpscr) },
- /* Next instruction pointer */
- { "nip|pc", offsetof(CPUPPCState, nip) },
- { "lr", offsetof(CPUPPCState, lr) },
- { "ctr", offsetof(CPUPPCState, ctr) },
- { "decr", 0, &monitor_get_decr, },
- { "ccr", 0, &monitor_get_ccr, },
- /* Machine state register */
- { "msr", 0, &monitor_get_msr, },
- { "xer", 0, &monitor_get_xer, },
- { "tbu", 0, &monitor_get_tbu, },
- { "tbl", 0, &monitor_get_tbl, },
- /* Segment registers */
- { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
- { "sr0", offsetof(CPUPPCState, sr[0]) },
- { "sr1", offsetof(CPUPPCState, sr[1]) },
- { "sr2", offsetof(CPUPPCState, sr[2]) },
- { "sr3", offsetof(CPUPPCState, sr[3]) },
- { "sr4", offsetof(CPUPPCState, sr[4]) },
- { "sr5", offsetof(CPUPPCState, sr[5]) },
- { "sr6", offsetof(CPUPPCState, sr[6]) },
- { "sr7", offsetof(CPUPPCState, sr[7]) },
- { "sr8", offsetof(CPUPPCState, sr[8]) },
- { "sr9", offsetof(CPUPPCState, sr[9]) },
- { "sr10", offsetof(CPUPPCState, sr[10]) },
- { "sr11", offsetof(CPUPPCState, sr[11]) },
- { "sr12", offsetof(CPUPPCState, sr[12]) },
- { "sr13", offsetof(CPUPPCState, sr[13]) },
- { "sr14", offsetof(CPUPPCState, sr[14]) },
- { "sr15", offsetof(CPUPPCState, sr[15]) },
- /* Too lazy to put BATs... */
- { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
-
- { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
- { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
- { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
- { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
- { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
- { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
- { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
- { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
- { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
- { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
- { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
- { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
- { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
- { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
- { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
- { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
- { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
- { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
- { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
- { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
- { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
- { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
- { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
- { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
- { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
- { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
- { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
- { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
- { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
- { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
- { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
- { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
- { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
- { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
- { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
- { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
- { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
- { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
- { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
- { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
- { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
- { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
- { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
- { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
- { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
- { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
- { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
- { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
- { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
- { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
- { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
- { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
- { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
- { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
- { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
- { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
- { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
- { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
- { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
- { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
- { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
- { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
- { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
- { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
- { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
- { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
-
-#elif defined(TARGET_SPARC)
- { "g0", offsetof(CPUSPARCState, gregs[0]) },
- { "g1", offsetof(CPUSPARCState, gregs[1]) },
- { "g2", offsetof(CPUSPARCState, gregs[2]) },
- { "g3", offsetof(CPUSPARCState, gregs[3]) },
- { "g4", offsetof(CPUSPARCState, gregs[4]) },
- { "g5", offsetof(CPUSPARCState, gregs[5]) },
- { "g6", offsetof(CPUSPARCState, gregs[6]) },
- { "g7", offsetof(CPUSPARCState, gregs[7]) },
- { "o0", 0, monitor_get_reg },
- { "o1", 1, monitor_get_reg },
- { "o2", 2, monitor_get_reg },
- { "o3", 3, monitor_get_reg },
- { "o4", 4, monitor_get_reg },
- { "o5", 5, monitor_get_reg },
- { "o6", 6, monitor_get_reg },
- { "o7", 7, monitor_get_reg },
- { "l0", 8, monitor_get_reg },
- { "l1", 9, monitor_get_reg },
- { "l2", 10, monitor_get_reg },
- { "l3", 11, monitor_get_reg },
- { "l4", 12, monitor_get_reg },
- { "l5", 13, monitor_get_reg },
- { "l6", 14, monitor_get_reg },
- { "l7", 15, monitor_get_reg },
- { "i0", 16, monitor_get_reg },
- { "i1", 17, monitor_get_reg },
- { "i2", 18, monitor_get_reg },
- { "i3", 19, monitor_get_reg },
- { "i4", 20, monitor_get_reg },
- { "i5", 21, monitor_get_reg },
- { "i6", 22, monitor_get_reg },
- { "i7", 23, monitor_get_reg },
- { "pc", offsetof(CPUSPARCState, pc) },
- { "npc", offsetof(CPUSPARCState, npc) },
- { "y", offsetof(CPUSPARCState, y) },
-#ifndef TARGET_SPARC64
- { "psr", 0, &monitor_get_psr, },
- { "wim", offsetof(CPUSPARCState, wim) },
-#endif
- { "tbr", offsetof(CPUSPARCState, tbr) },
- { "fsr", offsetof(CPUSPARCState, fsr) },
- { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
- { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
- { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
- { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
- { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
- { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
- { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
- { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
- { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
- { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
- { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
- { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
- { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
- { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
- { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
- { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
- { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
- { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
- { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
- { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
- { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
- { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
- { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
- { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
- { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
- { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
- { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
- { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
- { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
- { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
- { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
- { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
-#ifdef TARGET_SPARC64
- { "f32", offsetof(CPUSPARCState, fpr[16]) },
- { "f34", offsetof(CPUSPARCState, fpr[17]) },
- { "f36", offsetof(CPUSPARCState, fpr[18]) },
- { "f38", offsetof(CPUSPARCState, fpr[19]) },
- { "f40", offsetof(CPUSPARCState, fpr[20]) },
- { "f42", offsetof(CPUSPARCState, fpr[21]) },
- { "f44", offsetof(CPUSPARCState, fpr[22]) },
- { "f46", offsetof(CPUSPARCState, fpr[23]) },
- { "f48", offsetof(CPUSPARCState, fpr[24]) },
- { "f50", offsetof(CPUSPARCState, fpr[25]) },
- { "f52", offsetof(CPUSPARCState, fpr[26]) },
- { "f54", offsetof(CPUSPARCState, fpr[27]) },
- { "f56", offsetof(CPUSPARCState, fpr[28]) },
- { "f58", offsetof(CPUSPARCState, fpr[29]) },
- { "f60", offsetof(CPUSPARCState, fpr[30]) },
- { "f62", offsetof(CPUSPARCState, fpr[31]) },
- { "asi", offsetof(CPUSPARCState, asi) },
- { "pstate", offsetof(CPUSPARCState, pstate) },
- { "cansave", offsetof(CPUSPARCState, cansave) },
- { "canrestore", offsetof(CPUSPARCState, canrestore) },
- { "otherwin", offsetof(CPUSPARCState, otherwin) },
- { "wstate", offsetof(CPUSPARCState, wstate) },
- { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
- { "fprs", offsetof(CPUSPARCState, fprs) },
-#endif
-#endif
- { NULL },
-};
-
static void GCC_FMT_ATTR(2, 3) QEMU_NORETURN
expr_error(Monitor *mon, const char *fmt, ...)
{
@@ -3369,10 +2984,15 @@ expr_error(Monitor *mon, const char *fmt, ...)
/* return 0 if OK, -1 if not found */
static int get_monitor_def(target_long *pval, const char *name)
{
+ CPUState *cpu = ENV_GET_CPU(mon_get_cpu());
const MonitorDef *md;
void *ptr;
- for(md = monitor_defs; md->name != NULL; md++) {
+ if (cpu->monitor_defs == NULL) {
+ return -1;
+ }
+
+ for (md = cpu->monitor_defs; md->name != NULL; md++) {
if (compare_cmd(name, md->name)) {
if (md->get_value) {
*pval = md->get_value(md, md->offset);
diff --git a/target-i386/Makefile.objs b/target-i386/Makefile.objs
index da1fc40..839c8e6 100644
--- a/target-i386/Makefile.objs
+++ b/target-i386/Makefile.objs
@@ -2,7 +2,7 @@ obj-y += translate.o helper.o cpu.o
obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o
obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o
obj-y += gdbstub.o
-obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o
+obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o monitor.o
obj-$(CONFIG_KVM) += kvm.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-$(CONFIG_LINUX_USER) += ioport-user.o
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index f4fab15..cb90123 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -23,6 +23,7 @@
#include "qom/cpu.h"
#include "cpu.h"
#include "qapi/error.h"
+#include "monitor/monitor_def.h"
#ifdef TARGET_X86_64
#define TYPE_X86_CPU "x86_64-cpu"
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b682802..616b7da 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -22,6 +22,7 @@
#include <inttypes.h>
#include "cpu.h"
+#include "cpu-qom.h"
#include "sysemu/kvm.h"
#include "sysemu/cpus.h"
#include "topology.h"
@@ -47,7 +48,9 @@
#include "hw/xen/xen.h"
#include "hw/i386/apic_internal.h"
#endif
+#include "monitor/monitor_def.h"
+extern const MonitorDef i386_monitor_defs[];
/* Cache topology CPUID constants: */
@@ -2664,6 +2667,10 @@ static void x86_cpu_initfn(Object *obj)
cpu_set_debug_excp_handler(breakpoint_handler);
#endif
}
+
+#ifndef CONFIG_USER_ONLY
+ cs->monitor_defs = i386_monitor_defs;
+#endif
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
diff --git a/target-i386/monitor.c b/target-i386/monitor.c
new file mode 100644
index 0000000..c052d82
--- /dev/null
+++ b/target-i386/monitor.c
@@ -0,0 +1,62 @@
+/*
+ * i386 MonitorDef
+ *
+ * Copyright (c) 2013 AdaCore
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "monitor/monitor_def.h"
+
+static target_long monitor_get_pc(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->eip + env->segs[R_CS].base;
+}
+
+const MonitorDef i386_monitor_defs[] = {
+#define SEG(name, seg) \
+ { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
+ { name ".base", offsetof(CPUX86State, segs[seg].base) },\
+ { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
+
+ { "eax", offsetof(CPUX86State, regs[0]) },
+ { "ecx", offsetof(CPUX86State, regs[1]) },
+ { "edx", offsetof(CPUX86State, regs[2]) },
+ { "ebx", offsetof(CPUX86State, regs[3]) },
+ { "esp|sp", offsetof(CPUX86State, regs[4]) },
+ { "ebp|fp", offsetof(CPUX86State, regs[5]) },
+ { "esi", offsetof(CPUX86State, regs[6]) },
+ { "edi", offsetof(CPUX86State, regs[7]) },
+#ifdef TARGET_X86_64
+ { "r8", offsetof(CPUX86State, regs[8]) },
+ { "r9", offsetof(CPUX86State, regs[9]) },
+ { "r10", offsetof(CPUX86State, regs[10]) },
+ { "r11", offsetof(CPUX86State, regs[11]) },
+ { "r12", offsetof(CPUX86State, regs[12]) },
+ { "r13", offsetof(CPUX86State, regs[13]) },
+ { "r14", offsetof(CPUX86State, regs[14]) },
+ { "r15", offsetof(CPUX86State, regs[15]) },
+#endif
+ { "eflags", offsetof(CPUX86State, eflags) },
+ { "eip", offsetof(CPUX86State, eip) },
+ SEG("cs", R_CS)
+ SEG("ds", R_DS)
+ SEG("es", R_ES)
+ SEG("ss", R_SS)
+ SEG("fs", R_FS)
+ SEG("gs", R_GS)
+ { "pc", 0, monitor_get_pc, },
+ { NULL },
+};
diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs
index f72e399..802eb83 100644
--- a/target-ppc/Makefile.objs
+++ b/target-ppc/Makefile.objs
@@ -1,7 +1,7 @@
obj-y += cpu-models.o
obj-y += translate.o
ifeq ($(CONFIG_SOFTMMU),y)
-obj-y += machine.o mmu_helper.o mmu-hash32.o
+obj-y += machine.o mmu_helper.o mmu-hash32.o monitor.o
obj-$(TARGET_PPC64) += mmu-hash64.o
endif
obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
diff --git a/target-ppc/monitor.c b/target-ppc/monitor.c
new file mode 100644
index 0000000..6da3658
--- /dev/null
+++ b/target-ppc/monitor.c
@@ -0,0 +1,234 @@
+/*
+ * PPC MonitorDef
+ *
+ * Copyright (c) 2013 AdaCore
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "monitor/monitor_def.h"
+
+static target_long monitor_get_ccr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ unsigned int u;
+ int i;
+
+ u = 0;
+ for (i = 0; i < 8; i++) {
+ u |= env->crf[i] << (32 - (4 * i));
+ }
+
+ return u;
+}
+
+static target_long monitor_get_msr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->msr;
+}
+
+static target_long monitor_get_xer(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->xer;
+}
+
+static target_long monitor_get_decr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return cpu_ppc_load_decr(env);
+}
+
+static target_long monitor_get_tbu(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return cpu_ppc_load_tbu(env);
+}
+
+static target_long monitor_get_tbl(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return cpu_ppc_load_tbl(env);
+}
+
+const MonitorDef ppc_monitor_defs[] = {
+ /* General purpose registers */
+ { "r0", offsetof(CPUPPCState, gpr[0]) },
+ { "r1", offsetof(CPUPPCState, gpr[1]) },
+ { "r2", offsetof(CPUPPCState, gpr[2]) },
+ { "r3", offsetof(CPUPPCState, gpr[3]) },
+ { "r4", offsetof(CPUPPCState, gpr[4]) },
+ { "r5", offsetof(CPUPPCState, gpr[5]) },
+ { "r6", offsetof(CPUPPCState, gpr[6]) },
+ { "r7", offsetof(CPUPPCState, gpr[7]) },
+ { "r8", offsetof(CPUPPCState, gpr[8]) },
+ { "r9", offsetof(CPUPPCState, gpr[9]) },
+ { "r10", offsetof(CPUPPCState, gpr[10]) },
+ { "r11", offsetof(CPUPPCState, gpr[11]) },
+ { "r12", offsetof(CPUPPCState, gpr[12]) },
+ { "r13", offsetof(CPUPPCState, gpr[13]) },
+ { "r14", offsetof(CPUPPCState, gpr[14]) },
+ { "r15", offsetof(CPUPPCState, gpr[15]) },
+ { "r16", offsetof(CPUPPCState, gpr[16]) },
+ { "r17", offsetof(CPUPPCState, gpr[17]) },
+ { "r18", offsetof(CPUPPCState, gpr[18]) },
+ { "r19", offsetof(CPUPPCState, gpr[19]) },
+ { "r20", offsetof(CPUPPCState, gpr[20]) },
+ { "r21", offsetof(CPUPPCState, gpr[21]) },
+ { "r22", offsetof(CPUPPCState, gpr[22]) },
+ { "r23", offsetof(CPUPPCState, gpr[23]) },
+ { "r24", offsetof(CPUPPCState, gpr[24]) },
+ { "r25", offsetof(CPUPPCState, gpr[25]) },
+ { "r26", offsetof(CPUPPCState, gpr[26]) },
+ { "r27", offsetof(CPUPPCState, gpr[27]) },
+ { "r28", offsetof(CPUPPCState, gpr[28]) },
+ { "r29", offsetof(CPUPPCState, gpr[29]) },
+ { "r30", offsetof(CPUPPCState, gpr[30]) },
+ { "r31", offsetof(CPUPPCState, gpr[31]) },
+ /* Floating point registers */
+ { "f0", offsetof(CPUPPCState, fpr[0]) },
+ { "f1", offsetof(CPUPPCState, fpr[1]) },
+ { "f2", offsetof(CPUPPCState, fpr[2]) },
+ { "f3", offsetof(CPUPPCState, fpr[3]) },
+ { "f4", offsetof(CPUPPCState, fpr[4]) },
+ { "f5", offsetof(CPUPPCState, fpr[5]) },
+ { "f6", offsetof(CPUPPCState, fpr[6]) },
+ { "f7", offsetof(CPUPPCState, fpr[7]) },
+ { "f8", offsetof(CPUPPCState, fpr[8]) },
+ { "f9", offsetof(CPUPPCState, fpr[9]) },
+ { "f10", offsetof(CPUPPCState, fpr[10]) },
+ { "f11", offsetof(CPUPPCState, fpr[11]) },
+ { "f12", offsetof(CPUPPCState, fpr[12]) },
+ { "f13", offsetof(CPUPPCState, fpr[13]) },
+ { "f14", offsetof(CPUPPCState, fpr[14]) },
+ { "f15", offsetof(CPUPPCState, fpr[15]) },
+ { "f16", offsetof(CPUPPCState, fpr[16]) },
+ { "f17", offsetof(CPUPPCState, fpr[17]) },
+ { "f18", offsetof(CPUPPCState, fpr[18]) },
+ { "f19", offsetof(CPUPPCState, fpr[19]) },
+ { "f20", offsetof(CPUPPCState, fpr[20]) },
+ { "f21", offsetof(CPUPPCState, fpr[21]) },
+ { "f22", offsetof(CPUPPCState, fpr[22]) },
+ { "f23", offsetof(CPUPPCState, fpr[23]) },
+ { "f24", offsetof(CPUPPCState, fpr[24]) },
+ { "f25", offsetof(CPUPPCState, fpr[25]) },
+ { "f26", offsetof(CPUPPCState, fpr[26]) },
+ { "f27", offsetof(CPUPPCState, fpr[27]) },
+ { "f28", offsetof(CPUPPCState, fpr[28]) },
+ { "f29", offsetof(CPUPPCState, fpr[29]) },
+ { "f30", offsetof(CPUPPCState, fpr[30]) },
+ { "f31", offsetof(CPUPPCState, fpr[31]) },
+ { "fpscr", offsetof(CPUPPCState, fpscr) },
+ /* Next instruction pointer */
+ { "nip|pc", offsetof(CPUPPCState, nip) },
+ { "lr", offsetof(CPUPPCState, lr) },
+ { "ctr", offsetof(CPUPPCState, ctr) },
+ { "decr", 0, &monitor_get_decr, },
+ { "ccr", 0, &monitor_get_ccr, },
+ /* Machine state register */
+ { "msr", 0, &monitor_get_msr, },
+ { "xer", 0, &monitor_get_xer, },
+ { "tbu", 0, &monitor_get_tbu, },
+ { "tbl", 0, &monitor_get_tbl, },
+ /* Segment registers */
+ { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
+#if !defined(CONFIG_USER_ONLY)
+ { "sr0", offsetof(CPUPPCState, sr[0]) },
+ { "sr1", offsetof(CPUPPCState, sr[1]) },
+ { "sr2", offsetof(CPUPPCState, sr[2]) },
+ { "sr3", offsetof(CPUPPCState, sr[3]) },
+ { "sr4", offsetof(CPUPPCState, sr[4]) },
+ { "sr5", offsetof(CPUPPCState, sr[5]) },
+ { "sr6", offsetof(CPUPPCState, sr[6]) },
+ { "sr7", offsetof(CPUPPCState, sr[7]) },
+ { "sr8", offsetof(CPUPPCState, sr[8]) },
+ { "sr9", offsetof(CPUPPCState, sr[9]) },
+ { "sr10", offsetof(CPUPPCState, sr[10]) },
+ { "sr11", offsetof(CPUPPCState, sr[11]) },
+ { "sr12", offsetof(CPUPPCState, sr[12]) },
+ { "sr13", offsetof(CPUPPCState, sr[13]) },
+ { "sr14", offsetof(CPUPPCState, sr[14]) },
+ { "sr15", offsetof(CPUPPCState, sr[15]) },
+#endif /* Too lazy to put BATs... */
+ { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
+
+ { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
+ { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
+ { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
+ { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
+ { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
+ { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
+ { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
+ { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
+ { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
+ { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
+ { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
+ { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
+ { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
+ { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
+ { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
+ { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
+ { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
+ { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
+ { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
+ { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
+ { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
+ { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
+ { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
+ { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
+ { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
+ { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
+ { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
+ { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
+ { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
+ { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
+ { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
+ { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
+ { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
+ { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
+ { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
+ { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
+ { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
+ { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
+ { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
+ { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
+ { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
+ { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
+ { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
+ { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
+ { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
+ { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
+ { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
+ { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
+ { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
+ { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
+ { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
+ { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
+ { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
+ { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
+ { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
+ { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
+ { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
+ { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
+ { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
+ { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
+ { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
+ { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
+ { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
+ { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
+ { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
+ { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
+ { NULL },
+};
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d2645ba..fd97c15 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -25,14 +25,18 @@
#include "sysemu/arch_init.h"
#include "sysemu/cpus.h"
#include "cpu-models.h"
+#include "cpu-qom.h"
#include "mmu-hash32.h"
#include "mmu-hash64.h"
#include "qemu/error-report.h"
+#include "monitor/monitor_def.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
//#define PPC_DUMP_SPR_ACCESSES
+extern const MonitorDef ppc_monitor_defs[];
+
/* For user-mode emulation, we don't emulate any IRQ controller */
#if defined(CONFIG_USER_ONLY)
#define PPC_IRQ_INIT_FN(name) \
@@ -8542,6 +8546,10 @@ static void ppc_cpu_initfn(Object *obj)
}
#endif /* defined(TARGET_PPC64) */
+#if !defined(CONFIG_USER_ONLY)
+ cs->monitor_defs = ppc_monitor_defs;
+#endif
+
if (tcg_enabled()) {
ppc_translate_init();
}
diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs
index 1cd81cc..ec90569 100644
--- a/target-sparc/Makefile.objs
+++ b/target-sparc/Makefile.objs
@@ -1,4 +1,4 @@
-obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_SOFTMMU) += machine.o monitor.o
obj-y += translate.o helper.o cpu.o
obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
obj-$(TARGET_SPARC) += int32_helper.o
diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
index 8e3e0de..a2b83ad 100644
--- a/target-sparc/cpu-qom.h
+++ b/target-sparc/cpu-qom.h
@@ -21,7 +21,6 @@
#define QEMU_SPARC_CPU_QOM_H
#include "qom/cpu.h"
-#include "cpu.h"
#ifdef TARGET_SPARC64
#define TYPE_SPARC_CPU "sparc64-cpu"
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 47ce60d..1909107 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -18,6 +18,9 @@
*/
#include "cpu.h"
+#include "monitor/monitor_def.h"
+
+extern const MonitorDef sparc_monitor_defs[];
//#define DEBUG_FEATURES
@@ -757,6 +760,10 @@ static void sparc_cpu_initfn(Object *obj)
cs->env_ptr = env;
cpu_exec_init(env);
+#if !defined(CONFIG_USER_ONLY)
+ cs->monitor_defs = sparc_monitor_defs;
+#endif
+
if (tcg_enabled()) {
gen_intermediate_code_init(env);
}
diff --git a/target-sparc/monitor.c b/target-sparc/monitor.c
new file mode 100644
index 0000000..84e632a
--- /dev/null
+++ b/target-sparc/monitor.c
@@ -0,0 +1,138 @@
+/*
+ * SPARC MonitorDef
+ *
+ * Copyright (c) 2013 AdaCore
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "monitor/monitor_def.h"
+
+#ifndef TARGET_SPARC64
+static target_long monitor_get_psr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+
+ return cpu_get_psr(env);
+}
+#endif
+
+static target_long monitor_get_reg(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->regwptr[val];
+}
+
+const MonitorDef sparc_monitor_defs[] = {
+ { "g0", offsetof(CPUSPARCState, gregs[0]) },
+ { "g1", offsetof(CPUSPARCState, gregs[1]) },
+ { "g2", offsetof(CPUSPARCState, gregs[2]) },
+ { "g3", offsetof(CPUSPARCState, gregs[3]) },
+ { "g4", offsetof(CPUSPARCState, gregs[4]) },
+ { "g5", offsetof(CPUSPARCState, gregs[5]) },
+ { "g6", offsetof(CPUSPARCState, gregs[6]) },
+ { "g7", offsetof(CPUSPARCState, gregs[7]) },
+ { "o0", 0, monitor_get_reg },
+ { "o1", 1, monitor_get_reg },
+ { "o2", 2, monitor_get_reg },
+ { "o3", 3, monitor_get_reg },
+ { "o4", 4, monitor_get_reg },
+ { "o5", 5, monitor_get_reg },
+ { "o6", 6, monitor_get_reg },
+ { "o7", 7, monitor_get_reg },
+ { "l0", 8, monitor_get_reg },
+ { "l1", 9, monitor_get_reg },
+ { "l2", 10, monitor_get_reg },
+ { "l3", 11, monitor_get_reg },
+ { "l4", 12, monitor_get_reg },
+ { "l5", 13, monitor_get_reg },
+ { "l6", 14, monitor_get_reg },
+ { "l7", 15, monitor_get_reg },
+ { "i0", 16, monitor_get_reg },
+ { "i1", 17, monitor_get_reg },
+ { "i2", 18, monitor_get_reg },
+ { "i3", 19, monitor_get_reg },
+ { "i4", 20, monitor_get_reg },
+ { "i5", 21, monitor_get_reg },
+ { "i6", 22, monitor_get_reg },
+ { "i7", 23, monitor_get_reg },
+ { "pc", offsetof(CPUSPARCState, pc) },
+ { "npc", offsetof(CPUSPARCState, npc) },
+ { "y", offsetof(CPUSPARCState, y) },
+#ifndef TARGET_SPARC64
+ { "psr", 0, &monitor_get_psr, },
+ { "wim", offsetof(CPUSPARCState, wim) },
+#endif
+ { "tbr", offsetof(CPUSPARCState, tbr) },
+ { "fsr", offsetof(CPUSPARCState, fsr) },
+ { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
+ { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
+ { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
+ { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
+ { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
+ { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
+ { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
+ { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
+ { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
+ { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
+ { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
+ { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
+ { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
+ { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
+ { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
+ { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
+ { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
+ { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
+ { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
+ { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
+ { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
+ { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
+ { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
+ { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
+ { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
+ { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
+ { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
+ { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
+ { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
+ { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
+ { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
+ { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
+#ifdef TARGET_SPARC64
+ { "f32", offsetof(CPUSPARCState, fpr[16]) },
+ { "f34", offsetof(CPUSPARCState, fpr[17]) },
+ { "f36", offsetof(CPUSPARCState, fpr[18]) },
+ { "f38", offsetof(CPUSPARCState, fpr[19]) },
+ { "f40", offsetof(CPUSPARCState, fpr[20]) },
+ { "f42", offsetof(CPUSPARCState, fpr[21]) },
+ { "f44", offsetof(CPUSPARCState, fpr[22]) },
+ { "f46", offsetof(CPUSPARCState, fpr[23]) },
+ { "f48", offsetof(CPUSPARCState, fpr[24]) },
+ { "f50", offsetof(CPUSPARCState, fpr[25]) },
+ { "f52", offsetof(CPUSPARCState, fpr[26]) },
+ { "f54", offsetof(CPUSPARCState, fpr[27]) },
+ { "f56", offsetof(CPUSPARCState, fpr[28]) },
+ { "f58", offsetof(CPUSPARCState, fpr[29]) },
+ { "f60", offsetof(CPUSPARCState, fpr[30]) },
+ { "f62", offsetof(CPUSPARCState, fpr[31]) },
+ { "asi", offsetof(CPUSPARCState, asi) },
+ { "pstate", offsetof(CPUSPARCState, pstate) },
+ { "cansave", offsetof(CPUSPARCState, cansave) },
+ { "canrestore", offsetof(CPUSPARCState, canrestore) },
+ { "otherwin", offsetof(CPUSPARCState, otherwin) },
+ { "wstate", offsetof(CPUSPARCState, wstate) },
+ { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
+ { "fprs", offsetof(CPUSPARCState, fprs) },
+#endif
+ { NULL },
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands
2013-10-04 16:56 [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v4) Fabien Chouteau
` (2 preceding siblings ...)
2013-10-04 16:57 ` [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array Fabien Chouteau
@ 2013-10-04 16:57 ` Fabien Chouteau
2013-10-04 17:52 ` Peter Maydell
3 siblings, 1 reply; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-04 16:57 UTC (permalink / raw)
Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
target-arm/Makefile.objs | 2 +-
target-arm/cpu.c | 7 +++++++
target-arm/monitor.c | 40 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 target-arm/monitor.c
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index 6453f5c..6c3ec32 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -1,5 +1,5 @@
obj-y += arm-semi.o
-obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_SOFTMMU) += machine.o monitor.o
obj-$(CONFIG_KVM) += kvm.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += translate.o op_helper.o helper.o cpu.o
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d40f2a7..bb15ee8 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -26,6 +26,9 @@
#include "hw/arm/arm.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
+#include "monitor/monitor_def.h"
+
+extern const MonitorDef arm_monitor_defs[];
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -217,6 +220,10 @@ static void arm_cpu_initfn(Object *obj)
ARRAY_SIZE(cpu->gt_timer_outputs));
#endif
+#if !defined(CONFIG_USER_ONLY)
+ cs->monitor_defs = arm_monitor_defs;
+#endif
+
if (tcg_enabled() && !inited) {
inited = true;
arm_translate_init();
diff --git a/target-arm/monitor.c b/target-arm/monitor.c
new file mode 100644
index 0000000..0d68a14
--- /dev/null
+++ b/target-arm/monitor.c
@@ -0,0 +1,40 @@
+/*
+ * ARM MonitorDef
+ *
+ * Copyright (c) 2013 AdaCore
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "monitor/monitor_def.h"
+
+const MonitorDef arm_monitor_defs[] = {
+ { "r0", offsetof(CPUARMState, regs[0]) },
+ { "r1", offsetof(CPUARMState, regs[1]) },
+ { "r2", offsetof(CPUARMState, regs[2]) },
+ { "r3", offsetof(CPUARMState, regs[3]) },
+ { "r4", offsetof(CPUARMState, regs[4]) },
+ { "r5", offsetof(CPUARMState, regs[5]) },
+ { "r6", offsetof(CPUARMState, regs[6]) },
+ { "r7", offsetof(CPUARMState, regs[7]) },
+ { "r8", offsetof(CPUARMState, regs[8]) },
+ { "r9", offsetof(CPUARMState, regs[9]) },
+ { "r10", offsetof(CPUARMState, regs[10]) },
+ { "r11", offsetof(CPUARMState, regs[11]) },
+ { "r12", offsetof(CPUARMState, regs[12]) },
+ { "r13|sp", offsetof(CPUARMState, regs[13]) },
+ { "r14|lr", offsetof(CPUARMState, regs[14]) },
+ { "r15|pc", offsetof(CPUARMState, regs[15]) },
+ { NULL },
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-04 16:57 ` [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array Fabien Chouteau
@ 2013-10-04 17:49 ` Peter Maydell
2013-10-04 17:55 ` Andreas Färber
2013-10-07 10:11 ` Fabien Chouteau
0 siblings, 2 replies; 23+ messages in thread
From: Peter Maydell @ 2013-10-04 17:49 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: QEMU Developers, Andreas Färber, Luiz Capitulino
On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
> --- a/target-i386/cpu-qom.h
> +++ b/target-i386/cpu-qom.h
> @@ -23,6 +23,7 @@
> #include "qom/cpu.h"
> #include "cpu.h"
> #include "qapi/error.h"
> +#include "monitor/monitor_def.h"
> #ifdef TARGET_X86_64
> #define TYPE_X86_CPU "x86_64-cpu"
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index b682802..616b7da 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -22,6 +22,7 @@
> #include <inttypes.h>
>
> #include "cpu.h"
> +#include "cpu-qom.h"
> #include "sysemu/kvm.h"
> #include "sysemu/cpus.h"
> #include "topology.h"
> @@ -47,7 +48,9 @@
> #include "hw/xen/xen.h"
> #include "hw/i386/apic_internal.h"
> #endif
> +#include "monitor/monitor_def.h"
>
> +extern const MonitorDef i386_monitor_defs[];
Declare this in cpu-qom.h, rather than having an
extern declaration in a .c file.
> --- a/target-sparc/cpu-qom.h
> +++ b/target-sparc/cpu-qom.h
> @@ -21,7 +21,6 @@
> #define QEMU_SPARC_CPU_QOM_H
>
> #include "qom/cpu.h"
> -#include "cpu.h"
...why have you deleted this #include ?
>
> #ifdef TARGET_SPARC64
> #define TYPE_SPARC_CPU "sparc64-cpu"
thanks
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands
2013-10-04 16:57 ` [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands Fabien Chouteau
@ 2013-10-04 17:52 ` Peter Maydell
2013-10-07 10:12 ` Fabien Chouteau
0 siblings, 1 reply; 23+ messages in thread
From: Peter Maydell @ 2013-10-04 17:52 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: QEMU Developers, Andreas Färber, Luiz Capitulino
On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
>
> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> ---
> target-arm/Makefile.objs | 2 +-
> target-arm/cpu.c | 7 +++++++
> target-arm/monitor.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 48 insertions(+), 1 deletion(-)
> create mode 100644 target-arm/monitor.c
>
> diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
> index 6453f5c..6c3ec32 100644
> --- a/target-arm/Makefile.objs
> +++ b/target-arm/Makefile.objs
> @@ -1,5 +1,5 @@
> obj-y += arm-semi.o
> -obj-$(CONFIG_SOFTMMU) += machine.o
> +obj-$(CONFIG_SOFTMMU) += machine.o monitor.o
> obj-$(CONFIG_KVM) += kvm.o
> obj-$(CONFIG_NO_KVM) += kvm-stub.o
> obj-y += translate.o op_helper.o helper.o cpu.o
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index d40f2a7..bb15ee8 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -26,6 +26,9 @@
> #include "hw/arm/arm.h"
> #include "sysemu/sysemu.h"
> #include "sysemu/kvm.h"
> +#include "monitor/monitor_def.h"
> +
> +extern const MonitorDef arm_monitor_defs[];
>
> static void arm_cpu_set_pc(CPUState *cs, vaddr value)
> {
> @@ -217,6 +220,10 @@ static void arm_cpu_initfn(Object *obj)
> ARRAY_SIZE(cpu->gt_timer_outputs));
> #endif
>
> +#if !defined(CONFIG_USER_ONLY)
> + cs->monitor_defs = arm_monitor_defs;
> +#endif
> +
> if (tcg_enabled() && !inited) {
> inited = true;
> arm_translate_init();
> diff --git a/target-arm/monitor.c b/target-arm/monitor.c
> new file mode 100644
> index 0000000..0d68a14
> --- /dev/null
> +++ b/target-arm/monitor.c
> @@ -0,0 +1,40 @@
> +/*
> + * ARM MonitorDef
> + *
> + * Copyright (c) 2013 AdaCore
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "monitor/monitor_def.h"
> +
> +const MonitorDef arm_monitor_defs[] = {
> + { "r0", offsetof(CPUARMState, regs[0]) },
> + { "r1", offsetof(CPUARMState, regs[1]) },
These fields are all 32 bits, not target_long,
so they need to be marked as MD_I32. (If you build an
aarch64-softmmu target then it will have target_long be
64 bit but still support all the 32 bit CPUs, so it does
make a difference.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-04 17:49 ` Peter Maydell
@ 2013-10-04 17:55 ` Andreas Färber
2013-10-07 10:11 ` Fabien Chouteau
1 sibling, 0 replies; 23+ messages in thread
From: Andreas Färber @ 2013-10-04 17:55 UTC (permalink / raw)
To: Peter Maydell, Fabien Chouteau; +Cc: QEMU Developers, Luiz Capitulino
Am 04.10.2013 19:49, schrieb Peter Maydell:
> On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
>
>> --- a/target-sparc/cpu-qom.h
>> +++ b/target-sparc/cpu-qom.h
>> @@ -21,7 +21,6 @@
>> #define QEMU_SPARC_CPU_QOM_H
>>
>> #include "qom/cpu.h"
>> -#include "cpu.h"
>
> ...why have you deleted this #include ?
That's removing a circular include, I guess. If I get it as a separate
patch I would apply it immediately ... well, in quotes, sorry...
Andreas
>>
>> #ifdef TARGET_SPARC64
>> #define TYPE_SPARC_CPU "sparc64-cpu"
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-04 17:49 ` Peter Maydell
2013-10-04 17:55 ` Andreas Färber
@ 2013-10-07 10:11 ` Fabien Chouteau
2013-10-07 11:45 ` Peter Maydell
1 sibling, 1 reply; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-07 10:11 UTC (permalink / raw)
To: Peter Maydell; +Cc: Luiz Capitulino, QEMU Developers, Andreas Färber
On 10/04/2013 07:49 PM, Peter Maydell wrote:
> On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
> >> @@ -47,7 +48,9 @@
>> #include "hw/xen/xen.h"
>> #include "hw/i386/apic_internal.h"
>> #endif
>> +#include "monitor/monitor_def.h"
>>
>> +extern const MonitorDef i386_monitor_defs[];
>
> Declare this in cpu-qom.h, rather than having an
> extern declaration in a .c file.
>
I didn't manage to do that.
>
>> --- a/target-sparc/cpu-qom.h
>> +++ b/target-sparc/cpu-qom.h
>> @@ -21,7 +21,6 @@
>> #define QEMU_SPARC_CPU_QOM_H
>>
>> #include "qom/cpu.h"
>> -#include "cpu.h"
>
> ...why have you deleted this #include ?
>
I thought I added it myself, that's why I removed it.
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands
2013-10-04 17:52 ` Peter Maydell
@ 2013-10-07 10:12 ` Fabien Chouteau
0 siblings, 0 replies; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-07 10:12 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Andreas Färber, Luiz Capitulino
On 10/04/2013 07:52 PM, Peter Maydell wrote:
>> +#include "monitor/monitor_def.h"
>> +
>> +const MonitorDef arm_monitor_defs[] = {
>> + { "r0", offsetof(CPUARMState, regs[0]) },
>> + { "r1", offsetof(CPUARMState, regs[1]) },
>
> These fields are all 32 bits, not target_long,
> so they need to be marked as MD_I32. (If you build an
> aarch64-softmmu target then it will have target_long be
> 64 bit but still support all the 32 bit CPUs, so it does
> make a difference.)
>
OK, I'll mark them MD_I32.
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-07 10:11 ` Fabien Chouteau
@ 2013-10-07 11:45 ` Peter Maydell
2013-10-07 13:06 ` Fabien Chouteau
0 siblings, 1 reply; 23+ messages in thread
From: Peter Maydell @ 2013-10-07 11:45 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: Luiz Capitulino, QEMU Developers, Andreas Färber
On 7 October 2013 19:11, Fabien Chouteau <chouteau@adacore.com> wrote:
> On 10/04/2013 07:49 PM, Peter Maydell wrote:
>> On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
>> >> @@ -47,7 +48,9 @@
>>> #include "hw/xen/xen.h"
>>> #include "hw/i386/apic_internal.h"
>>> #endif
>>> +#include "monitor/monitor_def.h"
>>>
>>> +extern const MonitorDef i386_monitor_defs[];
>>
>> Declare this in cpu-qom.h, rather than having an
>> extern declaration in a .c file.
>>
>
> I didn't manage to do that.
If you just say "I couldn't make that work" with no details,
there isn't much I can say beyond "try harder" :-)
If you say *why* you couldn't get it to work then I'm more
likely to either (a) suggest an approach that will work or
(b) accept that it really does have to be that way...
thanks
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-07 11:45 ` Peter Maydell
@ 2013-10-07 13:06 ` Fabien Chouteau
2013-10-07 13:29 ` Peter Maydell
0 siblings, 1 reply; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-07 13:06 UTC (permalink / raw)
To: Peter Maydell; +Cc: Luiz Capitulino, QEMU Developers, Andreas Färber
On 10/07/2013 01:45 PM, Peter Maydell wrote:
> On 7 October 2013 19:11, Fabien Chouteau <chouteau@adacore.com> wrote:
>> On 10/04/2013 07:49 PM, Peter Maydell wrote:
>>> On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
>>>>> @@ -47,7 +48,9 @@
>>>> #include "hw/xen/xen.h"
>>>> #include "hw/i386/apic_internal.h"
>>>> #endif
>>>> +#include "monitor/monitor_def.h"
>>>>
>>>> +extern const MonitorDef i386_monitor_defs[];
>>>
>>> Declare this in cpu-qom.h, rather than having an
>>> extern declaration in a .c file.
>>>
>>
>> I didn't manage to do that.
>
> If you just say "I couldn't make that work" with no details,
> there isn't much I can say beyond "try harder" :-)
> If you say *why* you couldn't get it to work then I'm more
> likely to either (a) suggest an approach that will work or
> (b) accept that it really does have to be that way...
>
Sorry I sent the email too quickly. It looks like a circular dependency
In file included from /home/chouteau/src/qemu-main/target-arm/cpu.h:294:0,
from /home/chouteau/src/qemu-main/include/monitor/monitor_def.h:4,
from /home/chouteau/src/qemu-main/target-arm/monitor.c:20:
/home/chouteau/src/qemu-main/target-arm/cpu-qom.h:184:25: error: array type has incomplete element type
make[1]: *** [target-arm/monitor.o] Error 1
monitor_def.h -> cpu.h -> cpu-qom.h -.
^ |
|__________________________________/
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-07 13:06 ` Fabien Chouteau
@ 2013-10-07 13:29 ` Peter Maydell
2013-10-07 14:40 ` Fabien Chouteau
0 siblings, 1 reply; 23+ messages in thread
From: Peter Maydell @ 2013-10-07 13:29 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: Luiz Capitulino, QEMU Developers, Andreas Färber
On 7 October 2013 22:06, Fabien Chouteau <chouteau@adacore.com> wrote:
> On 10/07/2013 01:45 PM, Peter Maydell wrote:
>> On 7 October 2013 19:11, Fabien Chouteau <chouteau@adacore.com> wrote:
>>> On 10/04/2013 07:49 PM, Peter Maydell wrote:
>>>> On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
>>>>> +extern const MonitorDef i386_monitor_defs[];
>>>>
>>>> Declare this in cpu-qom.h, rather than having an
>>>> extern declaration in a .c file.
> Sorry I sent the email too quickly. It looks like a circular dependency
>
> In file included from /home/chouteau/src/qemu-main/target-arm/cpu.h:294:0,
> from /home/chouteau/src/qemu-main/include/monitor/monitor_def.h:4,
> from /home/chouteau/src/qemu-main/target-arm/monitor.c:20:
> /home/chouteau/src/qemu-main/target-arm/cpu-qom.h:184:25: error: array type has incomplete element type
> make[1]: *** [target-arm/monitor.o] Error 1
I think you should be able to declare it as
extern const MonitorDef *i386_monitor_defs;
then you don't need to include monitor_def.h from cpu-qom.h.
(untested, but the typedef should be sufficient for this)
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-07 13:29 ` Peter Maydell
@ 2013-10-07 14:40 ` Fabien Chouteau
0 siblings, 0 replies; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-07 14:40 UTC (permalink / raw)
To: Peter Maydell; +Cc: Luiz Capitulino, QEMU Developers, Andreas Färber
On 10/07/2013 03:29 PM, Peter Maydell wrote:
> On 7 October 2013 22:06, Fabien Chouteau <chouteau@adacore.com> wrote:
>> On 10/07/2013 01:45 PM, Peter Maydell wrote:
>>> On 7 October 2013 19:11, Fabien Chouteau <chouteau@adacore.com> wrote:
>>>> On 10/04/2013 07:49 PM, Peter Maydell wrote:
>>>>> On 5 October 2013 01:57, Fabien Chouteau <chouteau@adacore.com> wrote:
>>>>>> +extern const MonitorDef i386_monitor_defs[];
>>>>>
>>>>> Declare this in cpu-qom.h, rather than having an
>>>>> extern declaration in a .c file.
>
>> Sorry I sent the email too quickly. It looks like a circular dependency
>>
>> In file included from /home/chouteau/src/qemu-main/target-arm/cpu.h:294:0,
>> from /home/chouteau/src/qemu-main/include/monitor/monitor_def.h:4,
>> from /home/chouteau/src/qemu-main/target-arm/monitor.c:20:
>> /home/chouteau/src/qemu-main/target-arm/cpu-qom.h:184:25: error: array type has incomplete element type
>> make[1]: *** [target-arm/monitor.o] Error 1
>
> I think you should be able to declare it as
> extern const MonitorDef *i386_monitor_defs;
>
> then you don't need to include monitor_def.h from cpu-qom.h.
> (untested, but the typedef should be sufficient for this)
>
/home/chouteau/src/qemu-main/target-arm/monitor.c:22:19: error: conflicting types for ‘arm_monitor_defs’
/home/chouteau/src/qemu-main/target-arm/cpu-qom.h:183:26: note: previous declaration of ‘arm_monitor_defs’ was here
cpu-qom.h is indirectly included in target-arm/monitor.c
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-01 15:21 ` Peter Maydell
@ 2013-10-01 16:13 ` Fabien Chouteau
0 siblings, 0 replies; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-01 16:13 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Luiz Capitulino, Andreas Färber, Richard Henderson
On 10/01/2013 05:21 PM, Peter Maydell wrote:
> The declaration should go in cpu-qom.h (again, compare
> the gdb stuff), and it should be called "arm_monitor_defs",
> "ppc_monitor_defs" etc, not arch_monitor_defs. (This
> avoids issues if we ever manage to compile more than one
> target CPU into a single qemu binary, and again, it follows
> existing conventions).
>
monitor.h drag a lot of thing...
In file included from /home/chouteau/src/qemu-main/include/monitor/monitor.h:7:0,
from /home/chouteau/src/qemu-main/target-i386/cpu-qom.h:26,
from /home/chouteau/src/qemu-main/target-i386/cpu.h:917,
from /home/chouteau/src/qemu-main/include/qemu-common.h:116,
from /home/chouteau/src/qemu-main/exec.c:27:
/home/chouteau/src/qemu-main/include/block/block.h:187:59: error: unknown type name ‘QEMUIOVector’
Maybe MonitorDef can be in a specific file include/monitor/monitordef.h?
included by monitor.c target-*/monitor.c and target-*/cpu.c
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-01 15:13 ` Richard Henderson
@ 2013-10-01 15:21 ` Peter Maydell
2013-10-01 16:13 ` Fabien Chouteau
0 siblings, 1 reply; 23+ messages in thread
From: Peter Maydell @ 2013-10-01 15:21 UTC (permalink / raw)
To: Richard Henderson
Cc: Andreas Färber, QEMU Developers, Fabien Chouteau, Luiz Capitulino
On 2 October 2013 00:13, Richard Henderson <rth@twiddle.net> wrote:
> On 10/01/2013 07:28 AM, Fabien Chouteau wrote:
>> On 10/01/2013 04:00 AM, Richard Henderson wrote:
>>> On 09/30/2013 08:57 AM, Fabien Chouteau wrote:
>>>> +extern const MonitorDef arch_monitor_defs[];
>>>
>>> This is supplied by target-foo/monitor.c, right?
>>> Why in the world is it declared in generic code?
>>>
>>
>> Yes, why?
>>
>>> Especially if it's only ever accessed via the
>>> cpu->monitor_defs member?
>>>
>>
>> To begin with, I though I'd put in in each target-*/cpu.c, then having
>> it at only one place seemed more clean. I'm open to any suggestion.
>>
>
> If you put it in a global header like that, it looks like the array is
> part of the generic interface. But it isn't -- only the monitor_defs
> member is.
>
> If it's declared in any header at all, as opposed to static and local
> to cpu.c (why was a new monitor.c file chosen?)
Keeps monitor specific stuff in one file for the target and
avoids cpu.c gradually bloating into something enormous.
Compare use of gdbstub.c for the gdb stub related target
specific functions.
The declaration should go in cpu-qom.h (again, compare
the gdb stuff), and it should be called "arm_monitor_defs",
"ppc_monitor_defs" etc, not arch_monitor_defs. (This
avoids issues if we ever manage to compile more than one
target CPU into a single qemu binary, and again, it follows
existing conventions).
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-01 14:28 ` Fabien Chouteau
@ 2013-10-01 15:13 ` Richard Henderson
2013-10-01 15:21 ` Peter Maydell
0 siblings, 1 reply; 23+ messages in thread
From: Richard Henderson @ 2013-10-01 15:13 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
On 10/01/2013 07:28 AM, Fabien Chouteau wrote:
> On 10/01/2013 04:00 AM, Richard Henderson wrote:
>> On 09/30/2013 08:57 AM, Fabien Chouteau wrote:
>>> +extern const MonitorDef arch_monitor_defs[];
>>
>> This is supplied by target-foo/monitor.c, right?
>> Why in the world is it declared in generic code?
>>
>
> Yes, why?
>
>> Especially if it's only ever accessed via the
>> cpu->monitor_defs member?
>>
>
> To begin with, I though I'd put in in each target-*/cpu.c, then having
> it at only one place seemed more clean. I'm open to any suggestion.
>
If you put it in a global header like that, it looks like the array is
part of the generic interface. But it isn't -- only the monitor_defs
member is.
If it's declared in any header at all, as opposed to static and local
to cpu.c (why was a new monitor.c file chosen?), it should go into
target-foo/cpu.h, where most of the other cpu-specific declarations go.
r~
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-01 14:23 ` Fabien Chouteau
@ 2013-10-01 14:49 ` Peter Maydell
0 siblings, 0 replies; 23+ messages in thread
From: Peter Maydell @ 2013-10-01 14:49 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: Luiz Capitulino, QEMU Developers, Andreas Färber
On 1 October 2013 23:23, Fabien Chouteau <chouteau@adacore.com> wrote:
> On 10/01/2013 03:08 AM, Peter Maydell wrote:
>> I like this generally, but this detail is wrong. These changes
>> mean that these registers (and many others) are now described
>> as being int64_t wide rather than target_long wide, so you'll
>> find that on 32 bit x86 they will read/write incorrectly.
>> This is why I suggested that you need to have target-i386/monitor.c
>> do an
>> #if TARGET_LONG_BITS == 32
>> #define MD_TLONG MD_I32
>> #else
>> #define MD_TLONG MD_I64
>> #endif
>>
>> and then specifically mark these fields as MD_TLONG.
>
> This seems complicated. Is there a way to use target_long in monitor.h?
I would prefer it if we didn't, because the monitor should not depend
on target-specifics. So the monitor's interface to the CPU dependent
parts should expose basic "always the same" types, and if a particular
CPU happens to have CPU struct fields which are sometimes 32 bit
and sometimes 64 bit then it has to deal with them itself. (Not every
CPU has that kind of field.)
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-01 2:00 ` Richard Henderson
@ 2013-10-01 14:28 ` Fabien Chouteau
2013-10-01 15:13 ` Richard Henderson
0 siblings, 1 reply; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-01 14:28 UTC (permalink / raw)
To: Richard Henderson; +Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
On 10/01/2013 04:00 AM, Richard Henderson wrote:
> On 09/30/2013 08:57 AM, Fabien Chouteau wrote:
>> +extern const MonitorDef arch_monitor_defs[];
>
> This is supplied by target-foo/monitor.c, right?
> Why in the world is it declared in generic code?
>
Yes, why?
> Especially if it's only ever accessed via the
> cpu->monitor_defs member?
>
To begin with, I though I'd put in in each target-*/cpu.c, then having
it at only one place seemed more clean. I'm open to any suggestion.
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-10-01 1:08 ` Peter Maydell
@ 2013-10-01 14:23 ` Fabien Chouteau
2013-10-01 14:49 ` Peter Maydell
0 siblings, 1 reply; 23+ messages in thread
From: Fabien Chouteau @ 2013-10-01 14:23 UTC (permalink / raw)
To: Peter Maydell; +Cc: Luiz Capitulino, QEMU Developers, Andreas Färber
On 10/01/2013 03:08 AM, Peter Maydell wrote:
> On 1 October 2013 00:57, Fabien Chouteau <chouteau@adacore.com> wrote:
>
>> +#define MD_I64 0
>> +#define MD_I32 1
>
>> -#define MD_TLONG 0
>> -#define MD_I32 1
>
>> - { "eax", offsetof(CPUX86State, regs[0]) },
>> - { "ecx", offsetof(CPUX86State, regs[1]) },
>
>> + { "eax", offsetof(CPUX86State, regs[0]) },
>> + { "ecx", offsetof(CPUX86State, regs[1]) },
>
> I like this generally, but this detail is wrong. These changes
> mean that these registers (and many others) are now described
> as being int64_t wide rather than target_long wide, so you'll
> find that on 32 bit x86 they will read/write incorrectly.
> This is why I suggested that you need to have target-i386/monitor.c
> do an
> #if TARGET_LONG_BITS == 32
> #define MD_TLONG MD_I32
> #else
> #define MD_TLONG MD_I64
> #endif
>
> and then specifically mark these fields as MD_TLONG.
This seems complicated. Is there a way to use target_long in monitor.h?
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-09-30 15:57 ` [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array Fabien Chouteau
2013-10-01 1:08 ` Peter Maydell
@ 2013-10-01 2:00 ` Richard Henderson
2013-10-01 14:28 ` Fabien Chouteau
1 sibling, 1 reply; 23+ messages in thread
From: Richard Henderson @ 2013-10-01 2:00 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: peter.maydell, lcapitulino, qemu-devel, afaerber
On 09/30/2013 08:57 AM, Fabien Chouteau wrote:
> +extern const MonitorDef arch_monitor_defs[];
This is supplied by target-foo/monitor.c, right?
Why in the world is it declared in generic code?
Especially if it's only ever accessed via the
cpu->monitor_defs member?
r~
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-09-30 15:57 ` [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array Fabien Chouteau
@ 2013-10-01 1:08 ` Peter Maydell
2013-10-01 14:23 ` Fabien Chouteau
2013-10-01 2:00 ` Richard Henderson
1 sibling, 1 reply; 23+ messages in thread
From: Peter Maydell @ 2013-10-01 1:08 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: QEMU Developers, Andreas Färber, Luiz Capitulino
On 1 October 2013 00:57, Fabien Chouteau <chouteau@adacore.com> wrote:
> +#define MD_I64 0
> +#define MD_I32 1
> -#define MD_TLONG 0
> -#define MD_I32 1
> - { "eax", offsetof(CPUX86State, regs[0]) },
> - { "ecx", offsetof(CPUX86State, regs[1]) },
> + { "eax", offsetof(CPUX86State, regs[0]) },
> + { "ecx", offsetof(CPUX86State, regs[1]) },
I like this generally, but this detail is wrong. These changes
mean that these registers (and many others) are now described
as being int64_t wide rather than target_long wide, so you'll
find that on 32 bit x86 they will read/write incorrectly.
This is why I suggested that you need to have target-i386/monitor.c
do an
#if TARGET_LONG_BITS == 32
#define MD_TLONG MD_I32
#else
#define MD_TLONG MD_I64
#endif
and then specifically mark these fields as MD_TLONG.
(We could also get rid of that awkward mon_get_cpu()
which is the only thing in monitor.h that has to be guarded
by NEED_CPU_H, by having the function prototype for
the callback functions just take a CPUState* (nb: not
a CPUArchState*) rather than having them all call
mon_get_cpu. But we can do that in another patch
I guess.)
-- PMM
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array
2013-09-30 15:57 [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v3) Fabien Chouteau
@ 2013-09-30 15:57 ` Fabien Chouteau
2013-10-01 1:08 ` Peter Maydell
2013-10-01 2:00 ` Richard Henderson
0 siblings, 2 replies; 23+ messages in thread
From: Fabien Chouteau @ 2013-09-30 15:57 UTC (permalink / raw)
Cc: peter.maydell, qemu-devel, afaerber, lcapitulino
Everything has been moved to cpu specific directories (SPARC, PPC,
i386).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
include/monitor/monitor.h | 16 ++
include/qemu/typedefs.h | 1 +
include/qom/cpu.h | 3 +
monitor.c | 399 +------------------------------------------
target-i386/Makefile.objs | 2 +-
target-i386/cpu.c | 6 +-
target-i386/monitor.c | 63 +++++++
target-ppc/Makefile.objs | 2 +-
target-ppc/monitor.c | 234 +++++++++++++++++++++++++
target-ppc/translate_init.c | 5 +
target-sparc/Makefile.objs | 2 +-
target-sparc/cpu.c | 5 +
target-sparc/monitor.c | 138 +++++++++++++++
13 files changed, 482 insertions(+), 394 deletions(-)
create mode 100644 target-i386/monitor.c
create mode 100644 target-ppc/monitor.c
create mode 100644 target-sparc/monitor.c
diff --git a/include/monitor/monitor.h b/include/monitor/monitor.h
index 10fa0e3..208ed76 100644
--- a/include/monitor/monitor.h
+++ b/include/monitor/monitor.h
@@ -7,6 +7,22 @@
#include "block/block.h"
#include "monitor/readline.h"
+#ifdef NEED_CPU_H
+CPUArchState *mon_get_cpu(void);
+#endif
+
+#define MD_I64 0
+#define MD_I32 1
+
+typedef struct MonitorDef {
+ const char *name;
+ int offset;
+ uint64_t (*get_value)(const struct MonitorDef *md, int val);
+ int type;
+} MonitorDef;
+
+extern const MonitorDef arch_monitor_defs[];
+
extern Monitor *cur_mon;
extern Monitor *default_mon;
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 3205540..4465fe8 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -13,6 +13,7 @@ typedef struct AioContext AioContext;
struct Monitor;
typedef struct Monitor Monitor;
typedef struct MigrationParams MigrationParams;
+typedef struct MonitorDef MonitorDef;
typedef struct Property Property;
typedef struct PropertyInfo PropertyInfo;
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 7739e00..07ad3ee 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -156,6 +156,7 @@ struct kvm_run;
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
* @next_cpu: Next CPU sharing TB cache.
* @kvm_fd: vCPU file descriptor for KVM.
+ * @monitor_defs array of register definitions for monitor functions
*
* State of one CPU core or thread.
*/
@@ -198,6 +199,8 @@ struct CPUState {
struct KVMState *kvm_state;
struct kvm_run *kvm_run;
+ const MonitorDef *monitor_defs;
+
/* TODO Move common fields from CPUArchState here. */
int cpu_index; /* used by alpha TCG */
uint32_t halted; /* used by alpha, cris, ppc TCG */
diff --git a/monitor.c b/monitor.c
index 74f3f1b..059fc72 100644
--- a/monitor.c
+++ b/monitor.c
@@ -1096,7 +1096,7 @@ int monitor_set_cpu(int cpu_index)
return 0;
}
-static CPUArchState *mon_get_cpu(void)
+CPUArchState *mon_get_cpu(void)
{
if (!cur_mon->mon_cpu) {
monitor_set_cpu(0);
@@ -2969,392 +2969,6 @@ static const mon_cmd_t qmp_cmds[] = {
static const char *pch;
static sigjmp_buf expr_env;
-#define MD_TLONG 0
-#define MD_I32 1
-
-typedef struct MonitorDef {
- const char *name;
- int offset;
- target_long (*get_value)(const struct MonitorDef *md, int val);
- int type;
-} MonitorDef;
-
-#if defined(TARGET_I386)
-static target_long monitor_get_pc (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->eip + env->segs[R_CS].base;
-}
-#endif
-
-#if defined(TARGET_PPC)
-static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- unsigned int u;
- int i;
-
- u = 0;
- for (i = 0; i < 8; i++)
- u |= env->crf[i] << (32 - (4 * i));
-
- return u;
-}
-
-static target_long monitor_get_msr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->msr;
-}
-
-static target_long monitor_get_xer (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->xer;
-}
-
-static target_long monitor_get_decr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return cpu_ppc_load_decr(env);
-}
-
-static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return cpu_ppc_load_tbu(env);
-}
-
-static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return cpu_ppc_load_tbl(env);
-}
-#endif
-
-#if defined(TARGET_SPARC)
-#ifndef TARGET_SPARC64
-static target_long monitor_get_psr (const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
-
- return cpu_get_psr(env);
-}
-#endif
-
-static target_long monitor_get_reg(const struct MonitorDef *md, int val)
-{
- CPUArchState *env = mon_get_cpu();
- return env->regwptr[val];
-}
-#endif
-
-static const MonitorDef monitor_defs[] = {
-#ifdef TARGET_I386
-
-#define SEG(name, seg) \
- { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
- { name ".base", offsetof(CPUX86State, segs[seg].base) },\
- { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
-
- { "eax", offsetof(CPUX86State, regs[0]) },
- { "ecx", offsetof(CPUX86State, regs[1]) },
- { "edx", offsetof(CPUX86State, regs[2]) },
- { "ebx", offsetof(CPUX86State, regs[3]) },
- { "esp|sp", offsetof(CPUX86State, regs[4]) },
- { "ebp|fp", offsetof(CPUX86State, regs[5]) },
- { "esi", offsetof(CPUX86State, regs[6]) },
- { "edi", offsetof(CPUX86State, regs[7]) },
-#ifdef TARGET_X86_64
- { "r8", offsetof(CPUX86State, regs[8]) },
- { "r9", offsetof(CPUX86State, regs[9]) },
- { "r10", offsetof(CPUX86State, regs[10]) },
- { "r11", offsetof(CPUX86State, regs[11]) },
- { "r12", offsetof(CPUX86State, regs[12]) },
- { "r13", offsetof(CPUX86State, regs[13]) },
- { "r14", offsetof(CPUX86State, regs[14]) },
- { "r15", offsetof(CPUX86State, regs[15]) },
-#endif
- { "eflags", offsetof(CPUX86State, eflags) },
- { "eip", offsetof(CPUX86State, eip) },
- SEG("cs", R_CS)
- SEG("ds", R_DS)
- SEG("es", R_ES)
- SEG("ss", R_SS)
- SEG("fs", R_FS)
- SEG("gs", R_GS)
- { "pc", 0, monitor_get_pc, },
-#elif defined(TARGET_PPC)
- /* General purpose registers */
- { "r0", offsetof(CPUPPCState, gpr[0]) },
- { "r1", offsetof(CPUPPCState, gpr[1]) },
- { "r2", offsetof(CPUPPCState, gpr[2]) },
- { "r3", offsetof(CPUPPCState, gpr[3]) },
- { "r4", offsetof(CPUPPCState, gpr[4]) },
- { "r5", offsetof(CPUPPCState, gpr[5]) },
- { "r6", offsetof(CPUPPCState, gpr[6]) },
- { "r7", offsetof(CPUPPCState, gpr[7]) },
- { "r8", offsetof(CPUPPCState, gpr[8]) },
- { "r9", offsetof(CPUPPCState, gpr[9]) },
- { "r10", offsetof(CPUPPCState, gpr[10]) },
- { "r11", offsetof(CPUPPCState, gpr[11]) },
- { "r12", offsetof(CPUPPCState, gpr[12]) },
- { "r13", offsetof(CPUPPCState, gpr[13]) },
- { "r14", offsetof(CPUPPCState, gpr[14]) },
- { "r15", offsetof(CPUPPCState, gpr[15]) },
- { "r16", offsetof(CPUPPCState, gpr[16]) },
- { "r17", offsetof(CPUPPCState, gpr[17]) },
- { "r18", offsetof(CPUPPCState, gpr[18]) },
- { "r19", offsetof(CPUPPCState, gpr[19]) },
- { "r20", offsetof(CPUPPCState, gpr[20]) },
- { "r21", offsetof(CPUPPCState, gpr[21]) },
- { "r22", offsetof(CPUPPCState, gpr[22]) },
- { "r23", offsetof(CPUPPCState, gpr[23]) },
- { "r24", offsetof(CPUPPCState, gpr[24]) },
- { "r25", offsetof(CPUPPCState, gpr[25]) },
- { "r26", offsetof(CPUPPCState, gpr[26]) },
- { "r27", offsetof(CPUPPCState, gpr[27]) },
- { "r28", offsetof(CPUPPCState, gpr[28]) },
- { "r29", offsetof(CPUPPCState, gpr[29]) },
- { "r30", offsetof(CPUPPCState, gpr[30]) },
- { "r31", offsetof(CPUPPCState, gpr[31]) },
- /* Floating point registers */
- { "f0", offsetof(CPUPPCState, fpr[0]) },
- { "f1", offsetof(CPUPPCState, fpr[1]) },
- { "f2", offsetof(CPUPPCState, fpr[2]) },
- { "f3", offsetof(CPUPPCState, fpr[3]) },
- { "f4", offsetof(CPUPPCState, fpr[4]) },
- { "f5", offsetof(CPUPPCState, fpr[5]) },
- { "f6", offsetof(CPUPPCState, fpr[6]) },
- { "f7", offsetof(CPUPPCState, fpr[7]) },
- { "f8", offsetof(CPUPPCState, fpr[8]) },
- { "f9", offsetof(CPUPPCState, fpr[9]) },
- { "f10", offsetof(CPUPPCState, fpr[10]) },
- { "f11", offsetof(CPUPPCState, fpr[11]) },
- { "f12", offsetof(CPUPPCState, fpr[12]) },
- { "f13", offsetof(CPUPPCState, fpr[13]) },
- { "f14", offsetof(CPUPPCState, fpr[14]) },
- { "f15", offsetof(CPUPPCState, fpr[15]) },
- { "f16", offsetof(CPUPPCState, fpr[16]) },
- { "f17", offsetof(CPUPPCState, fpr[17]) },
- { "f18", offsetof(CPUPPCState, fpr[18]) },
- { "f19", offsetof(CPUPPCState, fpr[19]) },
- { "f20", offsetof(CPUPPCState, fpr[20]) },
- { "f21", offsetof(CPUPPCState, fpr[21]) },
- { "f22", offsetof(CPUPPCState, fpr[22]) },
- { "f23", offsetof(CPUPPCState, fpr[23]) },
- { "f24", offsetof(CPUPPCState, fpr[24]) },
- { "f25", offsetof(CPUPPCState, fpr[25]) },
- { "f26", offsetof(CPUPPCState, fpr[26]) },
- { "f27", offsetof(CPUPPCState, fpr[27]) },
- { "f28", offsetof(CPUPPCState, fpr[28]) },
- { "f29", offsetof(CPUPPCState, fpr[29]) },
- { "f30", offsetof(CPUPPCState, fpr[30]) },
- { "f31", offsetof(CPUPPCState, fpr[31]) },
- { "fpscr", offsetof(CPUPPCState, fpscr) },
- /* Next instruction pointer */
- { "nip|pc", offsetof(CPUPPCState, nip) },
- { "lr", offsetof(CPUPPCState, lr) },
- { "ctr", offsetof(CPUPPCState, ctr) },
- { "decr", 0, &monitor_get_decr, },
- { "ccr", 0, &monitor_get_ccr, },
- /* Machine state register */
- { "msr", 0, &monitor_get_msr, },
- { "xer", 0, &monitor_get_xer, },
- { "tbu", 0, &monitor_get_tbu, },
- { "tbl", 0, &monitor_get_tbl, },
- /* Segment registers */
- { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
- { "sr0", offsetof(CPUPPCState, sr[0]) },
- { "sr1", offsetof(CPUPPCState, sr[1]) },
- { "sr2", offsetof(CPUPPCState, sr[2]) },
- { "sr3", offsetof(CPUPPCState, sr[3]) },
- { "sr4", offsetof(CPUPPCState, sr[4]) },
- { "sr5", offsetof(CPUPPCState, sr[5]) },
- { "sr6", offsetof(CPUPPCState, sr[6]) },
- { "sr7", offsetof(CPUPPCState, sr[7]) },
- { "sr8", offsetof(CPUPPCState, sr[8]) },
- { "sr9", offsetof(CPUPPCState, sr[9]) },
- { "sr10", offsetof(CPUPPCState, sr[10]) },
- { "sr11", offsetof(CPUPPCState, sr[11]) },
- { "sr12", offsetof(CPUPPCState, sr[12]) },
- { "sr13", offsetof(CPUPPCState, sr[13]) },
- { "sr14", offsetof(CPUPPCState, sr[14]) },
- { "sr15", offsetof(CPUPPCState, sr[15]) },
- /* Too lazy to put BATs... */
- { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
-
- { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
- { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
- { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
- { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
- { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
- { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
- { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
- { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
- { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
- { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
- { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
- { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
- { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
- { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
- { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
- { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
- { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
- { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
- { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
- { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
- { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
- { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
- { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
- { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
- { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
- { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
- { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
- { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
- { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
- { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
- { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
- { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
- { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
- { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
- { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
- { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
- { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
- { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
- { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
- { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
- { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
- { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
- { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
- { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
- { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
- { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
- { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
- { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
- { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
- { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
- { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
- { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
- { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
- { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
- { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
- { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
- { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
- { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
- { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
- { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
- { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
- { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
- { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
- { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
- { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
- { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
-
-#elif defined(TARGET_SPARC)
- { "g0", offsetof(CPUSPARCState, gregs[0]) },
- { "g1", offsetof(CPUSPARCState, gregs[1]) },
- { "g2", offsetof(CPUSPARCState, gregs[2]) },
- { "g3", offsetof(CPUSPARCState, gregs[3]) },
- { "g4", offsetof(CPUSPARCState, gregs[4]) },
- { "g5", offsetof(CPUSPARCState, gregs[5]) },
- { "g6", offsetof(CPUSPARCState, gregs[6]) },
- { "g7", offsetof(CPUSPARCState, gregs[7]) },
- { "o0", 0, monitor_get_reg },
- { "o1", 1, monitor_get_reg },
- { "o2", 2, monitor_get_reg },
- { "o3", 3, monitor_get_reg },
- { "o4", 4, monitor_get_reg },
- { "o5", 5, monitor_get_reg },
- { "o6", 6, monitor_get_reg },
- { "o7", 7, monitor_get_reg },
- { "l0", 8, monitor_get_reg },
- { "l1", 9, monitor_get_reg },
- { "l2", 10, monitor_get_reg },
- { "l3", 11, monitor_get_reg },
- { "l4", 12, monitor_get_reg },
- { "l5", 13, monitor_get_reg },
- { "l6", 14, monitor_get_reg },
- { "l7", 15, monitor_get_reg },
- { "i0", 16, monitor_get_reg },
- { "i1", 17, monitor_get_reg },
- { "i2", 18, monitor_get_reg },
- { "i3", 19, monitor_get_reg },
- { "i4", 20, monitor_get_reg },
- { "i5", 21, monitor_get_reg },
- { "i6", 22, monitor_get_reg },
- { "i7", 23, monitor_get_reg },
- { "pc", offsetof(CPUSPARCState, pc) },
- { "npc", offsetof(CPUSPARCState, npc) },
- { "y", offsetof(CPUSPARCState, y) },
-#ifndef TARGET_SPARC64
- { "psr", 0, &monitor_get_psr, },
- { "wim", offsetof(CPUSPARCState, wim) },
-#endif
- { "tbr", offsetof(CPUSPARCState, tbr) },
- { "fsr", offsetof(CPUSPARCState, fsr) },
- { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
- { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
- { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
- { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
- { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
- { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
- { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
- { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
- { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
- { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
- { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
- { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
- { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
- { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
- { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
- { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
- { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
- { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
- { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
- { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
- { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
- { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
- { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
- { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
- { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
- { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
- { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
- { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
- { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
- { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
- { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
- { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
-#ifdef TARGET_SPARC64
- { "f32", offsetof(CPUSPARCState, fpr[16]) },
- { "f34", offsetof(CPUSPARCState, fpr[17]) },
- { "f36", offsetof(CPUSPARCState, fpr[18]) },
- { "f38", offsetof(CPUSPARCState, fpr[19]) },
- { "f40", offsetof(CPUSPARCState, fpr[20]) },
- { "f42", offsetof(CPUSPARCState, fpr[21]) },
- { "f44", offsetof(CPUSPARCState, fpr[22]) },
- { "f46", offsetof(CPUSPARCState, fpr[23]) },
- { "f48", offsetof(CPUSPARCState, fpr[24]) },
- { "f50", offsetof(CPUSPARCState, fpr[25]) },
- { "f52", offsetof(CPUSPARCState, fpr[26]) },
- { "f54", offsetof(CPUSPARCState, fpr[27]) },
- { "f56", offsetof(CPUSPARCState, fpr[28]) },
- { "f58", offsetof(CPUSPARCState, fpr[29]) },
- { "f60", offsetof(CPUSPARCState, fpr[30]) },
- { "f62", offsetof(CPUSPARCState, fpr[31]) },
- { "asi", offsetof(CPUSPARCState, asi) },
- { "pstate", offsetof(CPUSPARCState, pstate) },
- { "cansave", offsetof(CPUSPARCState, cansave) },
- { "canrestore", offsetof(CPUSPARCState, canrestore) },
- { "otherwin", offsetof(CPUSPARCState, otherwin) },
- { "wstate", offsetof(CPUSPARCState, wstate) },
- { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
- { "fprs", offsetof(CPUSPARCState, fprs) },
-#endif
-#endif
- { NULL },
-};
-
static void GCC_FMT_ATTR(2, 3) QEMU_NORETURN
expr_error(Monitor *mon, const char *fmt, ...)
{
@@ -3369,10 +2983,15 @@ expr_error(Monitor *mon, const char *fmt, ...)
/* return 0 if OK, -1 if not found */
static int get_monitor_def(target_long *pval, const char *name)
{
+ CPUState *cpu = ENV_GET_CPU(mon_get_cpu());
const MonitorDef *md;
void *ptr;
- for(md = monitor_defs; md->name != NULL; md++) {
+ if (cpu->monitor_defs == NULL) {
+ return -1;
+ }
+
+ for (md = cpu->monitor_defs; md->name != NULL; md++) {
if (compare_cmd(name, md->name)) {
if (md->get_value) {
*pval = md->get_value(md, md->offset);
@@ -3383,8 +3002,8 @@ static int get_monitor_def(target_long *pval, const char *name)
case MD_I32:
*pval = *(int32_t *)ptr;
break;
- case MD_TLONG:
- *pval = *(target_long *)ptr;
+ case MD_I64:
+ *pval = *(int64_t *)ptr;
break;
default:
*pval = 0;
diff --git a/target-i386/Makefile.objs b/target-i386/Makefile.objs
index da1fc40..839c8e6 100644
--- a/target-i386/Makefile.objs
+++ b/target-i386/Makefile.objs
@@ -2,7 +2,7 @@ obj-y += translate.o helper.o cpu.o
obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o
obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o
obj-y += gdbstub.o
-obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o
+obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o monitor.o
obj-$(CONFIG_KVM) += kvm.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-$(CONFIG_LINUX_USER) += ioport-user.o
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index c36345e..09bab99 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -47,7 +47,7 @@
#include "hw/xen/xen.h"
#include "hw/i386/apic_internal.h"
#endif
-
+#include "monitor/monitor.h"
/* Cache topology CPUID constants: */
@@ -2645,6 +2645,10 @@ static void x86_cpu_initfn(Object *obj)
cpu_set_debug_excp_handler(breakpoint_handler);
#endif
}
+
+#ifndef CONFIG_USER_ONLY
+ cs->monitor_defs = arch_monitor_defs;
+#endif
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
diff --git a/target-i386/monitor.c b/target-i386/monitor.c
new file mode 100644
index 0000000..f7ce747
--- /dev/null
+++ b/target-i386/monitor.c
@@ -0,0 +1,63 @@
+/*
+ * i386 MonitorDef
+ *
+ * Copyright (c) 2013 AdaCore
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "monitor/monitor.h"
+
+
+static uint64_t monitor_get_pc(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->eip + env->segs[R_CS].base;
+}
+
+const MonitorDef arch_monitor_defs[] = {
+#define SEG(name, seg) \
+ { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
+ { name ".base", offsetof(CPUX86State, segs[seg].base) },\
+ { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
+
+ { "eax", offsetof(CPUX86State, regs[0]) },
+ { "ecx", offsetof(CPUX86State, regs[1]) },
+ { "edx", offsetof(CPUX86State, regs[2]) },
+ { "ebx", offsetof(CPUX86State, regs[3]) },
+ { "esp|sp", offsetof(CPUX86State, regs[4]) },
+ { "ebp|fp", offsetof(CPUX86State, regs[5]) },
+ { "esi", offsetof(CPUX86State, regs[6]) },
+ { "edi", offsetof(CPUX86State, regs[7]) },
+#ifdef TARGET_X86_64
+ { "r8", offsetof(CPUX86State, regs[8]) },
+ { "r9", offsetof(CPUX86State, regs[9]) },
+ { "r10", offsetof(CPUX86State, regs[10]) },
+ { "r11", offsetof(CPUX86State, regs[11]) },
+ { "r12", offsetof(CPUX86State, regs[12]) },
+ { "r13", offsetof(CPUX86State, regs[13]) },
+ { "r14", offsetof(CPUX86State, regs[14]) },
+ { "r15", offsetof(CPUX86State, regs[15]) },
+#endif
+ { "eflags", offsetof(CPUX86State, eflags) },
+ { "eip", offsetof(CPUX86State, eip) },
+ SEG("cs", R_CS)
+ SEG("ds", R_DS)
+ SEG("es", R_ES)
+ SEG("ss", R_SS)
+ SEG("fs", R_FS)
+ SEG("gs", R_GS)
+ { "pc", 0, monitor_get_pc, },
+ { NULL },
+};
diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs
index f72e399..802eb83 100644
--- a/target-ppc/Makefile.objs
+++ b/target-ppc/Makefile.objs
@@ -1,7 +1,7 @@
obj-y += cpu-models.o
obj-y += translate.o
ifeq ($(CONFIG_SOFTMMU),y)
-obj-y += machine.o mmu_helper.o mmu-hash32.o
+obj-y += machine.o mmu_helper.o mmu-hash32.o monitor.o
obj-$(TARGET_PPC64) += mmu-hash64.o
endif
obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
diff --git a/target-ppc/monitor.c b/target-ppc/monitor.c
new file mode 100644
index 0000000..693c9b6
--- /dev/null
+++ b/target-ppc/monitor.c
@@ -0,0 +1,234 @@
+/*
+ * PPC MonitorDef
+ *
+ * Copyright (c) 2013 AdaCore
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "monitor/monitor.h"
+
+static uint64_t monitor_get_ccr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ unsigned int u;
+ int i;
+
+ u = 0;
+ for (i = 0; i < 8; i++) {
+ u |= env->crf[i] << (32 - (4 * i));
+ }
+
+ return u;
+}
+
+static uint64_t monitor_get_msr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->msr;
+}
+
+static uint64_t monitor_get_xer(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->xer;
+}
+
+static uint64_t monitor_get_decr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return cpu_ppc_load_decr(env);
+}
+
+static uint64_t monitor_get_tbu(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return cpu_ppc_load_tbu(env);
+}
+
+static uint64_t monitor_get_tbl(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return cpu_ppc_load_tbl(env);
+}
+
+const MonitorDef arch_monitor_defs[] = {
+ /* General purpose registers */
+ { "r0", offsetof(CPUPPCState, gpr[0]) },
+ { "r1", offsetof(CPUPPCState, gpr[1]) },
+ { "r2", offsetof(CPUPPCState, gpr[2]) },
+ { "r3", offsetof(CPUPPCState, gpr[3]) },
+ { "r4", offsetof(CPUPPCState, gpr[4]) },
+ { "r5", offsetof(CPUPPCState, gpr[5]) },
+ { "r6", offsetof(CPUPPCState, gpr[6]) },
+ { "r7", offsetof(CPUPPCState, gpr[7]) },
+ { "r8", offsetof(CPUPPCState, gpr[8]) },
+ { "r9", offsetof(CPUPPCState, gpr[9]) },
+ { "r10", offsetof(CPUPPCState, gpr[10]) },
+ { "r11", offsetof(CPUPPCState, gpr[11]) },
+ { "r12", offsetof(CPUPPCState, gpr[12]) },
+ { "r13", offsetof(CPUPPCState, gpr[13]) },
+ { "r14", offsetof(CPUPPCState, gpr[14]) },
+ { "r15", offsetof(CPUPPCState, gpr[15]) },
+ { "r16", offsetof(CPUPPCState, gpr[16]) },
+ { "r17", offsetof(CPUPPCState, gpr[17]) },
+ { "r18", offsetof(CPUPPCState, gpr[18]) },
+ { "r19", offsetof(CPUPPCState, gpr[19]) },
+ { "r20", offsetof(CPUPPCState, gpr[20]) },
+ { "r21", offsetof(CPUPPCState, gpr[21]) },
+ { "r22", offsetof(CPUPPCState, gpr[22]) },
+ { "r23", offsetof(CPUPPCState, gpr[23]) },
+ { "r24", offsetof(CPUPPCState, gpr[24]) },
+ { "r25", offsetof(CPUPPCState, gpr[25]) },
+ { "r26", offsetof(CPUPPCState, gpr[26]) },
+ { "r27", offsetof(CPUPPCState, gpr[27]) },
+ { "r28", offsetof(CPUPPCState, gpr[28]) },
+ { "r29", offsetof(CPUPPCState, gpr[29]) },
+ { "r30", offsetof(CPUPPCState, gpr[30]) },
+ { "r31", offsetof(CPUPPCState, gpr[31]) },
+ /* Floating point registers */
+ { "f0", offsetof(CPUPPCState, fpr[0]) },
+ { "f1", offsetof(CPUPPCState, fpr[1]) },
+ { "f2", offsetof(CPUPPCState, fpr[2]) },
+ { "f3", offsetof(CPUPPCState, fpr[3]) },
+ { "f4", offsetof(CPUPPCState, fpr[4]) },
+ { "f5", offsetof(CPUPPCState, fpr[5]) },
+ { "f6", offsetof(CPUPPCState, fpr[6]) },
+ { "f7", offsetof(CPUPPCState, fpr[7]) },
+ { "f8", offsetof(CPUPPCState, fpr[8]) },
+ { "f9", offsetof(CPUPPCState, fpr[9]) },
+ { "f10", offsetof(CPUPPCState, fpr[10]) },
+ { "f11", offsetof(CPUPPCState, fpr[11]) },
+ { "f12", offsetof(CPUPPCState, fpr[12]) },
+ { "f13", offsetof(CPUPPCState, fpr[13]) },
+ { "f14", offsetof(CPUPPCState, fpr[14]) },
+ { "f15", offsetof(CPUPPCState, fpr[15]) },
+ { "f16", offsetof(CPUPPCState, fpr[16]) },
+ { "f17", offsetof(CPUPPCState, fpr[17]) },
+ { "f18", offsetof(CPUPPCState, fpr[18]) },
+ { "f19", offsetof(CPUPPCState, fpr[19]) },
+ { "f20", offsetof(CPUPPCState, fpr[20]) },
+ { "f21", offsetof(CPUPPCState, fpr[21]) },
+ { "f22", offsetof(CPUPPCState, fpr[22]) },
+ { "f23", offsetof(CPUPPCState, fpr[23]) },
+ { "f24", offsetof(CPUPPCState, fpr[24]) },
+ { "f25", offsetof(CPUPPCState, fpr[25]) },
+ { "f26", offsetof(CPUPPCState, fpr[26]) },
+ { "f27", offsetof(CPUPPCState, fpr[27]) },
+ { "f28", offsetof(CPUPPCState, fpr[28]) },
+ { "f29", offsetof(CPUPPCState, fpr[29]) },
+ { "f30", offsetof(CPUPPCState, fpr[30]) },
+ { "f31", offsetof(CPUPPCState, fpr[31]) },
+ { "fpscr", offsetof(CPUPPCState, fpscr) },
+ /* Next instruction pointer */
+ { "nip|pc", offsetof(CPUPPCState, nip) },
+ { "lr", offsetof(CPUPPCState, lr) },
+ { "ctr", offsetof(CPUPPCState, ctr) },
+ { "decr", 0, &monitor_get_decr, },
+ { "ccr", 0, &monitor_get_ccr, },
+ /* Machine state register */
+ { "msr", 0, &monitor_get_msr, },
+ { "xer", 0, &monitor_get_xer, },
+ { "tbu", 0, &monitor_get_tbu, },
+ { "tbl", 0, &monitor_get_tbl, },
+ /* Segment registers */
+ { "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
+#if !defined(CONFIG_USER_ONLY)
+ { "sr0", offsetof(CPUPPCState, sr[0]) },
+ { "sr1", offsetof(CPUPPCState, sr[1]) },
+ { "sr2", offsetof(CPUPPCState, sr[2]) },
+ { "sr3", offsetof(CPUPPCState, sr[3]) },
+ { "sr4", offsetof(CPUPPCState, sr[4]) },
+ { "sr5", offsetof(CPUPPCState, sr[5]) },
+ { "sr6", offsetof(CPUPPCState, sr[6]) },
+ { "sr7", offsetof(CPUPPCState, sr[7]) },
+ { "sr8", offsetof(CPUPPCState, sr[8]) },
+ { "sr9", offsetof(CPUPPCState, sr[9]) },
+ { "sr10", offsetof(CPUPPCState, sr[10]) },
+ { "sr11", offsetof(CPUPPCState, sr[11]) },
+ { "sr12", offsetof(CPUPPCState, sr[12]) },
+ { "sr13", offsetof(CPUPPCState, sr[13]) },
+ { "sr14", offsetof(CPUPPCState, sr[14]) },
+ { "sr15", offsetof(CPUPPCState, sr[15]) },
+#endif /* Too lazy to put BATs... */
+ { "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
+
+ { "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
+ { "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
+ { "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
+ { "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
+ { "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
+ { "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
+ { "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
+ { "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
+ { "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
+ { "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
+ { "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
+ { "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
+ { "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
+ { "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
+ { "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
+ { "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
+ { "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
+ { "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
+ { "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
+ { "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
+ { "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
+ { "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
+ { "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
+ { "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
+ { "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
+ { "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
+ { "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
+ { "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
+ { "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
+ { "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
+ { "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
+ { "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
+ { "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
+ { "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
+ { "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
+ { "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
+ { "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
+ { "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
+ { "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
+ { "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
+ { "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
+ { "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
+ { "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
+ { "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
+ { "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
+ { "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
+ { "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
+ { "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
+ { "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
+ { "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
+ { "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
+ { "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
+ { "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
+ { "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
+ { "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
+ { "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
+ { "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
+ { "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
+ { "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
+ { "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
+ { "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
+ { "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
+ { "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
+ { "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
+ { "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
+ { "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
+ { NULL },
+};
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d2645ba..30026c7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -28,6 +28,7 @@
#include "mmu-hash32.h"
#include "mmu-hash64.h"
#include "qemu/error-report.h"
+#include "monitor/monitor.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
@@ -8542,6 +8543,10 @@ static void ppc_cpu_initfn(Object *obj)
}
#endif /* defined(TARGET_PPC64) */
+#if !defined(CONFIG_USER_ONLY)
+ cs->monitor_defs = arch_monitor_defs;
+#endif
+
if (tcg_enabled()) {
ppc_translate_init();
}
diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs
index 1cd81cc..ec90569 100644
--- a/target-sparc/Makefile.objs
+++ b/target-sparc/Makefile.objs
@@ -1,4 +1,4 @@
-obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_SOFTMMU) += machine.o monitor.o
obj-y += translate.o helper.o cpu.o
obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
obj-$(TARGET_SPARC) += int32_helper.o
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 47ce60d..3d82c66 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -18,6 +18,7 @@
*/
#include "cpu.h"
+#include "monitor/monitor.h"
//#define DEBUG_FEATURES
@@ -757,6 +758,10 @@ static void sparc_cpu_initfn(Object *obj)
cs->env_ptr = env;
cpu_exec_init(env);
+#if !defined(CONFIG_USER_ONLY)
+ cs->monitor_defs = arch_monitor_defs;
+#endif
+
if (tcg_enabled()) {
gen_intermediate_code_init(env);
}
diff --git a/target-sparc/monitor.c b/target-sparc/monitor.c
new file mode 100644
index 0000000..58fc094
--- /dev/null
+++ b/target-sparc/monitor.c
@@ -0,0 +1,138 @@
+/*
+ * SPARC MonitorDef
+ *
+ * Copyright (c) 2013 AdaCore
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "monitor/monitor.h"
+
+#ifndef TARGET_SPARC64
+static uint64_t monitor_get_psr(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+
+ return cpu_get_psr(env);
+}
+#endif
+
+static uint64_t monitor_get_reg(const struct MonitorDef *md, int val)
+{
+ CPUArchState *env = mon_get_cpu();
+ return env->regwptr[val];
+}
+
+const MonitorDef arch_monitor_defs[] = {
+ { "g0", offsetof(CPUSPARCState, gregs[0]) },
+ { "g1", offsetof(CPUSPARCState, gregs[1]) },
+ { "g2", offsetof(CPUSPARCState, gregs[2]) },
+ { "g3", offsetof(CPUSPARCState, gregs[3]) },
+ { "g4", offsetof(CPUSPARCState, gregs[4]) },
+ { "g5", offsetof(CPUSPARCState, gregs[5]) },
+ { "g6", offsetof(CPUSPARCState, gregs[6]) },
+ { "g7", offsetof(CPUSPARCState, gregs[7]) },
+ { "o0", 0, monitor_get_reg },
+ { "o1", 1, monitor_get_reg },
+ { "o2", 2, monitor_get_reg },
+ { "o3", 3, monitor_get_reg },
+ { "o4", 4, monitor_get_reg },
+ { "o5", 5, monitor_get_reg },
+ { "o6", 6, monitor_get_reg },
+ { "o7", 7, monitor_get_reg },
+ { "l0", 8, monitor_get_reg },
+ { "l1", 9, monitor_get_reg },
+ { "l2", 10, monitor_get_reg },
+ { "l3", 11, monitor_get_reg },
+ { "l4", 12, monitor_get_reg },
+ { "l5", 13, monitor_get_reg },
+ { "l6", 14, monitor_get_reg },
+ { "l7", 15, monitor_get_reg },
+ { "i0", 16, monitor_get_reg },
+ { "i1", 17, monitor_get_reg },
+ { "i2", 18, monitor_get_reg },
+ { "i3", 19, monitor_get_reg },
+ { "i4", 20, monitor_get_reg },
+ { "i5", 21, monitor_get_reg },
+ { "i6", 22, monitor_get_reg },
+ { "i7", 23, monitor_get_reg },
+ { "pc", offsetof(CPUSPARCState, pc) },
+ { "npc", offsetof(CPUSPARCState, npc) },
+ { "y", offsetof(CPUSPARCState, y) },
+#ifndef TARGET_SPARC64
+ { "psr", 0, &monitor_get_psr, },
+ { "wim", offsetof(CPUSPARCState, wim) },
+#endif
+ { "tbr", offsetof(CPUSPARCState, tbr) },
+ { "fsr", offsetof(CPUSPARCState, fsr) },
+ { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
+ { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
+ { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
+ { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
+ { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
+ { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
+ { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
+ { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
+ { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
+ { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
+ { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
+ { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
+ { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
+ { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
+ { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
+ { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
+ { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
+ { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
+ { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
+ { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
+ { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
+ { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
+ { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
+ { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
+ { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
+ { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
+ { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
+ { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
+ { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
+ { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
+ { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
+ { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
+#ifdef TARGET_SPARC64
+ { "f32", offsetof(CPUSPARCState, fpr[16]) },
+ { "f34", offsetof(CPUSPARCState, fpr[17]) },
+ { "f36", offsetof(CPUSPARCState, fpr[18]) },
+ { "f38", offsetof(CPUSPARCState, fpr[19]) },
+ { "f40", offsetof(CPUSPARCState, fpr[20]) },
+ { "f42", offsetof(CPUSPARCState, fpr[21]) },
+ { "f44", offsetof(CPUSPARCState, fpr[22]) },
+ { "f46", offsetof(CPUSPARCState, fpr[23]) },
+ { "f48", offsetof(CPUSPARCState, fpr[24]) },
+ { "f50", offsetof(CPUSPARCState, fpr[25]) },
+ { "f52", offsetof(CPUSPARCState, fpr[26]) },
+ { "f54", offsetof(CPUSPARCState, fpr[27]) },
+ { "f56", offsetof(CPUSPARCState, fpr[28]) },
+ { "f58", offsetof(CPUSPARCState, fpr[29]) },
+ { "f60", offsetof(CPUSPARCState, fpr[30]) },
+ { "f62", offsetof(CPUSPARCState, fpr[31]) },
+ { "asi", offsetof(CPUSPARCState, asi) },
+ { "pstate", offsetof(CPUSPARCState, pstate) },
+ { "cansave", offsetof(CPUSPARCState, cansave) },
+ { "canrestore", offsetof(CPUSPARCState, canrestore) },
+ { "otherwin", offsetof(CPUSPARCState, otherwin) },
+ { "wstate", offsetof(CPUSPARCState, wstate) },
+ { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
+ { "fprs", offsetof(CPUSPARCState, fprs) },
+#endif
+ { NULL },
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 23+ messages in thread
end of thread, other threads:[~2013-10-07 14:41 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-10-04 16:56 [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v4) Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 1/4] Fix coding style Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 2/4] Improve Monitor disas with symbol lookup Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array Fabien Chouteau
2013-10-04 17:49 ` Peter Maydell
2013-10-04 17:55 ` Andreas Färber
2013-10-07 10:11 ` Fabien Chouteau
2013-10-07 11:45 ` Peter Maydell
2013-10-07 13:06 ` Fabien Chouteau
2013-10-07 13:29 ` Peter Maydell
2013-10-07 14:40 ` Fabien Chouteau
2013-10-04 16:57 ` [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands Fabien Chouteau
2013-10-04 17:52 ` Peter Maydell
2013-10-07 10:12 ` Fabien Chouteau
-- strict thread matches above, loose matches on Subject: below --
2013-09-30 15:57 [Qemu-devel] [PATCH 0/4] Few minor improvements of monitor disas command (v3) Fabien Chouteau
2013-09-30 15:57 ` [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array Fabien Chouteau
2013-10-01 1:08 ` Peter Maydell
2013-10-01 14:23 ` Fabien Chouteau
2013-10-01 14:49 ` Peter Maydell
2013-10-01 2:00 ` Richard Henderson
2013-10-01 14:28 ` Fabien Chouteau
2013-10-01 15:13 ` Richard Henderson
2013-10-01 15:21 ` Peter Maydell
2013-10-01 16:13 ` Fabien Chouteau
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