All of lore.kernel.org
 help / color / mirror / Atom feed
From: <Conor.Dooley@microchip.com>
To: <heiko@sntech.de>, <samuel@sholland.org>, <wens@csie.org>,
	<jernej.skrabec@gmail.com>, <linux-sunxi@lists.linux.dev>,
	<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
	<aou@eecs.berkeley.edu>, <linux-riscv@lists.infradead.org>
Cc: <robh+dt@kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>
Subject: Re: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option
Date: Tue, 16 Aug 2022 09:23:16 +0000	[thread overview]
Message-ID: <53fa815e-b4aa-7dea-a403-c29738af296e@microchip.com> (raw)
In-Reply-To: <10785313.BaYr0rKQ5T@diego>

On 16/08/2022 10:17, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am Montag, 15. August 2022, 18:56:23 CEST schrieb Conor.Dooley@microchip.com:
>> On 15/08/2022 06:08, Samuel Holland wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Allwinner manufactures the sunxi family of application processors. This
>>> includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
>>> SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>>>
>>> The first SoC in the sun20i series is D1, containing a single T-HEAD
>>> C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>>>
>>> Most peripherals are shared across the entire chip family. In fact, the
>>> ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
>>> with the D1s.
>>>
>>> This means many existing device drivers can be reused. To facilitate
>>> this reuse, name the symbol ARCH_SUNXI, since that is what the existing
>>> drivers have as their dependency.
>>
>> Hey Samuel,
>> I think this and patch 12/12 with the defconfig changes should be
>> deferred until post LPC (which still leaves plenty of time for
>> making the 6.1 merge window). We already have like 4 different
>> approaches between the existing SOC_FOO symbols & two more when
>> D1 stuff and the Renesas stuff is considered.
> 
> On the other hand, I don't really think it's that hard to change things
> after the fact? I.e. ARCH_SUNXI is pretty much set in stone anyway,
> so there isn't very much that _could_ change without affecting most
> driver subsystems in the kernel.
> 
> So I don't think we'd actually need to wait with the Allwinner symbol.

True, but it'd be the same release anyway most likely so I don't
think that there'd really be any waiting involved. I /like/ the
idea of using ARCH_FOO rather than SOC_FOO as it's far more
consistent across the kernel - it's more a question of not doing
one thing here and another with the Renesas stuff to me.

> 
> 
> Heiko
> 
>> Plan is to decide at LPC on one approach for what to do with
>> Kconfig.socs & to me it seems like a good idea to do what's being
>> done here - it's likely that further arm vendors will move and
>> keeping the common symbols makes a lot of sense to me...
>>
>> Thanks,
>> Conor.
>>
>>>
>>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>>> ---
>>>
>>>   arch/riscv/Kconfig.socs | 9 +++++++++
>>>   1 file changed, 9 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>> index 69774bb362d6..1caacbfac1a5 100644
>>> --- a/arch/riscv/Kconfig.socs
>>> +++ b/arch/riscv/Kconfig.socs
>>> @@ -1,5 +1,14 @@
>>>   menu "SoC selection"
>>>
>>> +config ARCH_SUNXI
>>> +       bool "Allwinner sun20i SoCs"
>>> +       select ERRATA_THEAD if MMU && !XIP_KERNEL
>>> +       select SIFIVE_PLIC
>>> +       select SUN4I_TIMER
>>> +       help
>>> +         This enables support for Allwinner sun20i platform hardware,
>>> +         including boards based on the D1 and D1s SoCs.
>>> +
>>>   config SOC_MICROCHIP_POLARFIRE
>>>          bool "Microchip PolarFire SoCs"
>>>          select MCHP_CLK_MPFS
>>> --
>>> 2.35.1
>>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>
> 
> 
> 
> 


WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com>
To: <heiko@sntech.de>, <samuel@sholland.org>, <wens@csie.org>,
	<jernej.skrabec@gmail.com>, <linux-sunxi@lists.linux.dev>,
	<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
	<aou@eecs.berkeley.edu>, <linux-riscv@lists.infradead.org>
Cc: <robh+dt@kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>
Subject: Re: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option
Date: Tue, 16 Aug 2022 09:23:16 +0000	[thread overview]
Message-ID: <53fa815e-b4aa-7dea-a403-c29738af296e@microchip.com> (raw)
In-Reply-To: <10785313.BaYr0rKQ5T@diego>

On 16/08/2022 10:17, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am Montag, 15. August 2022, 18:56:23 CEST schrieb Conor.Dooley@microchip.com:
>> On 15/08/2022 06:08, Samuel Holland wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Allwinner manufactures the sunxi family of application processors. This
>>> includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
>>> SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>>>
>>> The first SoC in the sun20i series is D1, containing a single T-HEAD
>>> C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>>>
>>> Most peripherals are shared across the entire chip family. In fact, the
>>> ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
>>> with the D1s.
>>>
>>> This means many existing device drivers can be reused. To facilitate
>>> this reuse, name the symbol ARCH_SUNXI, since that is what the existing
>>> drivers have as their dependency.
>>
>> Hey Samuel,
>> I think this and patch 12/12 with the defconfig changes should be
>> deferred until post LPC (which still leaves plenty of time for
>> making the 6.1 merge window). We already have like 4 different
>> approaches between the existing SOC_FOO symbols & two more when
>> D1 stuff and the Renesas stuff is considered.
> 
> On the other hand, I don't really think it's that hard to change things
> after the fact? I.e. ARCH_SUNXI is pretty much set in stone anyway,
> so there isn't very much that _could_ change without affecting most
> driver subsystems in the kernel.
> 
> So I don't think we'd actually need to wait with the Allwinner symbol.

True, but it'd be the same release anyway most likely so I don't
think that there'd really be any waiting involved. I /like/ the
idea of using ARCH_FOO rather than SOC_FOO as it's far more
consistent across the kernel - it's more a question of not doing
one thing here and another with the Renesas stuff to me.

> 
> 
> Heiko
> 
>> Plan is to decide at LPC on one approach for what to do with
>> Kconfig.socs & to me it seems like a good idea to do what's being
>> done here - it's likely that further arm vendors will move and
>> keeping the common symbols makes a lot of sense to me...
>>
>> Thanks,
>> Conor.
>>
>>>
>>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>>> ---
>>>
>>>   arch/riscv/Kconfig.socs | 9 +++++++++
>>>   1 file changed, 9 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>> index 69774bb362d6..1caacbfac1a5 100644
>>> --- a/arch/riscv/Kconfig.socs
>>> +++ b/arch/riscv/Kconfig.socs
>>> @@ -1,5 +1,14 @@
>>>   menu "SoC selection"
>>>
>>> +config ARCH_SUNXI
>>> +       bool "Allwinner sun20i SoCs"
>>> +       select ERRATA_THEAD if MMU && !XIP_KERNEL
>>> +       select SIFIVE_PLIC
>>> +       select SUN4I_TIMER
>>> +       help
>>> +         This enables support for Allwinner sun20i platform hardware,
>>> +         including boards based on the D1 and D1s SoCs.
>>> +
>>>   config SOC_MICROCHIP_POLARFIRE
>>>          bool "Microchip PolarFire SoCs"
>>>          select MCHP_CLK_MPFS
>>> --
>>> 2.35.1
>>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>
> 
> 
> 
> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-08-16  9:23 UTC|newest]

Thread overview: 158+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-15  5:08 [PATCH 00/12] riscv: Allwinner D1 platform support Samuel Holland
2022-08-15  5:08 ` Samuel Holland
2022-08-15  5:08 ` [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15 17:06   ` Heiko Stübner
2022-08-15 17:06     ` Heiko Stübner
2022-08-15  5:08 ` [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15 17:07   ` Heiko Stübner
2022-08-15 17:07     ` Heiko Stübner
2022-08-16 17:34   ` Rob Herring
2022-08-16 17:34     ` Rob Herring
2022-11-04  2:57   ` Icenowy Zheng
2022-11-04  2:57     ` Icenowy Zheng
2022-11-20 11:23     ` Conor Dooley
2022-11-20 11:23       ` Conor Dooley
2022-11-20 11:25       ` Conor Dooley
2022-11-20 11:25         ` Conor Dooley
2022-08-15  5:08 ` [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15 17:12   ` Heiko Stübner
2022-08-15 17:12     ` Heiko Stübner
2022-08-16 17:34   ` Rob Herring
2022-08-16 17:34     ` Rob Herring
2022-08-15  5:08 ` [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-16  7:39   ` Krzysztof Kozlowski
2022-08-16  7:39     ` Krzysztof Kozlowski
2022-08-16  9:02     ` Heiko Stübner
2022-08-16  9:02       ` Heiko Stübner
2022-08-16  9:12   ` Heiko Stübner
2022-08-16  9:12     ` Heiko Stübner
2022-08-16 17:35   ` Rob Herring
2022-08-16 17:35     ` Rob Herring
2022-08-15  5:08 ` [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15 16:56   ` Conor.Dooley
2022-08-15 16:56     ` Conor.Dooley
2022-08-16  9:17     ` Heiko Stübner
2022-08-16  9:17       ` Heiko Stübner
2022-08-16  9:23       ` Conor.Dooley [this message]
2022-08-16  9:23         ` Conor.Dooley
2022-08-15 17:13   ` Heiko Stübner
2022-08-15 17:13     ` Heiko Stübner
2022-08-15  5:08 ` [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15 13:11   ` Andre Przywara
2022-08-15 13:11     ` Andre Przywara
2022-08-15 17:01     ` Conor.Dooley
2022-08-15 17:01       ` Conor.Dooley
2022-08-20 17:24       ` Samuel Holland
2022-08-20 17:24         ` Samuel Holland
2022-08-20 17:29         ` Conor.Dooley
2022-08-20 17:29           ` Conor.Dooley
2022-08-21  6:45           ` Icenowy Zheng
2022-08-21  6:45             ` Icenowy Zheng
2022-08-21 10:04             ` Conor.Dooley
2022-08-21 10:04               ` Conor.Dooley
2022-08-22 11:46               ` Geert Uytterhoeven
2022-08-22 11:46                 ` Geert Uytterhoeven
2022-08-22 12:13                 ` Conor.Dooley
2022-08-22 12:13                   ` Conor.Dooley
2022-08-22 12:29                   ` Andre Przywara
2022-08-22 12:29                     ` Andre Przywara
2022-08-22 12:31                   ` Geert Uytterhoeven
2022-08-22 12:31                     ` Geert Uytterhoeven
2022-08-22 13:56                     ` Conor.Dooley
2022-08-22 13:56                       ` Conor.Dooley
2022-08-22 15:29                       ` Jessica Clarke
2022-08-22 15:29                         ` Jessica Clarke
2022-09-09  3:42                         ` Samuel Holland
2022-09-09  3:42                           ` Samuel Holland
2022-09-09  7:10                           ` Geert Uytterhoeven
2022-09-09  7:10                             ` Geert Uytterhoeven
2022-09-21  7:49                             ` Geert Uytterhoeven
2022-09-21  7:49                               ` Geert Uytterhoeven
2022-08-22 10:50         ` Andre Przywara
2022-08-22 10:50           ` Andre Przywara
2022-08-16  7:41   ` Krzysztof Kozlowski
2022-08-16  7:41     ` Krzysztof Kozlowski
2022-08-16  7:49     ` Jernej Škrabec
2022-08-16  7:49       ` Jernej Škrabec
2022-08-16  9:12       ` Heiko Stübner
2022-08-16  9:12         ` Heiko Stübner
2022-08-16  9:25         ` Jernej Škrabec
2022-08-16  9:25           ` Jernej Škrabec
2022-08-16  9:42           ` Krzysztof Kozlowski
2022-08-16  9:42             ` Krzysztof Kozlowski
2022-08-16 11:00             ` Andre Przywara
2022-08-16 11:00               ` Andre Przywara
2022-08-16 11:11               ` Krzysztof Kozlowski
2022-08-16 11:11                 ` Krzysztof Kozlowski
2022-08-16 11:12                 ` Krzysztof Kozlowski
2022-08-16 11:12                   ` Krzysztof Kozlowski
2022-08-16 11:34                   ` Conor.Dooley
2022-08-16 11:34                     ` Conor.Dooley
2022-08-22 11:40           ` Geert Uytterhoeven
2022-08-22 11:40             ` Geert Uytterhoeven
2022-08-16  9:11   ` Heiko Stübner
2022-08-16  9:11     ` Heiko Stübner
2022-08-17  8:29   ` Krzysztof Kozlowski
2022-08-17  8:29     ` Krzysztof Kozlowski
2022-08-19 22:19   ` Conor.Dooley
2022-08-19 22:19     ` Conor.Dooley
2022-08-15  5:08 ` [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15 17:37   ` Conor.Dooley
2022-08-15 17:37     ` Conor.Dooley
2022-08-15 18:34     ` Conor.Dooley
2022-08-15 18:34       ` Conor.Dooley
2022-08-16  8:55   ` Heiko Stübner
2022-08-16  8:55     ` Heiko Stübner
2022-08-19 22:10   ` Conor.Dooley
2022-08-19 22:10     ` Conor.Dooley
2022-08-21  7:06     ` Icenowy Zheng
2022-08-21  7:06       ` Icenowy Zheng
2022-09-04 20:10     ` Peter Korsgaard
2022-09-04 20:10       ` Peter Korsgaard
2022-09-09  4:37     ` Samuel Holland
2022-09-09  4:37       ` Samuel Holland
2022-09-09  7:18       ` Conor.Dooley
2022-09-09  7:18         ` Conor.Dooley
2022-09-09  8:11         ` Heiko Stübner
2022-09-09  8:11           ` Heiko Stübner
2022-09-09 19:04           ` Jessica Clarke
2022-09-09 19:04             ` Jessica Clarke
2022-09-03 15:21   ` Peter Korsgaard
2022-09-03 15:21     ` Peter Korsgaard
2022-08-15  5:08 ` [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15  5:08 ` [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15  5:08 ` [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15  5:08 ` [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15  5:08 ` [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Samuel Holland
2022-08-15  5:08   ` Samuel Holland
2022-08-15  7:05 ` [PATCH 00/12] riscv: Allwinner D1 platform support Conor.Dooley
2022-08-15  7:05   ` Conor.Dooley
2022-08-15 17:12   ` Conor.Dooley
2022-08-15 17:12     ` Conor.Dooley
2022-08-16  2:42     ` Samuel Holland
2022-08-16  2:42       ` Samuel Holland
2022-08-16  6:38       ` Conor.Dooley
2022-08-16  6:38         ` Conor.Dooley
2022-09-01 18:10 ` Palmer Dabbelt
2022-09-01 18:10   ` Palmer Dabbelt
2022-09-02  5:42   ` Conor.Dooley
2022-09-02  5:42     ` Conor.Dooley
2022-09-06 20:29   ` Jernej Škrabec
2022-09-06 20:29     ` Jernej Škrabec
2022-09-07 20:43     ` Conor.Dooley
2022-09-07 20:43       ` Conor.Dooley
2022-09-08  7:00       ` Geert Uytterhoeven
2022-09-08  7:00         ` Geert Uytterhoeven
2022-09-08  9:04         ` Arnd Bergmann
2022-09-08  9:04           ` Arnd Bergmann

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=53fa815e-b4aa-7dea-a403-c29738af296e@microchip.com \
    --to=conor.dooley@microchip.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=devicetree@vger.kernel.org \
    --cc=heiko@sntech.de \
    --cc=jernej.skrabec@gmail.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=samuel@sholland.org \
    --cc=wens@csie.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.