[Qemu-devel] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Qemu-devel] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Pierre Mallard]

This patch series enable floating point instruction in 440x5 CPUs 
which have the capabilities to have optional APU FPU.

1) Add floating point standard insns flag to 440x5 in case there is an apu fpu.
2) Define a new floating point insns flag for operation 
previously reserved to 64 bits proc (fcfid, fctid, fctidz)
3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64 
restrictions
*** BLURB HERE ***

Pierre Mallard (3):
  target-ppc : Add floating point ability to 440x5 PPC CPU
  target-ppc : Add PPC_FLOAT_64 flag to instructions type
  target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and
    remove their TARGET_PPC64 restriction

 target-ppc/cpu.h            |    7 +++++--
 target-ppc/fpu_helper.c     |    7 +++----
 target-ppc/helper.h         |    6 ++++--
 target-ppc/translate.c      |   20 ++++++++++++--------
 target-ppc/translate_init.c |    4 ++++
 5 files changed, 28 insertions(+), 16 deletions(-)

-- 
1.7.10.4

[Qemu-devel] [PATCH 1/3] target-ppc : Add floating point ability to 440x5 PPC CPU

[Pierre Mallard]

This patch add some floating point operation for PPC440x5.
Compile with PPC440x5_HAVE_FPU enabled in configure extra-cflags

Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
---
 target-ppc/translate_init.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 48177ed..b4dedce 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3897,6 +3897,10 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
     pcc->init_proc = init_proc_440x5;
     pcc->check_pow = check_pow_nocheck;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
+#ifdef PPC440x5_HAVE_FPU
+                       PPC_FLOAT | PPC_FLOAT_FSQRT | 
+                       PPC_FLOAT_STFIWX |
+#endif
                        PPC_DCR | PPC_WRTEE | PPC_RFMCI |
                        PPC_CACHE | PPC_CACHE_ICBI |
                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
-- 
1.7.10.4

Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/3] target-ppc : Add floating point ability to 440x5 PPC CPU

[Alexander Graf]

On 10.09.14 07:03, Pierre Mallard wrote:
> This patch add some floating point operation for PPC440x5.
> Compile with PPC440x5_HAVE_FPU enabled in configure extra-cflags
> 
> Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>

Instead of the define, could we just create a new CPU that has these
flags enabled? Just call it "440x5-fpu" or so.


Alex

> ---
>  target-ppc/translate_init.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 48177ed..b4dedce 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -3897,6 +3897,10 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
>      pcc->init_proc = init_proc_440x5;
>      pcc->check_pow = check_pow_nocheck;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
> +#ifdef PPC440x5_HAVE_FPU
> +                       PPC_FLOAT | PPC_FLOAT_FSQRT | 
> +                       PPC_FLOAT_STFIWX |
> +#endif
>                         PPC_DCR | PPC_WRTEE | PPC_RFMCI |
>                         PPC_CACHE | PPC_CACHE_ICBI |
>                         PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
> 

[Qemu-devel] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type

[Pierre Mallard]

This patch declare a new floating point instruction flag PPC_FLOAT_64 to be used
by fcfid, fctid[z] operations. Note that due to limited number of bit, 
FSEL and FRES points now to same value, and PPC_FLOAT_64 to former FSEL value. 
(There seems to be no case where FSEL and FRES are not used together at the moment)

Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
---
 target-ppc/cpu.h            |    7 +++++--
 target-ppc/translate_init.c |    2 +-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b64c652..b5b3912 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1868,9 +1868,12 @@ enum {
     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
-    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
+    PPC_FLOAT_FSEL     = 0x0000000000080000ULL,
     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
 
+    /* Use for PPC with double precision fpu */
+    PPC_FLOAT_64   = 0x0000000000400000ULL,
+
     /* Vector/SIMD extensions                                                */
     /*   Altivec support                                                     */
     PPC_ALTIVEC        = 0x0000000001000000ULL,
@@ -1957,7 +1960,7 @@ enum {
                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
-                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
+                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | PPC_FLOAT_64 \
                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b4dedce..073bef1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3899,7 +3899,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
 #ifdef PPC440x5_HAVE_FPU
                        PPC_FLOAT | PPC_FLOAT_FSQRT | 
-                       PPC_FLOAT_STFIWX |
+                       PPC_FLOAT_STFIWX | PPC_FLOAT_64 |
 #endif
                        PPC_DCR | PPC_WRTEE | PPC_RFMCI |
                        PPC_CACHE | PPC_CACHE_ICBI |
-- 
1.7.10.4

Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type

[Alexander Graf]

On 10.09.14 07:03, Pierre Mallard wrote:
> This patch declare a new floating point instruction flag PPC_FLOAT_64 to be used
> by fcfid, fctid[z] operations. Note that due to limited number of bit, 
> FSEL and FRES points now to same value, and PPC_FLOAT_64 to former FSEL value. 
> (There seems to be no case where FSEL and FRES are not used together at the moment)
> 
> Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
> ---
>  target-ppc/cpu.h            |    7 +++++--
>  target-ppc/translate_init.c |    2 +-
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index b64c652..b5b3912 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1868,9 +1868,12 @@ enum {
>      PPC_FLOAT_FRES     = 0x0000000000080000ULL,
>      PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
>      PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
> -    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
> +    PPC_FLOAT_FSEL     = 0x0000000000080000ULL,
>      PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
>  
> +    /* Use for PPC with double precision fpu */
> +    PPC_FLOAT_64   = 0x0000000000400000ULL,

Please keep the list sorted by the bit number. Also I think we're better
off not having the same bit used for 2 enums. Just keep PPC_FLOAT_FRES
and make FSEL depend on the FRES bit in translate.c

> +
>      /* Vector/SIMD extensions                                                */
>      /*   Altivec support                                                     */
>      PPC_ALTIVEC        = 0x0000000001000000ULL,
> @@ -1957,7 +1960,7 @@ enum {
>                          | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
>                          | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
>                          | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
> -                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
> +                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | PPC_FLOAT_64 \
>                          | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
>                          | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
>                          | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index b4dedce..073bef1 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -3899,7 +3899,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
>  #ifdef PPC440x5_HAVE_FPU
>                         PPC_FLOAT | PPC_FLOAT_FSQRT | 
> -                       PPC_FLOAT_STFIWX |
> +                       PPC_FLOAT_STFIWX | PPC_FLOAT_64 |
>  #endif
>                         PPC_DCR | PPC_WRTEE | PPC_RFMCI |
>                         PPC_CACHE | PPC_CACHE_ICBI |
> 

Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type

[Tom Musta]

On 9/10/2014 4:18 AM, Alexander Graf wrote:
> 
> 
> On 10.09.14 07:03, Pierre Mallard wrote:
>> This patch declare a new floating point instruction flag PPC_FLOAT_64 to be used
>> by fcfid, fctid[z] operations. Note that due to limited number of bit, 
>> FSEL and FRES points now to same value, and PPC_FLOAT_64 to former FSEL value. 
>> (There seems to be no case where FSEL and FRES are not used together at the moment)
>>
>> Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
>> ---
>>  target-ppc/cpu.h            |    7 +++++--
>>  target-ppc/translate_init.c |    2 +-
>>  2 files changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index b64c652..b5b3912 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1868,9 +1868,12 @@ enum {
>>      PPC_FLOAT_FRES     = 0x0000000000080000ULL,
>>      PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
>>      PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
>> -    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
>> +    PPC_FLOAT_FSEL     = 0x0000000000080000ULL,
>>      PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
>>  
>> +    /* Use for PPC with double precision fpu */
>> +    PPC_FLOAT_64   = 0x0000000000400000ULL,
> 
> Please keep the list sorted by the bit number. Also I think we're better
> off not having the same bit used for 2 enums. Just keep PPC_FLOAT_FRES
> and make FSEL depend on the FRES bit in translate.c
> 

Alternatively, you could add the new flag to PPC2_xxx .

>> +
>>      /* Vector/SIMD extensions                                                */
>>      /*   Altivec support                                                     */
>>      PPC_ALTIVEC        = 0x0000000001000000ULL,
>> @@ -1957,7 +1960,7 @@ enum {
>>                          | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
>>                          | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
>>                          | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
>> -                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
>> +                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | PPC_FLOAT_64 \
>>                          | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
>>                          | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
>>                          | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index b4dedce..073bef1 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -3899,7 +3899,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
>>      pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
>>  #ifdef PPC440x5_HAVE_FPU
>>                         PPC_FLOAT | PPC_FLOAT_FSQRT | 
>> -                       PPC_FLOAT_STFIWX |
>> +                       PPC_FLOAT_STFIWX | PPC_FLOAT_64 |
>>  #endif
>>                         PPC_DCR | PPC_WRTEE | PPC_RFMCI |
>>                         PPC_CACHE | PPC_CACHE_ICBI |
>>

[Qemu-devel] [PATCH 3/3] target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and remove their TARGET_PPC64 restriction

[Pierre Mallard]

Apply the new PPC_FLOAT_64 flag to fctid[z] and fcfid. 
May also be applyed to fctidu[z] and fcfid[su][z], but since they are not 
mentionned in xilinx documentation it might not be needed yet.

Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
---
 target-ppc/fpu_helper.c |    7 +++----
 target-ppc/helper.h     |    6 ++++--
 target-ppc/translate.c  |   20 ++++++++++++--------
 3 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index da93d12..4e0e9e2 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -649,15 +649,13 @@ FPU_FCTI(fctiw, int32, 0x80000000U)
 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
 FPU_FCTI(fctiwu, uint32, 0x00000000U)
 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
-#if defined(TARGET_PPC64)
 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
+#if defined(TARGET_PPC64)
 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
 #endif
 
-#if defined(TARGET_PPC64)
-
 #define FPU_FCFI(op, cvtr, is_single)                      \
 uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
 {                                                          \
@@ -674,10 +672,11 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
 }
 
 FPU_FCFI(fcfid, int64_to_float64, 0)
+
+#if defined(TARGET_PPC64)
 FPU_FCFI(fcfids, int64_to_float32, 1)
 FPU_FCFI(fcfidu, uint64_to_float64, 0)
 FPU_FCFI(fcfidus, uint64_to_float32, 1)
-
 #endif
 
 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 509eae5..e51aa69 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -67,14 +67,16 @@ DEF_HELPER_2(fctiw, i64, env, i64)
 DEF_HELPER_2(fctiwu, i64, env, i64)
 DEF_HELPER_2(fctiwz, i64, env, i64)
 DEF_HELPER_2(fctiwuz, i64, env, i64)
-#if defined(TARGET_PPC64)
 DEF_HELPER_2(fcfid, i64, env, i64)
+#if defined(TARGET_PPC64)
 DEF_HELPER_2(fcfidu, i64, env, i64)
 DEF_HELPER_2(fcfids, i64, env, i64)
 DEF_HELPER_2(fcfidus, i64, env, i64)
+#endif
 DEF_HELPER_2(fctid, i64, env, i64)
-DEF_HELPER_2(fctidu, i64, env, i64)
 DEF_HELPER_2(fctidz, i64, env, i64)
+#if defined(TARGET_PPC64)
+DEF_HELPER_2(fctidu, i64, env, i64)
 DEF_HELPER_2(fctiduz, i64, env, i64)
 #endif
 DEF_HELPER_2(frsp, i64, env, i64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c07bb01..6af25fe 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2246,21 +2246,23 @@ GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
 /* frsp */
 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
-#if defined(TARGET_PPC64)
 /* fcfid */
-GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
+GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_FLOAT_64|PPC_64B);
+#if defined(TARGET_PPC64)
 /* fcfids */
 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
 /* fcfidu */
 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
 /* fcfidus */
 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
+#endif
 /* fctid */
-GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
+GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_FLOAT_64|PPC_64B);
+/* fctidz */
+GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_FLOAT_64|PPC_64B);
+#if defined(TARGET_PPC64)
 /* fctidu */
 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
-/* fctidz */
-GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
 /* fctidu */
 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
 #endif
@@ -10050,14 +10052,16 @@ GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
+GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_FLOAT_64|PPC_64B),
 #if defined(TARGET_PPC64)
-GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
+#endif
+GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_FLOAT_64|PPC_64B),
+GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_FLOAT_64|PPC_64B),
+#if defined(TARGET_PPC64)
 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
 #endif
 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
-- 
1.7.10.4

Re: [Qemu-devel] [Qemu-ppc] [PATCH 3/3] target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and remove their TARGET_PPC64 restriction

[Alexander Graf]

On 10.09.14 07:03, Pierre Mallard wrote:
> Apply the new PPC_FLOAT_64 flag to fctid[z] and fcfid. 
> May also be applyed to fctidu[z] and fcfid[su][z], but since they are not 
> mentionned in xilinx documentation it might not be needed yet.
> 
> Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
> ---
>  target-ppc/fpu_helper.c |    7 +++----
>  target-ppc/helper.h     |    6 ++++--
>  target-ppc/translate.c  |   20 ++++++++++++--------
>  3 files changed, 19 insertions(+), 14 deletions(-)
> 
> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> index da93d12..4e0e9e2 100644
> --- a/target-ppc/fpu_helper.c
> +++ b/target-ppc/fpu_helper.c
> @@ -649,15 +649,13 @@ FPU_FCTI(fctiw, int32, 0x80000000U)
>  FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
>  FPU_FCTI(fctiwu, uint32, 0x00000000U)
>  FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
> -#if defined(TARGET_PPC64)
>  FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
>  FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
> +#if defined(TARGET_PPC64)
>  FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
>  FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
>  #endif
>  
> -#if defined(TARGET_PPC64)
> -
>  #define FPU_FCFI(op, cvtr, is_single)                      \
>  uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
>  {                                                          \
> @@ -674,10 +672,11 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
>  }
>  
>  FPU_FCFI(fcfid, int64_to_float64, 0)
> +
> +#if defined(TARGET_PPC64)
>  FPU_FCFI(fcfids, int64_to_float32, 1)
>  FPU_FCFI(fcfidu, uint64_to_float64, 0)
>  FPU_FCFI(fcfidus, uint64_to_float32, 1)
> -
>  #endif
>  
>  static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 509eae5..e51aa69 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -67,14 +67,16 @@ DEF_HELPER_2(fctiw, i64, env, i64)
>  DEF_HELPER_2(fctiwu, i64, env, i64)
>  DEF_HELPER_2(fctiwz, i64, env, i64)
>  DEF_HELPER_2(fctiwuz, i64, env, i64)
> -#if defined(TARGET_PPC64)
>  DEF_HELPER_2(fcfid, i64, env, i64)
> +#if defined(TARGET_PPC64)
>  DEF_HELPER_2(fcfidu, i64, env, i64)
>  DEF_HELPER_2(fcfids, i64, env, i64)
>  DEF_HELPER_2(fcfidus, i64, env, i64)
> +#endif
>  DEF_HELPER_2(fctid, i64, env, i64)
> -DEF_HELPER_2(fctidu, i64, env, i64)
>  DEF_HELPER_2(fctidz, i64, env, i64)
> +#if defined(TARGET_PPC64)
> +DEF_HELPER_2(fctidu, i64, env, i64)
>  DEF_HELPER_2(fctiduz, i64, env, i64)
>  #endif
>  DEF_HELPER_2(frsp, i64, env, i64)
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index c07bb01..6af25fe 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -2246,21 +2246,23 @@ GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
>  GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
>  /* frsp */
>  GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
> -#if defined(TARGET_PPC64)
>  /* fcfid */
> -GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
> +GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_FLOAT_64|PPC_64B);
> +#if defined(TARGET_PPC64)
>  /* fcfids */
>  GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
>  /* fcfidu */
>  GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
>  /* fcfidus */
>  GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
> +#endif
>  /* fctid */
> -GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
> +GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_FLOAT_64|PPC_64B);
> +/* fctidz */
> +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_FLOAT_64|PPC_64B);
> +#if defined(TARGET_PPC64)
>  /* fctidu */
>  GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
> -/* fctidz */
> -GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
>  /* fctidu */
>  GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
>  #endif
> @@ -10050,14 +10052,16 @@ GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>  GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
>  GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>  GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
> +GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_FLOAT_64|PPC_64B),
>  #if defined(TARGET_PPC64)
> -GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
>  GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>  GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>  GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
> -GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
> +#endif
> +GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_FLOAT_64|PPC_64B),
> +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_FLOAT_64|PPC_64B),

I think we're better off with only a single bit. Just make all 64bit
CPUs that have an FPU also set PPC_FLOAT_64 and only check for that.


Alex

Re: [Qemu-devel] [Qemu-ppc] [PATCH 3/3] target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and remove their TARGET_PPC64 restriction

[Tom Musta]

On 9/10/2014 4:19 AM, Alexander Graf wrote:
> 
> 
> On 10.09.14 07:03, Pierre Mallard wrote:
>> Apply the new PPC_FLOAT_64 flag to fctid[z] and fcfid. 
>> May also be applyed to fctidu[z] and fcfid[su][z], but since they are not 
>> mentionned in xilinx documentation it might not be needed yet.
>>
>> Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
>> ---
>>  target-ppc/fpu_helper.c |    7 +++----
>>  target-ppc/helper.h     |    6 ++++--
>>  target-ppc/translate.c  |   20 ++++++++++++--------
>>  3 files changed, 19 insertions(+), 14 deletions(-)
>>
>> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
>> index da93d12..4e0e9e2 100644
>> --- a/target-ppc/fpu_helper.c
>> +++ b/target-ppc/fpu_helper.c
>> @@ -649,15 +649,13 @@ FPU_FCTI(fctiw, int32, 0x80000000U)
>>  FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
>>  FPU_FCTI(fctiwu, uint32, 0x00000000U)
>>  FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
>> -#if defined(TARGET_PPC64)
>>  FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
>>  FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
>> +#if defined(TARGET_PPC64)
>>  FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
>>  FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
>>  #endif

So fctid[z] are being handled by this new flag but fctidu[z] are not?  Uggh.
>>  
>> -#if defined(TARGET_PPC64)
>> -
>>  #define FPU_FCFI(op, cvtr, is_single)                      \
>>  uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
>>  {                                                          \
>> @@ -674,10 +672,11 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
>>  }
>>  
>>  FPU_FCFI(fcfid, int64_to_float64, 0)
>> +
>> +#if defined(TARGET_PPC64)
>>  FPU_FCFI(fcfids, int64_to_float32, 1)
>>  FPU_FCFI(fcfidu, uint64_to_float64, 0)
>>  FPU_FCFI(fcfidus, uint64_to_float32, 1)
>> -
>>  #endif
>>  
>>  static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index 509eae5..e51aa69 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -67,14 +67,16 @@ DEF_HELPER_2(fctiw, i64, env, i64)
>>  DEF_HELPER_2(fctiwu, i64, env, i64)
>>  DEF_HELPER_2(fctiwz, i64, env, i64)
>>  DEF_HELPER_2(fctiwuz, i64, env, i64)
>> -#if defined(TARGET_PPC64)
>>  DEF_HELPER_2(fcfid, i64, env, i64)
>> +#if defined(TARGET_PPC64)
>>  DEF_HELPER_2(fcfidu, i64, env, i64)
>>  DEF_HELPER_2(fcfids, i64, env, i64)
>>  DEF_HELPER_2(fcfidus, i64, env, i64)
>> +#endif
>>  DEF_HELPER_2(fctid, i64, env, i64)
>> -DEF_HELPER_2(fctidu, i64, env, i64)
>>  DEF_HELPER_2(fctidz, i64, env, i64)
>> +#if defined(TARGET_PPC64)
>> +DEF_HELPER_2(fctidu, i64, env, i64)
>>  DEF_HELPER_2(fctiduz, i64, env, i64)
>>  #endif
>>  DEF_HELPER_2(frsp, i64, env, i64)
>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>> index c07bb01..6af25fe 100644
>> --- a/target-ppc/translate.c
>> +++ b/target-ppc/translate.c
>> @@ -2246,21 +2246,23 @@ GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
>>  GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
>>  /* frsp */
>>  GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
>> -#if defined(TARGET_PPC64)
>>  /* fcfid */
>> -GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
>> +GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_FLOAT_64|PPC_64B);

Given the limited scope of the flag (see my previous comment), I dont think PPC_FLOAT_64 is a very good name for this.  The semantic of this flag derived from your implementation is really limited to fcfid/fctid, fctidz
>> +#if defined(TARGET_PPC64)
>>  /* fcfids */
>>  GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
>>  /* fcfidu */
>>  GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
>>  /* fcfidus */
>>  GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
>> +#endif
>>  /* fctid */
>> -GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
>> +GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_FLOAT_64|PPC_64B);
>> +/* fctidz */
>> +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_FLOAT_64|PPC_64B);
>> +#if defined(TARGET_PPC64)
>>  /* fctidu */
>>  GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
>> -/* fctidz */
>> -GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
>>  /* fctidu */
>>  GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
>>  #endif
>> @@ -10050,14 +10052,16 @@ GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>>  GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
>>  GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>>  GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
>> +GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_FLOAT_64|PPC_64B),
>>  #if defined(TARGET_PPC64)
>> -GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
>>  GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>>  GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>>  GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
>> -GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
>> +#endif
>> +GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_FLOAT_64|PPC_64B),
>> +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_FLOAT_64|PPC_64B),
> 
> I think we're better off with only a single bit. Just make all 64bit
> CPUs that have an FPU also set PPC_FLOAT_64 and only check for that.
> 
> 
> Alex
> 

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Alexander Graf]

On 10.09.14 07:03, Pierre Mallard wrote:
> This patch series enable floating point instruction in 440x5 CPUs 
> which have the capabilities to have optional APU FPU.
> 
> 1) Add floating point standard insns flag to 440x5 in case there is an apu fpu.
> 2) Define a new floating point insns flag for operation 
> previously reserved to 64 bits proc (fcfid, fctid, fctidz)
> 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64 
> restrictions

I've looked through the patches mostly from a stylistic point of view.
As for whether the changes are technically correct and fully adhere to
the specs, I haven't verified anything and would leave that part to Tom :).


Alex

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Tom Musta]

On 9/10/2014 4:20 AM, Alexander Graf wrote:
> 
> 
> On 10.09.14 07:03, Pierre Mallard wrote:
>> This patch series enable floating point instruction in 440x5 CPUs 
>> which have the capabilities to have optional APU FPU.
>>
>> 1) Add floating point standard insns flag to 440x5 in case there is an apu fpu.
>> 2) Define a new floating point insns flag for operation 
>> previously reserved to 64 bits proc (fcfid, fctid, fctidz)
>> 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64 
>> restrictions
> 
> I've looked through the patches mostly from a stylistic point of view.
> As for whether the changes are technically correct and fully adhere to
> the specs, I haven't verified anything and would leave that part to Tom :).
> 

I went back to some old (paper) versions of the ISA circa 1998 and the Floating Convert To/From Doubleword instructions all have this clause:

"This instruction is defined only for 64-bit implementations.  Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked."

I believe this view of things was in play for the 60x and PowerMAC era 32-bit CPUs.  Which is consistent with the existing QEMU implementation.

The next revision of the spec that I have is Power ISA 2.03 (2006) and the clause is gone.  Furthermore, the instructions are *NOT* in the "64" category.

To complicate matters more, the unsigned integer versions were added in ISA 2.06 (fcfidu, fctidu, fctiduz).  QEMU deals with these via the PPC2_FP_CVT_ISA206 flag.

My interpretation is that all of the fc[tf]id[*] instructions are a required part of any Power floating point implementation -- 32-bit or 64-bit is irrelevant.

Based on all of this, I think it would make sense to do the following in this patch series:

(1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer Conversion instructions.

(2) Defined a new flag for FP Signed Doubleword Conversion instructions (PPC2_FP_CVT_S64).  Use this flag exclusively when defining the opcode tables, e.g.

+/* fctidz */
+GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);


(3) You would have to add the flag to all existing 64-bit CPUs that support floating point.  And of course, to your new 440-w-fpu CPU.

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Pierre Mallard]

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Thanks for your review Alexander and Tom. All your proposition looks fine
to me.
Xilinx Virtex5 is not ISA compliant and does not support unsigned
conversions, that's why I left all unsigned version as it was but you are
right, PPC_FLOAT_64 is such a bad name !
Adding this flag to all CPU seems ok since it shall result in looking those
that defined the PPC_64B flag.
Will repost a patch in a few days taking in account your comments.
Pierre

On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta <tommusta@gmail.com> wrote:

> On 9/10/2014 4:20 AM, Alexander Graf wrote:
> >
> >
> > On 10.09.14 07:03, Pierre Mallard wrote:
> >> This patch series enable floating point instruction in 440x5 CPUs
> >> which have the capabilities to have optional APU FPU.
> >>
> >> 1) Add floating point standard insns flag to 440x5 in case there is an
> apu fpu.
> >> 2) Define a new floating point insns flag for operation
> >> previously reserved to 64 bits proc (fcfid, fctid, fctidz)
> >> 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64
> >> restrictions
> >
> > I've looked through the patches mostly from a stylistic point of view.
> > As for whether the changes are technically correct and fully adhere to
> > the specs, I haven't verified anything and would leave that part to Tom
> :).
> >
>
> I went back to some old (paper) versions of the ISA circa 1998 and the
> Floating Convert To/From Doubleword instructions all have this clause:
>
> "This instruction is defined only for 64-bit implementations.  Using it on
> a 32-bit implementation will cause the system illegal instruction error
> handler to be invoked."
>
> I believe this view of things was in play for the 60x and PowerMAC era
> 32-bit CPUs.  Which is consistent with the existing QEMU implementation.
>
> The next revision of the spec that I have is Power ISA 2.03 (2006) and the
> clause is gone.  Furthermore, the instructions are *NOT* in the "64"
> category.
>
> To complicate matters more, the unsigned integer versions were added in
> ISA 2.06 (fcfidu, fctidu, fctiduz).  QEMU deals with these via the
> PPC2_FP_CVT_ISA206 flag.
>
> My interpretation is that all of the fc[tf]id[*] instructions are a
> required part of any Power floating point implementation -- 32-bit or
> 64-bit is irrelevant.
>
> Based on all of this, I think it would make sense to do the following in
> this patch series:
>
> (1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer
> Conversion instructions.
>
> (2) Defined a new flag for FP Signed Doubleword Conversion instructions
> (PPC2_FP_CVT_S64).  Use this flag exclusively when defining the opcode
> tables, e.g.
>
> +/* fctidz */
> +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
>
>
> (3) You would have to add the flag to all existing 64-bit CPUs that
> support floating point.  And of course, to your new 440-w-fpu CPU.
>

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Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Pierre Mallard]

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On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta <tommusta@gmail.com> wrote:

>
> (1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer
> Conversion instructions.
>

There is also fcfids and fcfidus which leads to 8 instructions (fcfid,
fcfids, fcfidu, fcfidus and fctid, fctidz, fctidu, fctiduz), is this right ?

>
> (2) Defined a new flag for FP Signed Doubleword Conversion instructions
> (PPC2_FP_CVT_S64).  Use this flag exclusively when defining the opcode
> tables, e.g.
>
> +/* fctidz */
> +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
>
> I'm not sure, I did understand correctly that one, indeed to have the flag
check I have to make changes for each of the three instructions (fcfid,
fctif, fctidz) at 2 places in translate.c :

One at the gen_XXXX function definition which is quite straight forward :
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
becomes
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);

One in the Opcode Table which requires to use the GEN_HANDLER_E macro for
the second type to be taken in account :
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64),
becomes
GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE,
PPC2_FP_CVT_S64)

is this right ?


>
> (3) You would have to add the flag to all existing 64-bit CPUs that
> support floating point.  And of course, to your new 440-w-fpu CPU.
>

Pierre

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Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs

[Tom Musta]

On 9/10/2014 5:43 PM, Pierre Mallard wrote:
> On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta <tommusta@gmail.com <mailto:tommusta@gmail.com>> wrote:
> 
> 
>     (1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer Conversion instructions.
> 
> 
> There is also fcfids and fcfidus which leads to 8 instructions (fcfid, fcfids, fcfidu, fcfidus and fctid, fctidz, fctidu, fctiduz), is this right ?

You are correct.

> 
> 
>     (2) Defined a new flag for FP Signed Doubleword Conversion instructions (PPC2_FP_CVT_S64).  Use this flag exclusively when defining the opcode tables, e.g.
> 
>     +/* fctidz */
>     +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
> 
> I'm not sure, I did understand correctly that one, indeed to have the flag check I have to make changes for each of the three instructions (fcfid, fctif, fctidz) at 2 places in translate.c :
> 
> One at the gen_XXXX function definition which is quite straight forward :
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
> becomes
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
> 
> One in the Opcode Table which requires to use the GEN_HANDLER_E macro for the second type to be taken in account :
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64),
> becomes
> GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64)
> 
> is this right ?

Yes.

>  
> 
> 
>     (3) You would have to add the flag to all existing 64-bit CPUs that support floating point.  And of course, to your new 440-w-fpu CPU.
> 
>  
> Pierre