[U-Boot] [PATCH v4 0/4] rockchip: rk3288: add fastboot support

[U-Boot] [PATCH v4 0/4] rockchip: rk3288: add fastboot support

[Ziyuan Xu]

This patchset add the fastboot support for rk3288, and I have tested on
firefly-rk3288 & evb-rk3288 board.

Fix an issue which was mentioned in V1's cover-letter:
The DMA buffer was always zero after DMA transmission is compete, it
takes no effect that invalidate dcache after DMA transfer completed and
before the CPU readed. It's important to invalidate dcache before
starting DMA, ensure coherency and prevent from any dirty lines in the
cache which from the DMA buffer.


Changes in v4:
- Implement a mechanism to be compatible with more Rockchip SoCs
- Rename rockchip_usb_syno_phy.c to rockchip_usb2_phy.c
- Rework fifo size getting and setting
- Update commit message
- Add fifo size for rk3288
- Get usb_phy's dt_node

Changes in v3:
- Make UOC_CON registers to be unfixed which should be got from DT
- Achieve UOC_CON_OFFSET physical address from DT
- New commit since v3 to fix the coherence issue between memory and
cache

Changes in v2:
- Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c
- Rework the behaviour in otg_phy_init() and otg_phy_off()
- Update detailed commit message
- Modify the macro's values
- Achieve the regs_phy from DT
- Update comments a little

Xu Ziyuan (4):
  usb: rockchip-phy: implement USB2.0 phy control
  usb: dwc2-otg: adjust fifo size via platform data
  rockchip: rk3288: add fastboot support
  usb: dwc2 : invalidate dcache before starting DMA

 arch/arm/dts/rk3288.dtsi                   |   1 +
 arch/arm/mach-rockchip/board.c             |  72 +++++++++++++++++++
 drivers/usb/gadget/dwc2_udc_otg.c          |  22 ++++--
 drivers/usb/gadget/dwc2_udc_otg_regs.h     |   6 +-
 drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |   3 +
 drivers/usb/phy/Makefile                   |   1 +
 drivers/usb/phy/rockchip_usb2_phy.c        | 107 +++++++++++++++++++++++++++++
 include/configs/rk3288_common.h            |  26 +++++++
 include/usb/dwc2_udc.h                     |   5 ++
 9 files changed, 234 insertions(+), 9 deletions(-)
 create mode 100644 drivers/usb/phy/rockchip_usb2_phy.c

-- 
1.9.1

[U-Boot] [PATCH v4 1/4] usb: rockchip-phy: implement USB2.0 phy control

[Ziyuan Xu]

From: Xu Ziyuan <xzy.xu@rock-chips.com>

So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and
Innosilicon. This patch applys dwc2 usb driver framework to implement
phy_init() and phy_off() methods for Synopsys phy on Rockchip platform.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

---

Changes in v4:
- Implement a mechanism to be compatible with more Rockchip SoCs
- Rename rockchip_usb_syno_phy.c to rockchip_usb2_phy.c

Changes in v3:
- Make UOC_CON registers to be unfixed which should be got from DT

Changes in v2:
- Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c
- Rework the behaviour in otg_phy_init() and otg_phy_off()

 drivers/usb/phy/Makefile            |   1 +
 drivers/usb/phy/rockchip_usb2_phy.c | 107 ++++++++++++++++++++++++++++++++++++
 include/usb/dwc2_udc.h              |   2 +
 3 files changed, 110 insertions(+)
 create mode 100644 drivers/usb/phy/rockchip_usb2_phy.c

diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 93d147e..4e548c2 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -7,3 +7,4 @@
 
 obj-$(CONFIG_TWL4030_USB) += twl4030.o
 obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o
+obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o
diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c
new file mode 100644
index 0000000..1958478
--- /dev/null
+++ b/drivers/usb/phy/rockchip_usb2_phy.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <libfdt.h>
+
+#include "../gadget/dwc2_udc_otg_priv.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT_WRITEABLE_SHIFT	16
+
+struct usb2phy_reg {
+	unsigned int offset;
+	unsigned int bitend;
+	unsigned int bitstart;
+	unsigned int disable;
+	unsigned int enable;
+};
+
+/**
+ * struct rockchip_usb2_phy_cfg: usb-phy port configuration
+ * @port_reset: usb otg per-port reset register
+ * @soft_con: software control usb otg register
+ * @suspend: phy suspend register
+ */
+struct rockchip_usb2_phy_cfg {
+	struct usb2phy_reg port_reset;
+	struct usb2phy_reg soft_con;
+	struct usb2phy_reg suspend;
+};
+
+struct rockchip_usb2_phy_dt_id {
+	char		compatible[128];
+	const void	*data;
+};
+
+static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
+	.port_reset     = {0x00, 12, 12, 0, 1},
+	.soft_con       = {0x08, 2, 2, 0, 1},
+	.suspend	= {0x0c, 5, 0, 0x01, 0x2A},
+};
+
+static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
+	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
+	{}
+};
+
+static void property_enable(struct dwc2_plat_otg_data *pdata,
+				  const struct usb2phy_reg *reg, bool en)
+{
+	unsigned int val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	writel(val, pdata->regs_phy + reg->offset);
+}
+
+
+void otg_phy_init(struct dwc2_udc *dev)
+{
+	struct dwc2_plat_otg_data *pdata = dev->pdata;
+	struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
+	struct rockchip_usb2_phy_dt_id *of_id;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
+		of_id = &rockchip_usb2_phy_dt_ids[i];
+		if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node,
+					      of_id->compatible) == 0) {
+			phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
+			break;
+		}
+	}
+	if (!phy_cfg) {
+		debug("Can't find device platform data\n");
+
+		hang();
+		return;
+	}
+	pdata->priv = phy_cfg;
+	/* disable software control */
+	property_enable(pdata, &phy_cfg->soft_con, false);
+
+	/* reset otg port */
+	property_enable(pdata, &phy_cfg->port_reset, true);
+	mdelay(1);
+	property_enable(pdata, &phy_cfg->port_reset, false);
+	udelay(1);
+}
+
+void otg_phy_off(struct dwc2_udc *dev)
+{
+	struct dwc2_plat_otg_data *pdata = dev->pdata;
+	struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
+
+	/* enable software control */
+	property_enable(pdata, &phy_cfg->soft_con, true);
+	/* enter suspend */
+	property_enable(pdata, &phy_cfg->suspend, true);
+}
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index 302e9a3..3ce43f8 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -12,6 +12,8 @@
 #define PHY0_SLEEP              (1 << 5)
 
 struct dwc2_plat_otg_data {
+	void		*priv;
+	int		phy_of_node;
 	int		(*phy_control)(int on);
 	unsigned int	regs_phy;
 	unsigned int	regs_otg;
-- 
1.9.1

[U-Boot] [PATCH v4 1/4] usb: rockchip-phy: implement USB2.0 phy control

[Simon Glass]

On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>
> So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and
> Innosilicon. This patch applys dwc2 usb driver framework to implement
> phy_init() and phy_off() methods for Synopsys phy on Rockchip platform.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> ---
>
> Changes in v4:
> - Implement a mechanism to be compatible with more Rockchip SoCs
> - Rename rockchip_usb_syno_phy.c to rockchip_usb2_phy.c
>
> Changes in v3:
> - Make UOC_CON registers to be unfixed which should be got from DT
>
> Changes in v2:
> - Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c
> - Rework the behaviour in otg_phy_init() and otg_phy_off()
>
>  drivers/usb/phy/Makefile            |   1 +
>  drivers/usb/phy/rockchip_usb2_phy.c | 107 ++++++++++++++++++++++++++++++++++++
>  include/usb/dwc2_udc.h              |   2 +
>  3 files changed, 110 insertions(+)
>  create mode 100644 drivers/usb/phy/rockchip_usb2_phy.c

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v4 1/4] usb: rockchip-phy: implement USB2.0 phy control

[Simon Glass]

On 14 July 2016 at 21:20, Simon Glass <sjg@chromium.org> wrote:
> On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>
>> So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and
>> Innosilicon. This patch applys dwc2 usb driver framework to implement
>> phy_init() and phy_off() methods for Synopsys phy on Rockchip platform.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> ---
>>
>> Changes in v4:
>> - Implement a mechanism to be compatible with more Rockchip SoCs
>> - Rename rockchip_usb_syno_phy.c to rockchip_usb2_phy.c
>>
>> Changes in v3:
>> - Make UOC_CON registers to be unfixed which should be got from DT
>>
>> Changes in v2:
>> - Rename rk3288_usb_phy.c to rockchip_usb_syno_phy.c
>> - Rework the behaviour in otg_phy_init() and otg_phy_off()
>>
>>  drivers/usb/phy/Makefile            |   1 +
>>  drivers/usb/phy/rockchip_usb2_phy.c | 107 ++++++++++++++++++++++++++++++++++++
>>  include/usb/dwc2_udc.h              |   2 +
>>  3 files changed, 110 insertions(+)
>>  create mode 100644 drivers/usb/phy/rockchip_usb2_phy.c
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip, thanks!

[U-Boot] [PATCH v4 2/4] usb: dwc2-otg: adjust fifo size via platform data

[Ziyuan Xu]

From: Xu Ziyuan <xzy.xu@rock-chips.com>

The total FIFO size of some SoCs may be different from the existen, this
patch supports fifo size setting from platform data.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

---

Changes in v4:
- Rework fifo size getting and setting
- Update commit message

Changes in v3: None
Changes in v2:
- Update detailed commit message
- Modify the macro's values

 drivers/usb/gadget/dwc2_udc_otg.c      | 22 ++++++++++++++++------
 drivers/usb/gadget/dwc2_udc_otg_regs.h |  6 +++---
 include/usb/dwc2_udc.h                 |  3 +++
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index a23278d..029927f 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -403,6 +403,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 	int i;
 	unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
 	uint32_t dflt_gusbcfg;
+	uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
 
 	debug("Reseting OTG controller\n");
 
@@ -467,18 +468,27 @@ static void reconfig_usbd(struct dwc2_udc *dev)
 	/* 10. Unmask device IN EP common interrupts*/
 	writel(DIEPMSK_INIT, &reg->diepmsk);
 
+	rx_fifo_sz = RX_FIFO_SIZE;
+	np_tx_fifo_sz = NPTX_FIFO_SIZE;
+	tx_fifo_sz = PTX_FIFO_SIZE;
+
+	if (dev->pdata->rx_fifo_sz)
+		rx_fifo_sz = dev->pdata->rx_fifo_sz;
+	if (dev->pdata->np_tx_fifo_sz)
+		np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
+	if (dev->pdata->tx_fifo_sz)
+		tx_fifo_sz = dev->pdata->tx_fifo_sz;
+
 	/* 11. Set Rx FIFO Size (in 32-bit words) */
-	writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
+	writel(rx_fifo_sz, &reg->grxfsiz);
 
 	/* 12. Set Non Periodic Tx FIFO Size */
-	writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
+	writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
 	       &reg->gnptxfsiz);
 
 	for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
-		writel((PTX_FIFO_SIZE >> 2) << 16 |
-		       ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
-			 PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
-		       &reg->dieptxf[i-1]);
+		writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
+			tx_fifo_sz << 16, &reg->dieptxf[i-1]);
 
 	/* Flush the RX FIFO */
 	writel(RX_FIFO_FLUSH, &reg->grstctl);
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h
index 78ec90e..c94396a 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
+++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
@@ -130,9 +130,9 @@ struct dwc2_usbotg_reg {
 #define HIGH_SPEED_CONTROL_PKT_SIZE	64
 #define HIGH_SPEED_BULK_PKT_SIZE	512
 
-#define RX_FIFO_SIZE			(1024*4)
-#define NPTX_FIFO_SIZE			(1024*4)
-#define PTX_FIFO_SIZE			(1536*1)
+#define RX_FIFO_SIZE			(1024)
+#define NPTX_FIFO_SIZE			(1024)
+#define PTX_FIFO_SIZE			(384)
 
 #define DEPCTL_TXFNUM_0		(0x0<<22)
 #define DEPCTL_TXFNUM_1		(0x1<<22)
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index 3ce43f8..7324d8a 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -20,6 +20,9 @@ struct dwc2_plat_otg_data {
 	unsigned int    usb_phy_ctrl;
 	unsigned int    usb_flags;
 	unsigned int	usb_gusbcfg;
+	unsigned int	rx_fifo_sz;
+	unsigned int	np_tx_fifo_sz;
+	unsigned int	tx_fifo_sz;
 };
 
 int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata);
-- 
1.9.1

[U-Boot] [PATCH v4 2/4] usb: dwc2-otg: adjust fifo size via platform data

[Simon Glass]

On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>
> The total FIFO size of some SoCs may be different from the existen, this
> patch supports fifo size setting from platform data.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> ---
>
> Changes in v4:
> - Rework fifo size getting and setting
> - Update commit message
>
> Changes in v3: None
> Changes in v2:
> - Update detailed commit message
> - Modify the macro's values
>
>  drivers/usb/gadget/dwc2_udc_otg.c      | 22 ++++++++++++++++------
>  drivers/usb/gadget/dwc2_udc_otg_regs.h |  6 +++---
>  include/usb/dwc2_udc.h                 |  3 +++
>  3 files changed, 22 insertions(+), 9 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v4 2/4] usb: dwc2-otg: adjust fifo size via platform data

[Simon Glass]

On 14 July 2016 at 21:20, Simon Glass <sjg@chromium.org> wrote:
> On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>
>> The total FIFO size of some SoCs may be different from the existen, this
>> patch supports fifo size setting from platform data.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> ---
>>
>> Changes in v4:
>> - Rework fifo size getting and setting
>> - Update commit message
>>
>> Changes in v3: None
>> Changes in v2:
>> - Update detailed commit message
>> - Modify the macro's values
>>
>>  drivers/usb/gadget/dwc2_udc_otg.c      | 22 ++++++++++++++++------
>>  drivers/usb/gadget/dwc2_udc_otg_regs.h |  6 +++---
>>  include/usb/dwc2_udc.h                 |  3 +++
>>  3 files changed, 22 insertions(+), 9 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip, thanks!

[U-Boot] [PATCH v4 2/4] usb: dwc2-otg: adjust fifo size via platform data

[Marek Vasut]

On 07/15/2016 05:56 AM, Simon Glass wrote:
> On 14 July 2016 at 21:20, Simon Glass <sjg@chromium.org> wrote:
>> On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>>
>>> The total FIFO size of some SoCs may be different from the existen, this
>>> patch supports fifo size setting from platform data.
>>>
>>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>>
>>> ---
>>>
>>> Changes in v4:
>>> - Rework fifo size getting and setting
>>> - Update commit message
>>>
>>> Changes in v3: None
>>> Changes in v2:
>>> - Update detailed commit message
>>> - Modify the macro's values
>>>
>>>  drivers/usb/gadget/dwc2_udc_otg.c      | 22 ++++++++++++++++------
>>>  drivers/usb/gadget/dwc2_udc_otg_regs.h |  6 +++---
>>>  include/usb/dwc2_udc.h                 |  3 +++
>>>  3 files changed, 22 insertions(+), 9 deletions(-)
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>
> Applied to u-boot-rockchip, thanks!
>

Simon, I see you're now picking generic usb gadget code via platform 
tree. This is NOT OK, there is a tree for usb gadget code and this 
should go through that tree. I would be glad if this didn't repeat.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH v4 2/4] usb: dwc2-otg: adjust fifo size via platform data

[Simon Glass]

Hi Marek,

On 15 July 2016 at 23:43, Marek Vasut <marex@denx.de> wrote:
> On 07/15/2016 05:56 AM, Simon Glass wrote:
>>
>> On 14 July 2016 at 21:20, Simon Glass <sjg@chromium.org> wrote:
>>>
>>> On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>>>>
>>>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>>>
>>>> The total FIFO size of some SoCs may be different from the existen, this
>>>> patch supports fifo size setting from platform data.
>>>>
>>>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>>>
>>>> ---
>>>>
>>>> Changes in v4:
>>>> - Rework fifo size getting and setting
>>>> - Update commit message
>>>>
>>>> Changes in v3: None
>>>> Changes in v2:
>>>> - Update detailed commit message
>>>> - Modify the macro's values
>>>>
>>>>  drivers/usb/gadget/dwc2_udc_otg.c      | 22 ++++++++++++++++------
>>>>  drivers/usb/gadget/dwc2_udc_otg_regs.h |  6 +++---
>>>>  include/usb/dwc2_udc.h                 |  3 +++
>>>>  3 files changed, 22 insertions(+), 9 deletions(-)
>>>
>>>
>>> Acked-by: Simon Glass <sjg@chromium.org>
>>
>>
>> Applied to u-boot-rockchip, thanks!
>>
>
> Simon, I see you're now picking generic usb gadget code via platform tree.
> This is NOT OK, there is a tree for usb gadget code and this should go
> through that tree. I would be glad if this didn't repeat.

Ah OK, sorry. I'll leave those alone from now on. Which one is it?

http://www.denx.de/wiki/U-Boot/Custodians

Are the patches OK as applied, or are there more comments?

Regards,
Simon

[U-Boot] [PATCH v4 3/4] rockchip: rk3288: add fastboot support

[Ziyuan Xu]

From: Xu Ziyuan <xzy.xu@rock-chips.com>

Enable fastboot feature on rk3288.

This path doesn't support the fastboot flash function command entirely.
We will hit "cannot find partition" assertion without specified
partition environment. Define gpt partition layout in specified board
such as firefly-rk3288, then enjoy it!

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

---

Changes in v4:
- Add fifo size for rk3288
- Get usb_phy's dt_node

Changes in v3:
- Achieve UOC_CON_OFFSET physical address from DT

Changes in v2:
- Achieve the regs_phy from DT
- Update comments a little

 arch/arm/dts/rk3288.dtsi        |  1 +
 arch/arm/mach-rockchip/board.c  | 72 +++++++++++++++++++++++++++++++++++++++++
 include/configs/rk3288_common.h | 26 +++++++++++++++
 3 files changed, 99 insertions(+)

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 3dab0fc..bcf051a 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -454,6 +454,7 @@
 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_OTG0>;
 		clock-names = "otg";
+		dr_mode = "otg";
 		phys = <&usbphy0>;
 		phy-names = "usb2-phy";
 		status = "disabled";
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 816540e..ab41877 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -52,6 +52,78 @@ void lowlevel_init(void)
 {
 }
 
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3288_otg_data = {
+	.rx_fifo_sz	= 512,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 512,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node, phy_node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+	u32 grf_phy_offset;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3288-usb");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node,
+					"rockchip,rk3288-usb");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+	rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	node = fdtdec_lookup_phandle(blob, node, "phys");
+	if (node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	phy_node = fdt_parent_offset(blob, node);
+	if (phy_node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	rk3288_otg_data.phy_of_node = phy_node;
+	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
+
+	/* find the grf node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3288-grf");
+	if (node <= 0) {
+		debug("Not found grf device\n");
+		return -ENODEV;
+	}
+	rk3288_otg_data.regs_phy = grf_phy_offset +
+				fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&rk3288_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif
+
 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 8adc26f..2040cdd 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -79,6 +79,32 @@
 #define CONFIG_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_ROCKCHIP_USB2_PHY
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+
+/* fastboot  */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	1	/* eMMC */
+/* stroe safely fastboot buffer data to the middle of bank */
+#define CONFIG_FASTBOOT_BUF_ADDR	(CONFIG_SYS_SDRAM_BASE \
+					+ SDRAM_BANK_SIZE / 2)
+#define CONFIG_FASTBOOT_BUF_SIZE	0x08000000
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER	"Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM		0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM	0x320a
+
+/* Enable gpt partition table */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 
-- 
1.9.1

[U-Boot] [PATCH v4 3/4] rockchip: rk3288: add fastboot support

[William.wu]

Hi Ziyuan Xu?


On 2016/7/14 14:52, Ziyuan Xu wrote:
> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>
> Enable fastboot feature on rk3288.
>
> This path doesn't support the fastboot flash function command entirely.
> We will hit "cannot find partition" assertion without specified
> partition environment. Define gpt partition layout in specified board
> such as firefly-rk3288, then enjoy it!
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> ---
>
> Changes in v4:
> - Add fifo size for rk3288
> - Get usb_phy's dt_node
>
> Changes in v3:
> - Achieve UOC_CON_OFFSET physical address from DT
>
> Changes in v2:
> - Achieve the regs_phy from DT
> - Update comments a little
>
>   arch/arm/dts/rk3288.dtsi        |  1 +
>   arch/arm/mach-rockchip/board.c  | 72 +++++++++++++++++++++++++++++++++++++++++
>   include/configs/rk3288_common.h | 26 +++++++++++++++
>   3 files changed, 99 insertions(+)
>
> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
> index 3dab0fc..bcf051a 100644
> --- a/arch/arm/dts/rk3288.dtsi
> +++ b/arch/arm/dts/rk3288.dtsi
> @@ -454,6 +454,7 @@
>   		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>   		clocks = <&cru HCLK_OTG0>;
>   		clock-names = "otg";
> +		dr_mode = "otg";
>   		phys = <&usbphy0>;
>   		phy-names = "usb2-phy";
>   		status = "disabled";
> diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
> index 816540e..ab41877 100644
> --- a/arch/arm/mach-rockchip/board.c
> +++ b/arch/arm/mach-rockchip/board.c
> @@ -52,6 +52,78 @@ void lowlevel_init(void)
>   {
>   }
>   
> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> +#include <usb.h>
> +#include <usb/dwc2_udc.h>
> +
> +static struct dwc2_plat_otg_data rk3288_otg_data = {
> +	.rx_fifo_sz	= 512,
> +	.np_tx_fifo_sz	= 16,
> +	.tx_fifo_sz	= 512,
> +};
> +
rk3288 otg port total fifo size is only 0x3cc ?972?this value is in 
terms of 32-bit words??
read from  GHWCFG3 register bit[31:16], it's smaller than the total fifo 
size you configured.

> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +	int node, phy_node;
> +	const char *mode;
> +	bool matched = false;
> +	const void *blob = gd->fdt_blob;
> +	u32 grf_phy_offset;
> +
> +	/* find the usb_otg node */
> +	node = fdt_node_offset_by_compatible(blob, -1,
> +					"rockchip,rk3288-usb");
> +
> +	while (node > 0) {
> +		mode = fdt_getprop(blob, node, "dr_mode", NULL);
> +		if (mode && strcmp(mode, "otg") == 0) {
> +			matched = true;
> +			break;
> +		}
> +
> +		node = fdt_node_offset_by_compatible(blob, node,
> +					"rockchip,rk3288-usb");
> +	}
> +	if (!matched) {
> +		debug("Not found usb_otg device\n");
> +		return -ENODEV;
> +	}
> +	rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> +
> +	node = fdtdec_lookup_phandle(blob, node, "phys");
> +	if (node <= 0) {
> +		debug("Not found usb phy device\n");
> +		return -ENODEV;
> +	}
> +
> +	phy_node = fdt_parent_offset(blob, node);
> +	if (phy_node <= 0) {
> +		debug("Not found usb phy device\n");
> +		return -ENODEV;
> +	}
> +
> +	rk3288_otg_data.phy_of_node = phy_node;
> +	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
> +
> +	/* find the grf node */
> +	node = fdt_node_offset_by_compatible(blob, -1,
> +					"rockchip,rk3288-grf");
> +	if (node <= 0) {
> +		debug("Not found grf device\n");
> +		return -ENODEV;
> +	}
> +	rk3288_otg_data.regs_phy = grf_phy_offset +
> +				fdtdec_get_addr(blob, node, "reg");
> +
> +	return dwc2_udc_probe(&rk3288_otg_data);
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> +	return 0;
> +}
> +#endif
> +
>   static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
>   		       char * const argv[])
>   {
> diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
> index 8adc26f..2040cdd 100644
> --- a/include/configs/rk3288_common.h
> +++ b/include/configs/rk3288_common.h
> @@ -79,6 +79,32 @@
>   #define CONFIG_SPI
>   #define CONFIG_SF_DEFAULT_SPEED 20000000
>   
> +/* usb otg */
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_DWC2_OTG
> +#define CONFIG_ROCKCHIP_USB2_PHY
> +#define CONFIG_USB_GADGET_VBUS_DRAW	0
> +
> +/* fastboot  */
> +#define CONFIG_CMD_FASTBOOT
> +#define CONFIG_USB_FUNCTION_FASTBOOT
> +#define CONFIG_FASTBOOT_FLASH
> +#define CONFIG_FASTBOOT_FLASH_MMC_DEV	1	/* eMMC */
> +/* stroe safely fastboot buffer data to the middle of bank */
> +#define CONFIG_FASTBOOT_BUF_ADDR	(CONFIG_SYS_SDRAM_BASE \
> +					+ SDRAM_BANK_SIZE / 2)
> +#define CONFIG_FASTBOOT_BUF_SIZE	0x08000000
> +
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_G_DNL_MANUFACTURER	"Rockchip"
> +#define CONFIG_G_DNL_VENDOR_NUM		0x2207
> +#define CONFIG_G_DNL_PRODUCT_NUM	0x320a
> +
> +/* Enable gpt partition table */
> +#define CONFIG_CMD_GPT
> +#define CONFIG_EFI_PARTITION
> +
>   #ifndef CONFIG_SPL_BUILD
>   #include <config_distro_defaults.h>
>   

[U-Boot] [PATCH v4 3/4] rockchip: rk3288: add fastboot support

[Ziyuan Xu]

Hi William,

On 2016?07?14? 19:06, William.wu wrote:
> Hi Ziyuan Xu?
>
>
> On 2016/7/14 14:52, Ziyuan Xu wrote:
>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>
>> Enable fastboot feature on rk3288.
>>
>> This path doesn't support the fastboot flash function command entirely.
>> We will hit "cannot find partition" assertion without specified
>> partition environment. Define gpt partition layout in specified board
>> such as firefly-rk3288, then enjoy it!
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> ---
>>
>> Changes in v4:
>> - Add fifo size for rk3288
>> - Get usb_phy's dt_node
>>
>> Changes in v3:
>> - Achieve UOC_CON_OFFSET physical address from DT
>>
>> Changes in v2:
>> - Achieve the regs_phy from DT
>> - Update comments a little
>>
>>   arch/arm/dts/rk3288.dtsi        |  1 +
>>   arch/arm/mach-rockchip/board.c  | 72 
>> +++++++++++++++++++++++++++++++++++++++++
>>   include/configs/rk3288_common.h | 26 +++++++++++++++
>>   3 files changed, 99 insertions(+)
>>
>> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
>> index 3dab0fc..bcf051a 100644
>> --- a/arch/arm/dts/rk3288.dtsi
>> +++ b/arch/arm/dts/rk3288.dtsi
>> @@ -454,6 +454,7 @@
>>           interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>>           clocks = <&cru HCLK_OTG0>;
>>           clock-names = "otg";
>> +        dr_mode = "otg";
>>           phys = <&usbphy0>;
>>           phy-names = "usb2-phy";
>>           status = "disabled";
>> diff --git a/arch/arm/mach-rockchip/board.c 
>> b/arch/arm/mach-rockchip/board.c
>> index 816540e..ab41877 100644
>> --- a/arch/arm/mach-rockchip/board.c
>> +++ b/arch/arm/mach-rockchip/board.c
>> @@ -52,6 +52,78 @@ void lowlevel_init(void)
>>   {
>>   }
>>   +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
>> +#include <usb.h>
>> +#include <usb/dwc2_udc.h>
>> +
>> +static struct dwc2_plat_otg_data rk3288_otg_data = {
>> +    .rx_fifo_sz    = 512,
>> +    .np_tx_fifo_sz    = 16,
>> +    .tx_fifo_sz    = 512,
>> +};
>> +
> rk3288 otg port total fifo size is only 0x3cc ?972?this value is in 
> terms of 32-bit words??
> read from  GHWCFG3 register bit[31:16], it's smaller than the total 
> fifo size you configured.
>
I understand what you concern, but fifo size is in terms of 1 byte 
above, please take a look on v4 
2/4(http://patchwork.ozlabs.org/patch/648237/).I remove >> 2 on the 
former code. Let  me know if you still disagree with it.
Thanks!
>> +int board_usb_init(int index, enum usb_init_type init)
>> +{
>> +    int node, phy_node;
>> +    const char *mode;
>> +    bool matched = false;
>> +    const void *blob = gd->fdt_blob;
>> +    u32 grf_phy_offset;
>> +
>> +    /* find the usb_otg node */
>> +    node = fdt_node_offset_by_compatible(blob, -1,
>> +                    "rockchip,rk3288-usb");
>> +
>> +    while (node > 0) {
>> +        mode = fdt_getprop(blob, node, "dr_mode", NULL);
>> +        if (mode && strcmp(mode, "otg") == 0) {
>> +            matched = true;
>> +            break;
>> +        }
>> +
>> +        node = fdt_node_offset_by_compatible(blob, node,
>> +                    "rockchip,rk3288-usb");
>> +    }
>> +    if (!matched) {
>> +        debug("Not found usb_otg device\n");
>> +        return -ENODEV;
>> +    }
>> +    rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
>> +
>> +    node = fdtdec_lookup_phandle(blob, node, "phys");
>> +    if (node <= 0) {
>> +        debug("Not found usb phy device\n");
>> +        return -ENODEV;
>> +    }
>> +
>> +    phy_node = fdt_parent_offset(blob, node);
>> +    if (phy_node <= 0) {
>> +        debug("Not found usb phy device\n");
>> +        return -ENODEV;
>> +    }
>> +
>> +    rk3288_otg_data.phy_of_node = phy_node;
>> +    grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
>> +
>> +    /* find the grf node */
>> +    node = fdt_node_offset_by_compatible(blob, -1,
>> +                    "rockchip,rk3288-grf");
>> +    if (node <= 0) {
>> +        debug("Not found grf device\n");
>> +        return -ENODEV;
>> +    }
>> +    rk3288_otg_data.regs_phy = grf_phy_offset +
>> +                fdtdec_get_addr(blob, node, "reg");
>> +
>> +    return dwc2_udc_probe(&rk3288_otg_data);
>> +}
>> +
>> +int board_usb_cleanup(int index, enum usb_init_type init)
>> +{
>> +    return 0;
>> +}
>> +#endif
>> +
>>   static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
>>                  char * const argv[])
>>   {
>> diff --git a/include/configs/rk3288_common.h 
>> b/include/configs/rk3288_common.h
>> index 8adc26f..2040cdd 100644
>> --- a/include/configs/rk3288_common.h
>> +++ b/include/configs/rk3288_common.h
>> @@ -79,6 +79,32 @@
>>   #define CONFIG_SPI
>>   #define CONFIG_SF_DEFAULT_SPEED 20000000
>>   +/* usb otg */
>> +#define CONFIG_USB_GADGET
>> +#define CONFIG_USB_GADGET_DUALSPEED
>> +#define CONFIG_USB_GADGET_DWC2_OTG
>> +#define CONFIG_ROCKCHIP_USB2_PHY
>> +#define CONFIG_USB_GADGET_VBUS_DRAW    0
>> +
>> +/* fastboot  */
>> +#define CONFIG_CMD_FASTBOOT
>> +#define CONFIG_USB_FUNCTION_FASTBOOT
>> +#define CONFIG_FASTBOOT_FLASH
>> +#define CONFIG_FASTBOOT_FLASH_MMC_DEV    1    /* eMMC */
>> +/* stroe safely fastboot buffer data to the middle of bank */
>> +#define CONFIG_FASTBOOT_BUF_ADDR    (CONFIG_SYS_SDRAM_BASE \
>> +                    + SDRAM_BANK_SIZE / 2)
>> +#define CONFIG_FASTBOOT_BUF_SIZE    0x08000000
>> +
>> +#define CONFIG_USB_GADGET_DOWNLOAD
>> +#define CONFIG_G_DNL_MANUFACTURER    "Rockchip"
>> +#define CONFIG_G_DNL_VENDOR_NUM        0x2207
>> +#define CONFIG_G_DNL_PRODUCT_NUM    0x320a
>> +
>> +/* Enable gpt partition table */
>> +#define CONFIG_CMD_GPT
>> +#define CONFIG_EFI_PARTITION
>> +
>>   #ifndef CONFIG_SPL_BUILD
>>   #include <config_distro_defaults.h>
>
>
>
>

[U-Boot] [PATCH v4.1 3/4] rockchip: rk3288: add fastboot support

[Ziyuan Xu]

From: Xu Ziyuan <xzy.xu@rock-chips.com>

Enable fastboot feature on rk3288.

This path doesn't support the fastboot flash function command entirely.
We will hit "cannot find partition" assertion without specified
partition environment. Define gpt partition layout in specified board
such as firefly-rk3288, then enjoy it!

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

---

Changes in v4.1:
- Revise tx_fifo_sz to 128

Changes in v4:
- Add fifo size for rk3288
- Get usb_phy's dt_node

Changes in v3:
- Achieve UOC_CON_OFFSET physical address from DT

Changes in v2:
- Achieve the regs_phy from DT
- Update comments a little

 arch/arm/dts/rk3288.dtsi        |  1 +
 arch/arm/mach-rockchip/board.c  | 72 +++++++++++++++++++++++++++++++++++++++++
 include/configs/rk3288_common.h | 26 +++++++++++++++
 3 files changed, 99 insertions(+)

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 3dab0fc..bcf051a 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -454,6 +454,7 @@
 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_OTG0>;
 		clock-names = "otg";
+		dr_mode = "otg";
 		phys = <&usbphy0>;
 		phy-names = "usb2-phy";
 		status = "disabled";
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 816540e..1458e80 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -52,6 +52,78 @@ void lowlevel_init(void)
 {
 }
 
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3288_otg_data = {
+	.rx_fifo_sz	= 512,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node, phy_node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+	u32 grf_phy_offset;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3288-usb");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node,
+					"rockchip,rk3288-usb");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+	rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	node = fdtdec_lookup_phandle(blob, node, "phys");
+	if (node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	phy_node = fdt_parent_offset(blob, node);
+	if (phy_node <= 0) {
+		debug("Not found usb phy device\n");
+		return -ENODEV;
+	}
+
+	rk3288_otg_data.phy_of_node = phy_node;
+	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
+
+	/* find the grf node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3288-grf");
+	if (node <= 0) {
+		debug("Not found grf device\n");
+		return -ENODEV;
+	}
+	rk3288_otg_data.regs_phy = grf_phy_offset +
+				fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&rk3288_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif
+
 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 8adc26f..2040cdd 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -79,6 +79,32 @@
 #define CONFIG_SPI
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_ROCKCHIP_USB2_PHY
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+
+/* fastboot  */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	1	/* eMMC */
+/* stroe safely fastboot buffer data to the middle of bank */
+#define CONFIG_FASTBOOT_BUF_ADDR	(CONFIG_SYS_SDRAM_BASE \
+					+ SDRAM_BANK_SIZE / 2)
+#define CONFIG_FASTBOOT_BUF_SIZE	0x08000000
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER	"Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM		0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM	0x320a
+
+/* Enable gpt partition table */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
 #ifndef CONFIG_SPL_BUILD
 #include <config_distro_defaults.h>
 
-- 
1.9.1

[U-Boot] [PATCH v4.1 3/4] rockchip: rk3288: add fastboot support

[Simon Glass]

On 14 July 2016 at 10:26, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>
> Enable fastboot feature on rk3288.
>
> This path doesn't support the fastboot flash function command entirely.

patch?

> We will hit "cannot find partition" assertion without specified
> partition environment. Define gpt partition layout in specified board
> such as firefly-rk3288, then enjoy it!
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> ---
>
> Changes in v4.1:
> - Revise tx_fifo_sz to 128
>
> Changes in v4:
> - Add fifo size for rk3288
> - Get usb_phy's dt_node
>
> Changes in v3:
> - Achieve UOC_CON_OFFSET physical address from DT
>
> Changes in v2:
> - Achieve the regs_phy from DT
> - Update comments a little
>
>  arch/arm/dts/rk3288.dtsi        |  1 +
>  arch/arm/mach-rockchip/board.c  | 72 +++++++++++++++++++++++++++++++++++++++++
>  include/configs/rk3288_common.h | 26 +++++++++++++++
>  3 files changed, 99 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

Could you please add some documentation to README.rockchip on how to use this?

[U-Boot] [PATCH v4.1 3/4] rockchip: rk3288: add fastboot support

[Ziyuan Xu]

Hi Simon,

On 2016?07?15? 11:20, Simon Glass wrote:
> On 14 July 2016 at 10:26, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>
>> Enable fastboot feature on rk3288.
>>
>> This path doesn't support the fastboot flash function command entirely.
> patch?
Yup, patch!!!
>
>> We will hit "cannot find partition" assertion without specified
>> partition environment. Define gpt partition layout in specified board
>> such as firefly-rk3288, then enjoy it!
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> ---
>>
>> Changes in v4.1:
>> - Revise tx_fifo_sz to 128
>>
>> Changes in v4:
>> - Add fifo size for rk3288
>> - Get usb_phy's dt_node
>>
>> Changes in v3:
>> - Achieve UOC_CON_OFFSET physical address from DT
>>
>> Changes in v2:
>> - Achieve the regs_phy from DT
>> - Update comments a little
>>
>>   arch/arm/dts/rk3288.dtsi        |  1 +
>>   arch/arm/mach-rockchip/board.c  | 72 +++++++++++++++++++++++++++++++++++++++++
>>   include/configs/rk3288_common.h | 26 +++++++++++++++
>>   3 files changed, 99 insertions(+)
> Acked-by: Simon Glass <sjg@chromium.org>
>
> Could you please add some documentation to README.rockchip on how to use this?
>
I'm glad to do it, how about sending a individual patch for introduction?
>

[U-Boot] [PATCH v4.1 3/4] rockchip: rk3288: add fastboot support

[Simon Glass]

Hi Ziyuan,

On 15 July 2016 at 08:05, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>
> Hi Simon,
>
> On 2016?07?15? 11:20, Simon Glass wrote:
>>
>> On 14 July 2016 at 10:26, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>>>
>>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>>
>>> Enable fastboot feature on rk3288.
>>>
>>> This path doesn't support the fastboot flash function command entirely.
>>
>> patch?
>
> Yup, patch!!!
>>
>>
>>> We will hit "cannot find partition" assertion without specified
>>> partition environment. Define gpt partition layout in specified board
>>> such as firefly-rk3288, then enjoy it!
>>>
>>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>>
>>> ---
>>>
>>> Changes in v4.1:
>>> - Revise tx_fifo_sz to 128
>>>
>>> Changes in v4:
>>> - Add fifo size for rk3288
>>> - Get usb_phy's dt_node
>>>
>>> Changes in v3:
>>> - Achieve UOC_CON_OFFSET physical address from DT
>>>
>>> Changes in v2:
>>> - Achieve the regs_phy from DT
>>> - Update comments a little
>>>
>>>   arch/arm/dts/rk3288.dtsi        |  1 +
>>>   arch/arm/mach-rockchip/board.c  | 72 +++++++++++++++++++++++++++++++++++++++++
>>>   include/configs/rk3288_common.h | 26 +++++++++++++++
>>>   3 files changed, 99 insertions(+)
>>
>> Acked-by: Simon Glass <sjg@chromium.org>
>>
>> Could you please add some documentation to README.rockchip on how to use this?
>>
> I'm glad to do it, how about sending a individual patch for introduction?

Yes that is good. Please base it on u-boot-rockchip/master.

Regards,
Simon

[U-Boot] [PATCH v4.1 3/4] rockchip: rk3288: add fastboot support

[Simon Glass]

On 14 July 2016 at 21:20, Simon Glass <sjg@chromium.org> wrote:
> On 14 July 2016 at 10:26, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>
>> Enable fastboot feature on rk3288.
>>
>> This path doesn't support the fastboot flash function command entirely.
>
> patch?
>
>> We will hit "cannot find partition" assertion without specified
>> partition environment. Define gpt partition layout in specified board
>> such as firefly-rk3288, then enjoy it!
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> ---
>>
>> Changes in v4.1:
>> - Revise tx_fifo_sz to 128
>>
>> Changes in v4:
>> - Add fifo size for rk3288
>> - Get usb_phy's dt_node
>>
>> Changes in v3:
>> - Achieve UOC_CON_OFFSET physical address from DT
>>
>> Changes in v2:
>> - Achieve the regs_phy from DT
>> - Update comments a little
>>
>>  arch/arm/dts/rk3288.dtsi        |  1 +
>>  arch/arm/mach-rockchip/board.c  | 72 +++++++++++++++++++++++++++++++++++++++++
>>  include/configs/rk3288_common.h | 26 +++++++++++++++
>>  3 files changed, 99 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> Could you please add some documentation to README.rockchip on how to use this?

Applied to u-boot-rockchip, thanks!

[U-Boot] [PATCH v4 4/4] usb: dwc2 : invalidate dcache before starting DMA

[Ziyuan Xu]

From: Xu Ziyuan <xzy.xu@rock-chips.com>

Invalidate dcache before starting the DMA to ensure coherency. In case
there are any dirty lines from the DMA buffer in the cache, subsequent
cache-line replacements may corrupt the buffer in memory while the DMA
is still going on. Cache-line replacement can happen if the CPU tries to
bring some other memory locations into the cache while the DMA is going
on.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

---

Changes in v4: None
Changes in v3:
- New commit since v3 to fix the coherence issue between memory and
cache

Changes in v2: None

 drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 12f5c85..0d6d2fb 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -110,6 +110,9 @@ static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
 
 	ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 
+	invalidate_dcache_range((unsigned long) ep->dma_buf,
+				(unsigned long) ep->dma_buf + ep->len);
+
 	writel((unsigned int) ep->dma_buf, &reg->out_endp[ep_num].doepdma);
 	writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 	       &reg->out_endp[ep_num].doeptsiz);
-- 
1.9.1

[U-Boot] [PATCH v4 4/4] usb: dwc2 : invalidate dcache before starting DMA

[Simon Glass]

On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>
> Invalidate dcache before starting the DMA to ensure coherency. In case
> there are any dirty lines from the DMA buffer in the cache, subsequent
> cache-line replacements may corrupt the buffer in memory while the DMA
> is still going on. Cache-line replacement can happen if the CPU tries to
> bring some other memory locations into the cache while the DMA is going
> on.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> ---
>
> Changes in v4: None
> Changes in v3:
> - New commit since v3 to fix the coherence issue between memory and
> cache
>
> Changes in v2: None
>
>  drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 3 +++
>  1 file changed, 3 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v4 4/4] usb: dwc2 : invalidate dcache before starting DMA

[Simon Glass]

On 14 July 2016 at 21:20, Simon Glass <sjg@chromium.org> wrote:
> On 14 July 2016 at 00:52, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
>> From: Xu Ziyuan <xzy.xu@rock-chips.com>
>>
>> Invalidate dcache before starting the DMA to ensure coherency. In case
>> there are any dirty lines from the DMA buffer in the cache, subsequent
>> cache-line replacements may corrupt the buffer in memory while the DMA
>> is still going on. Cache-line replacement can happen if the CPU tries to
>> bring some other memory locations into the cache while the DMA is going
>> on.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> ---
>>
>> Changes in v4: None
>> Changes in v3:
>> - New commit since v3 to fix the coherence issue between memory and
>> cache
>>
>> Changes in v2: None
>>
>>  drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 3 +++
>>  1 file changed, 3 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip, thanks!