From: Thomas Gleixner <tglx@linutronix.de> To: "Raj\, Ashok" <ashok.raj@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com>, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, H Peter Anvin <hpa@zytor.com>, David Woodhouse <dwmw2@infradead.org>, Lu Baolu <baolu.lu@linux.intel.com>, Dave Hansen <dave.hansen@intel.com>, Tony Luck <tony.luck@intel.com>, Jacob Jun Pan <jacob.jun.pan@intel.com>, Dave Jiang <dave.jiang@intel.com>, Sohil Mehta <sohil.mehta@intel.com>, Ravi V Shankar <ravi.v.shankar@intel.com>, linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>, iommu@lists.linux-foundation.org, Ashok Raj <ashok.raj@intel.com> Subject: Re: [PATCH 6/7] x86/traps: Fix up invalid PASID Date: Tue, 28 Apr 2020 02:54:59 +0200 [thread overview] Message-ID: <874kt4pgyk.fsf@nanos.tec.linutronix.de> (raw) In-Reply-To: <20200427224646.GA103955@otc-nc-03> Ashok, "Raj, Ashok" <ashok.raj@intel.com> writes: > On Sun, Apr 26, 2020 at 05:25:06PM +0200, Thomas Gleixner wrote: >> Just for the record I also suggested to have a proper errorcode in the >> #GP for ENQCMD and I surely did not suggest to avoid decoding the user >> instructions. > > We certainly discussed the possiblity of adding an error code to > identiy #GP due to ENQCMD with our HW architects. > > There are only a few cases that have an error code, like move to segment > with an invalid value for instance. There were a few but i don't > recall that entire list. > > Since the error code is 0 in most places, there isn't plumbing in hw to return > this value in all cases. It appeared that due to some uarch reasons it > wasn't as simple as it appears to /me sw kinds :-) Sigh. > So after some internal discussion we decided to take the current > approach. Its possible that if the #GP was due to some other reason > we might #GP another time. Since this wasn't perf or speed path we took > this lazy approach. I know that the HW people's mantra is that everything can be fixed in software and therefore slapping new features into the CPUs can be done without thinking about the consequeses. But we all know from painful experience that this is fundamentally wrong unless there is a really compelling reason. For new features there is absolutely no reason at all. Can HW people pretty please understand that hardware and software have to be co-designed and not dictated by 'some uarch reasons'. This is nothing fundamentally new. This problem existed 30+ years ago, is well documented and has been ignored forever. I'm tired of that, really. But as this seems to be unsolvable for the problem at hand can you please document the inability, unwillingness or whatever in the changelog? The question why this brand new_ ENQCMD + invalid PASID induced #GP does not generate an useful error code and needs heuristics to be dealt with is pretty obvious. Thanks, tglx
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de> To: "Raj\, Ashok" <ashok.raj@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com>, Tony Luck <tony.luck@intel.com>, Dave Jiang <dave.jiang@intel.com>, Ashok Raj <ashok.raj@intel.com>, Ravi V Shankar <ravi.v.shankar@intel.com>, x86 <x86@kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, Dave Hansen <dave.hansen@intel.com>, iommu@lists.linux-foundation.org, Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>, Jacob Jun Pan <jacob.jun.pan@intel.com>, H Peter Anvin <hpa@zytor.com>, David Woodhouse <dwmw2@infradead.org> Subject: Re: [PATCH 6/7] x86/traps: Fix up invalid PASID Date: Tue, 28 Apr 2020 02:54:59 +0200 [thread overview] Message-ID: <874kt4pgyk.fsf@nanos.tec.linutronix.de> (raw) In-Reply-To: <20200427224646.GA103955@otc-nc-03> Ashok, "Raj, Ashok" <ashok.raj@intel.com> writes: > On Sun, Apr 26, 2020 at 05:25:06PM +0200, Thomas Gleixner wrote: >> Just for the record I also suggested to have a proper errorcode in the >> #GP for ENQCMD and I surely did not suggest to avoid decoding the user >> instructions. > > We certainly discussed the possiblity of adding an error code to > identiy #GP due to ENQCMD with our HW architects. > > There are only a few cases that have an error code, like move to segment > with an invalid value for instance. There were a few but i don't > recall that entire list. > > Since the error code is 0 in most places, there isn't plumbing in hw to return > this value in all cases. It appeared that due to some uarch reasons it > wasn't as simple as it appears to /me sw kinds :-) Sigh. > So after some internal discussion we decided to take the current > approach. Its possible that if the #GP was due to some other reason > we might #GP another time. Since this wasn't perf or speed path we took > this lazy approach. I know that the HW people's mantra is that everything can be fixed in software and therefore slapping new features into the CPUs can be done without thinking about the consequeses. But we all know from painful experience that this is fundamentally wrong unless there is a really compelling reason. For new features there is absolutely no reason at all. Can HW people pretty please understand that hardware and software have to be co-designed and not dictated by 'some uarch reasons'. This is nothing fundamentally new. This problem existed 30+ years ago, is well documented and has been ignored forever. I'm tired of that, really. But as this seems to be unsolvable for the problem at hand can you please document the inability, unwillingness or whatever in the changelog? The question why this brand new_ ENQCMD + invalid PASID induced #GP does not generate an useful error code and needs heuristics to be dealt with is pretty obvious. Thanks, tglx _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-04-28 0:55 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-30 19:33 [PATCH 0/7] x86: tag application address space for devices Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-03-30 19:33 ` [PATCH 1/7] docs: x86: Add a documentation for ENQCMD Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-04-26 11:02 ` Thomas Gleixner 2020-04-26 11:02 ` Thomas Gleixner 2020-04-27 20:13 ` Fenghua Yu 2020-04-27 20:13 ` Fenghua Yu 2020-03-30 19:33 ` [PATCH 2/7] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-04-26 11:06 ` Thomas Gleixner 2020-04-26 11:06 ` Thomas Gleixner 2020-04-27 20:17 ` Fenghua Yu 2020-04-27 20:17 ` Fenghua Yu 2020-03-30 19:33 ` [PATCH 3/7] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-04-26 11:17 ` Thomas Gleixner 2020-04-26 11:17 ` Thomas Gleixner 2020-04-27 20:33 ` Fenghua Yu 2020-04-27 20:33 ` Fenghua Yu 2020-03-30 19:33 ` [PATCH 4/7] x86/msr-index: Define IA32_PASID MSR Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-04-26 11:22 ` Thomas Gleixner 2020-04-26 11:22 ` Thomas Gleixner 2020-04-27 20:50 ` Fenghua Yu 2020-04-27 20:50 ` Fenghua Yu 2020-03-30 19:33 ` [PATCH 5/7] x86/mmu: Allocate/free PASID Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-04-26 14:55 ` Thomas Gleixner 2020-04-26 14:55 ` Thomas Gleixner 2020-04-27 22:18 ` Fenghua Yu 2020-04-27 22:18 ` Fenghua Yu 2020-04-27 23:44 ` Thomas Gleixner 2020-04-27 23:44 ` Thomas Gleixner 2020-04-28 18:21 ` Jacob Pan (Jun) 2020-04-28 18:21 ` Jacob Pan (Jun) 2020-04-28 18:54 ` Thomas Gleixner 2020-04-28 18:54 ` Thomas Gleixner 2020-04-28 19:07 ` Luck, Tony 2020-04-28 19:07 ` Luck, Tony 2020-04-28 20:42 ` Jacob Pan (Jun) 2020-04-28 20:42 ` Jacob Pan (Jun) 2020-04-28 20:59 ` Luck, Tony 2020-04-28 20:59 ` Luck, Tony 2020-04-28 22:13 ` Jacob Pan (Jun) 2020-04-28 22:13 ` Jacob Pan (Jun) 2020-04-28 22:32 ` Luck, Tony 2020-04-28 22:32 ` Luck, Tony 2020-04-28 20:40 ` Jacob Pan (Jun) 2020-04-28 20:40 ` Jacob Pan (Jun) 2020-04-28 20:57 ` Fenghua Yu 2020-04-28 20:57 ` Fenghua Yu 2020-03-30 19:33 ` [PATCH 6/7] x86/traps: Fix up invalid PASID Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-04-26 15:25 ` Thomas Gleixner 2020-04-26 15:25 ` Thomas Gleixner 2020-04-27 20:11 ` Fenghua Yu 2020-04-27 20:11 ` Fenghua Yu 2020-04-28 0:13 ` Thomas Gleixner 2020-04-28 0:13 ` Thomas Gleixner 2020-04-27 22:46 ` Raj, Ashok 2020-04-27 22:46 ` Raj, Ashok 2020-04-27 23:08 ` Luck, Tony 2020-04-27 23:08 ` Luck, Tony 2020-04-28 0:20 ` Thomas Gleixner 2020-04-28 0:20 ` Thomas Gleixner 2020-04-28 0:54 ` Thomas Gleixner [this message] 2020-04-28 0:54 ` Thomas Gleixner 2020-04-28 1:08 ` Raj, Ashok 2020-04-28 1:08 ` Raj, Ashok 2020-03-30 19:33 ` [PATCH 7/7] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu 2020-03-30 19:33 ` Fenghua Yu 2020-04-22 20:41 ` [PATCH 0/7] x86: tag application address space for devices Fenghua Yu 2020-04-22 20:41 ` Fenghua Yu
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