[Qemu-devel] [RFC 0/6] POWER9 TCG enablements - part1

[Qemu-devel] [RFC 0/6] POWER9 TCG enablements - part1

[Nikunj A Dadhania]

This set starts adding new instructions for POWER9 described in ISA3.0.

First two patches adds the required POWER9 cpu model and ISA defines.

Next four patches adds following instructions:

addpcis   : Add PC Immediate Shifted
cmprb     : Compare Ranged Byte
moduw     : Modulo Unsigned Word
modsw     : Modulo Signed Word
modud     : Modulo Unsigned Dword
modsd     : Modulo Signed Dword

Aneesh Kumar K.V (1):
  target-ppc: Introduce Power9 family

Nikunj A Dadhania (5):
  target-ppc: Introduce POWER ISA 3.0 flag
  target-ppc: adding addpcis instruction
  target-ppc: add cmprb instruction
  target-ppc: add modulo word operations
  target-ppc: add modulo dword operations

 target-ppc/cpu-models.c     |   5 ++
 target-ppc/cpu-models.h     |   2 +
 target-ppc/cpu-qom.h        |   7 ++
 target-ppc/cpu.h            |   5 +-
 target-ppc/mmu_helper.c     |   3 +-
 target-ppc/translate.c      | 162 ++++++++++++++++++++++++++++++++++++++++++++
 target-ppc/translate_init.c |  85 ++++++++++++++++++++++-
 7 files changed, 266 insertions(+), 3 deletions(-)

-- 
2.7.4

[Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family

[Nikunj A Dadhania]

From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ rebased and added POWER9 alias ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/cpu-models.c     |  5 +++
 target-ppc/cpu-models.h     |  2 ++
 target-ppc/cpu-qom.h        |  7 ++++
 target-ppc/mmu_helper.c     |  3 +-
 target-ppc/translate_init.c | 85 ++++++++++++++++++++++++++++++++++++++++++++-
 5 files changed, 100 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 5209e63..901cf40 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1147,6 +1147,10 @@
                 "POWER8NVL v1.0")
     POWERPC_DEF("970_v2.2",      CPU_POWERPC_970_v22,                970,
                 "PowerPC 970 v2.2")
+
+    POWERPC_DEF("POWER9_v1.0",   CPU_POWERPC_POWER9_BASE,            POWER9,
+                "POWER9 v1.0")
+
     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970,
                 "PowerPC 970FX v1.0 (G5)")
     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970,
@@ -1395,6 +1399,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
     { "POWER8E", "POWER8E_v2.1" },
     { "POWER8", "POWER8_v2.0" },
     { "POWER8NVL", "POWER8NVL_v1.0" },
+    { "POWER9", "POWER9_v1.0" },
     { "970", "970_v2.2" },
     { "970fx", "970fx_v3.1" },
     { "970mp", "970mp_v1.1" },
diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
index f21a44c..beeaaba 100644
--- a/target-ppc/cpu-models.h
+++ b/target-ppc/cpu-models.h
@@ -562,6 +562,8 @@ enum {
     CPU_POWERPC_POWER8_v20         = 0x004D0200,
     CPU_POWERPC_POWER8NVL_BASE     = 0x004C0000,
     CPU_POWERPC_POWER8NVL_v10      = 0x004C0100,
+    CPU_POWERPC_POWER9_BASE        = 0x004E0000,
+    CPU_POWERPC_POWER9_MAM         = 0x004E0100,
     CPU_POWERPC_970_v22            = 0x00390202,
     CPU_POWERPC_970FX_v10          = 0x00391100,
     CPU_POWERPC_970FX_v20          = 0x003C0200,
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 2864105..df2fb65 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -86,6 +86,13 @@ enum powerpc_mmu_t {
     POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
                              | POWERPC_MMU_64K
                              | POWERPC_MMU_AMR | 0x00000004,
+    /* for now , We can add radix later if needed */
+    /* POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
+     * | POWERPC_MMU_AMR | 0x00000005,
+     */
+
+    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x00000005,
+
     /* Architecture 2.07 "degraded" (no 1T segments)           */
     POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
                              | 0x00000004,
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 485d5b8..6219c4a 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1935,13 +1935,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
     case POWERPC_MMU_2_06a:
     case POWERPC_MMU_2_07:
     case POWERPC_MMU_2_07a:
+    case POWERPC_MMU_3_00:
 #endif /* defined(TARGET_PPC64) */
         env->tlb_need_flush = 0;
         tlb_flush(CPU(cpu), 1);
         break;
     default:
         /* XXX: TODO */
-        cpu_abort(CPU(cpu), "Unknown MMU model\n");
+        cpu_abort(CPU(cpu), "Unknown MMU model %d\n", env->mmu_model);
         break;
     }
 }
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8f257fb..51bab23 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7459,7 +7459,8 @@ enum BOOK3S_CPU_TYPE {
     BOOK3S_CPU_POWER5PLUS,
     BOOK3S_CPU_POWER6,
     BOOK3S_CPU_POWER7,
-    BOOK3S_CPU_POWER8
+    BOOK3S_CPU_POWER8,
+    BOOK3S_CPU_POWER9
 };
 
 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
@@ -8241,6 +8242,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
         break;
     case BOOK3S_CPU_POWER7:
     case BOOK3S_CPU_POWER8:
+    case BOOK3S_CPU_POWER9:
         gen_spr_book3s_ids(env);
         gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
         gen_spr_book3s_purr(env);
@@ -8293,6 +8295,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
         break;
     case BOOK3S_CPU_POWER7:
     case BOOK3S_CPU_POWER8:
+    case BOOK3S_CPU_POWER9:
     default:
         env->slb_nr = 32;
         break;
@@ -8310,6 +8313,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
         ppcPOWER7_irq_init(ppc_env_get_cpu(env));
         break;
     case BOOK3S_CPU_POWER8:
+    case BOOK3S_CPU_POWER9:
         init_excp_POWER8(env);
         ppcPOWER7_irq_init(ppc_env_get_cpu(env));
         break;
@@ -8772,6 +8776,85 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
 }
+static void init_proc_POWER9(CPUPPCState *env)
+{
+    init_proc_book3s_64(env, BOOK3S_CPU_POWER9);
+}
+
+static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
+{
+    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
+        return true;
+    }
+    return false;
+}
+
+POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+    dc->fw_name = "PowerPC,POWER9";
+    dc->desc = "POWER9";
+    dc->props = powerpc_servercpu_properties;
+    pcc->pvr_match = ppc_pvr_match_power9;
+    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
+    pcc->init_proc = init_proc_POWER9;
+    pcc->check_pow = check_pow_nocheck;
+    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
+                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+                       PPC_FLOAT_FRSQRTES |
+                       PPC_FLOAT_STFIWX |
+                       PPC_FLOAT_EXT |
+                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
+                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+                       PPC_64B | PPC_64BX | PPC_ALTIVEC |
+                       PPC_SEGMENT_64B | PPC_SLBI |
+                       PPC_POPCNTB | PPC_POPCNTWD |
+                       PPC_CILDST;
+    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
+                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+                        PPC2_TM | PPC2_PM_ISA206;
+    pcc->msr_mask = (1ull << MSR_SF) |
+                    (1ull << MSR_TM) |
+                    (1ull << MSR_VR) |
+                    (1ull << MSR_VSX) |
+                    (1ull << MSR_EE) |
+                    (1ull << MSR_PR) |
+                    (1ull << MSR_FP) |
+                    (1ull << MSR_ME) |
+                    (1ull << MSR_FE0) |
+                    (1ull << MSR_SE) |
+                    (1ull << MSR_DE) |
+                    (1ull << MSR_FE1) |
+                    (1ull << MSR_IR) |
+                    (1ull << MSR_DR) |
+                    (1ull << MSR_PMM) |
+                    (1ull << MSR_RI) |
+                    (1ull << MSR_LE);
+    pcc->mmu_model = POWERPC_MMU_3_00;
+#if defined(CONFIG_SOFTMMU)
+    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+    /* segment page size remain the same */
+    pcc->sps = &POWER7_POWER8_sps;
+#endif
+    pcc->excp_model = POWERPC_EXCP_POWER8;
+    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
+    pcc->bfd_mach = bfd_mach_ppc64;
+    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
+                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
+    pcc->l1_dcache_size = 0x8000;
+    pcc->l1_icache_size = 0x8000;
+    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+}
 
 #if !defined(CONFIG_USER_ONLY)
 
-- 
2.7.4

[Qemu-devel] [RFC 2/6] target-ppc: Introduce POWER ISA 3.0 flag

[Nikunj A Dadhania]

This flag will be used for POWER9 instructions.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/cpu.h            | 5 ++++-
 target-ppc/translate_init.c | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 2666a3f..f48ff0f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2093,6 +2093,8 @@ enum {
     PPC2_TM            = 0x0000000000020000ULL,
     /* Server PM instructgions (ISA 2.06, Book III)                          */
     PPC2_PM_ISA206     = 0x0000000000040000ULL,
+    /* POWER ISA 3.0                                                         */
+    PPC2_ISA300        = 0x0000000000080000ULL,
 
 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2100,7 +2102,8 @@ enum {
                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
-                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206)
+                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
+                        PPC2_ISA300)
 };
 
 /*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 51bab23..9852524 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8820,7 +8820,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
                         PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
                         PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
-                        PPC2_TM | PPC2_PM_ISA206;
+                        PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300;
     pcc->msr_mask = (1ull << MSR_SF) |
                     (1ull << MSR_TM) |
                     (1ull << MSR_VR) |
-- 
2.7.4

[Qemu-devel] [RFC 3/6] target-ppc: adding addpcis instruction

[Nikunj A Dadhania]

ISA 3.0 instruction for adding immediate value with next instruction
address and return the result in the target register.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 92030b6..93c7c66 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -432,6 +432,20 @@ static inline uint32_t name(uint32_t opcode)                                  \
     return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |             \
             ((opcode >> (shift2)) & ((1 << (nb2)) - 1));                      \
 }
+
+#define EXTRACT_HELPER_DXFORM(name,                                           \
+                              d0_bits, shift_op_d0, shift_d0,                 \
+                              d1_bits, shift_op_d1, shift_d1,                 \
+                              d2_bits, shift_op_d2, shift_d2)                 \
+static inline int16_t name(uint32_t opcode)                                   \
+{                                                                             \
+    return                                                                    \
+        (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
+        (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
+        (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2));  \
+}
+
+
 /* Opcode part 1 */
 EXTRACT_HELPER(opc1, 26, 6);
 /* Opcode part 2 */
@@ -501,6 +515,9 @@ EXTRACT_HELPER(FPL, 25, 1);
 EXTRACT_HELPER(FPFLM, 17, 8);
 EXTRACT_HELPER(FPW, 16, 1);
 
+/* addpcis */
+EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+
 /***                            Jump target decoding                       ***/
 /* Immediate address */
 static inline target_ulong LI(uint32_t opcode)
@@ -984,6 +1001,15 @@ static void gen_addis(DisasContext *ctx)
     }
 }
 
+/* addpcis */
+static void gen_addpcis(DisasContext *ctx)
+{
+    target_long d = DX(ctx->opcode);
+
+    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip);
+    tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], d);
+}
+
 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
                                      TCGv arg2, int sign, int compute_ov)
 {
@@ -9877,6 +9903,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
+GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
-- 
2.7.4

[Qemu-devel] [RFC 4/6] target-ppc: add cmprb instruction

[Nikunj A Dadhania]

ISA 3.0 Compare Ranged Byte instruction useful for
isupper/islower/isaplha kind of operation.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 93c7c66..8de217f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -817,6 +817,45 @@ static void gen_cmpli(DisasContext *ctx)
     }
 }
 
+/* cmprb - range comparison: isupper, isaplha, islower*/
+static void gen_cmprb(DisasContext *ctx)
+{
+    TCGLabel *lab1 = gen_new_label();
+    TCGLabel *lab2 = gen_new_label();
+    TCGv src1 = tcg_temp_local_new();
+    TCGv src2 = tcg_temp_local_new();
+    TCGv src2lo = tcg_temp_local_new();
+    TCGv src2hi = tcg_temp_local_new();
+
+    tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
+    tcg_gen_andi_tl(src2, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF);
+
+    tcg_gen_andi_tl(src2lo, src2, 0xFF);
+    tcg_gen_shri_tl(src2hi, src2, 8);
+    tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
+
+    tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab1);
+    tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab1);
+    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
+    tcg_gen_br(lab2);
+    gen_set_label(lab1);
+
+    if (ctx->opcode & 0x00200000) {
+        tcg_gen_shri_tl(src2hi, src2, 24);
+        tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
+        tcg_gen_shri_tl(src2lo, src2, 16);
+        tcg_gen_andi_tl(src2lo, src2lo, 0xFF);
+        tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab2);
+        tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab2);
+        tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
+    }
+    gen_set_label(lab2);
+    tcg_temp_free(src1);
+    tcg_temp_free(src2);
+    tcg_temp_free(src2lo);
+    tcg_temp_free(src2hi);
+}
+
 /* isel (PowerPC 2.03 specification) */
 static void gen_isel(DisasContext *ctx)
 {
@@ -9898,6 +9937,7 @@ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-- 
2.7.4

[Qemu-devel] [RFC 5/6] target-ppc: add modulo word operations

[Nikunj A Dadhania]

Adding following instructions:

moduw: Modulo Unsigned Word
modsw: Modulo Signed Word

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8de217f..c505684 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1178,6 +1178,54 @@ GEN_DIVE(divde, divde, 0);
 GEN_DIVE(divdeo, divde, 1);
 #endif
 
+static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
+                                     TCGv arg2, int sign)
+{
+    TCGLabel *l1 = gen_new_label();
+    TCGLabel *l2 = gen_new_label();
+    TCGv_i32 t0 = tcg_temp_local_new_i32();
+    TCGv_i32 t1 = tcg_temp_local_new_i32();
+    TCGv_i32 t2 = tcg_temp_local_new_i32();
+
+    tcg_gen_trunc_tl_i32(t0, arg1);
+    tcg_gen_trunc_tl_i32(t1, arg2);
+    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
+    if (sign) {
+        TCGLabel *l3 = gen_new_label();
+        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
+        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
+        gen_set_label(l3);
+        tcg_gen_div_i32(t2, t0, t1);
+    } else {
+        tcg_gen_divu_i32(t2, t0, t1);
+    }
+    tcg_gen_mul_i32(t2, t2, t1);
+    tcg_gen_sub_i32(t2, t0, t2);
+    tcg_gen_br(l2);
+    gen_set_label(l1);
+    if (sign) {
+        tcg_gen_sari_i32(t2, t0, 31);
+    } else {
+        tcg_gen_movi_i32(t2, 0);
+    }
+    gen_set_label(l2);
+    tcg_gen_extu_i32_tl(ret, t2);
+    tcg_temp_free_i32(t0);
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
+#define GEN_INT_ARITH_MODW(name, opc3, sign)                                \
+static void glue(gen_, name)(DisasContext *ctx)                             \
+{                                                                           \
+    gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)],                        \
+                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
+                      sign);                                                \
+}
+
+GEN_INT_ARITH_MODW(modsw, 0x18, 1);
+GEN_INT_ARITH_MODW(moduw, 0x08, 0);
+
 /* mulhw  mulhw. */
 static void gen_mulhw(DisasContext *ctx)
 {
@@ -10244,6 +10292,8 @@ GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
+GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
 
 #if defined(TARGET_PPC64)
 #undef GEN_INT_ARITH_DIVD
-- 
2.7.4

[Qemu-devel] [RFC 6/6] target-ppc: add modulo dword operations

[Nikunj A Dadhania]

Adding following instructions for ISA3.0 support

modud: Modulo Unsigned Dword
modsd: Modulo Signed Dword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c505684..efc740a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1226,6 +1226,49 @@ static void glue(gen_, name)(DisasContext *ctx)                             \
 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
 
+#if defined(TARGET_PPC64)
+static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
+                                     TCGv arg2, int sign)
+{
+    TCGLabel *l1 = gen_new_label();
+    TCGLabel *l2 = gen_new_label();
+    TCGv_i64 t0 = tcg_temp_local_new_i64();
+
+    tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
+    if (sign) {
+        TCGLabel *l3 = gen_new_label();
+        tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
+        tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
+        gen_set_label(l3);
+        tcg_gen_div_i64(t0, arg1, arg2);
+    } else {
+        tcg_gen_divu_i64(t0, arg1, arg2);
+    }
+    tcg_gen_mul_i64(t0, t0, arg2);
+    tcg_gen_sub_i64(ret, arg1, t0);
+    tcg_gen_br(l2);
+    gen_set_label(l1);
+    if (sign) {
+        tcg_gen_sari_i64(ret, arg1, 63);
+    } else {
+        tcg_gen_movi_i64(ret, 0);
+    }
+    gen_set_label(l2);
+    tcg_temp_free_i64(t0);
+}
+
+#define GEN_INT_ARITH_MODD(name, opc3, sign)                            \
+static void glue(gen_, name)(DisasContext *ctx)                           \
+{                                                                         \
+  gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)],                        \
+                    cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
+                    sign);                                                \
+}
+
+GEN_INT_ARITH_MODD(modsd, 0x18, 1);
+GEN_INT_ARITH_MODD(modud, 0x08, 0);
+#endif
+
 /* mulhw  mulhw. */
 static void gen_mulhw(DisasContext *ctx)
 {
@@ -10308,6 +10351,8 @@ GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
+GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
 
 #undef GEN_INT_ARITH_MUL_HELPER
 #define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
-- 
2.7.4

Re: [Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family

[Bharata B Rao]

On Tue, Jul 12, 2016 at 11:33 PM, Nikunj A Dadhania
<nikunj@linux.vnet.ibm.com> wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> [ rebased and added POWER9 alias ]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target-ppc/cpu-models.c     |  5 +++
>  target-ppc/cpu-models.h     |  2 ++
>  target-ppc/cpu-qom.h        |  7 ++++
>  target-ppc/mmu_helper.c     |  3 +-
>  target-ppc/translate_init.c | 85 ++++++++++++++++++++++++++++++++++++++++++++-
>  5 files changed, 100 insertions(+), 2 deletions(-)
>
> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> index 5209e63..901cf40 100644
> --- a/target-ppc/cpu-models.c
> +++ b/target-ppc/cpu-models.c
> @@ -1147,6 +1147,10 @@
>                  "POWER8NVL v1.0")
>      POWERPC_DEF("970_v2.2",      CPU_POWERPC_970_v22,                970,
>                  "PowerPC 970 v2.2")
> +
> +    POWERPC_DEF("POWER9_v1.0",   CPU_POWERPC_POWER9_BASE,            POWER9,
> +                "POWER9 v1.0")
> +

I realize it is still early days, but eventually remember to add a
POWER9 core definition in spapr_cpu_core.c

Regards,
Bharata.

Re: [Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family

[Nikunj A Dadhania]

Bharata B Rao <bharata.rao@gmail.com> writes:

> On Tue, Jul 12, 2016 at 11:33 PM, Nikunj A Dadhania
> <nikunj@linux.vnet.ibm.com> wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> [ rebased and added POWER9 alias ]
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>>  target-ppc/cpu-models.c     |  5 +++
>>  target-ppc/cpu-models.h     |  2 ++
>>  target-ppc/cpu-qom.h        |  7 ++++
>>  target-ppc/mmu_helper.c     |  3 +-
>>  target-ppc/translate_init.c | 85 ++++++++++++++++++++++++++++++++++++++++++++-
>>  5 files changed, 100 insertions(+), 2 deletions(-)
>>
>> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
>> index 5209e63..901cf40 100644
>> --- a/target-ppc/cpu-models.c
>> +++ b/target-ppc/cpu-models.c
>> @@ -1147,6 +1147,10 @@
>>                  "POWER8NVL v1.0")
>>      POWERPC_DEF("970_v2.2",      CPU_POWERPC_970_v22,                970,
>>                  "PowerPC 970 v2.2")
>> +
>> +    POWERPC_DEF("POWER9_v1.0",   CPU_POWERPC_POWER9_BASE,            POWER9,
>> +                "POWER9 v1.0")
>> +
>
> I realize it is still early days, but eventually remember to add a
> POWER9 core definition in spapr_cpu_core.c

Yes, sure will add them. Haven't still reached there yet, mostly testing
with qemu-ppc64le :-)

Regards,
Nikunj

Re: [Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family

[David Gibson]

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On Tue, Jul 12, 2016 at 11:33:17PM +0530, Nikunj A Dadhania wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> [ rebased and added POWER9 alias ]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target-ppc/cpu-models.c     |  5 +++
>  target-ppc/cpu-models.h     |  2 ++
>  target-ppc/cpu-qom.h        |  7 ++++
>  target-ppc/mmu_helper.c     |  3 +-
>  target-ppc/translate_init.c | 85 ++++++++++++++++++++++++++++++++++++++++++++-
>  5 files changed, 100 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> index 5209e63..901cf40 100644
> --- a/target-ppc/cpu-models.c
> +++ b/target-ppc/cpu-models.c
> @@ -1147,6 +1147,10 @@
>                  "POWER8NVL v1.0")
>      POWERPC_DEF("970_v2.2",      CPU_POWERPC_970_v22,                970,
>                  "PowerPC 970 v2.2")
> +
> +    POWERPC_DEF("POWER9_v1.0",   CPU_POWERPC_POWER9_BASE,            POWER9,
> +                "POWER9 v1.0")
> +
>      POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970,
>                  "PowerPC 970FX v1.0 (G5)")
>      POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970,
> @@ -1395,6 +1399,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
>      { "POWER8E", "POWER8E_v2.1" },
>      { "POWER8", "POWER8_v2.0" },
>      { "POWER8NVL", "POWER8NVL_v1.0" },
> +    { "POWER9", "POWER9_v1.0" },
>      { "970", "970_v2.2" },
>      { "970fx", "970fx_v3.1" },
>      { "970mp", "970mp_v1.1" },
> diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
> index f21a44c..beeaaba 100644
> --- a/target-ppc/cpu-models.h
> +++ b/target-ppc/cpu-models.h
> @@ -562,6 +562,8 @@ enum {
>      CPU_POWERPC_POWER8_v20         = 0x004D0200,
>      CPU_POWERPC_POWER8NVL_BASE     = 0x004C0000,
>      CPU_POWERPC_POWER8NVL_v10      = 0x004C0100,
> +    CPU_POWERPC_POWER9_BASE        = 0x004E0000,
> +    CPU_POWERPC_POWER9_MAM         = 0x004E0100,
>      CPU_POWERPC_970_v22            = 0x00390202,
>      CPU_POWERPC_970FX_v10          = 0x00391100,
>      CPU_POWERPC_970FX_v20          = 0x003C0200,
> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
> index 2864105..df2fb65 100644
> --- a/target-ppc/cpu-qom.h
> +++ b/target-ppc/cpu-qom.h
> @@ -86,6 +86,13 @@ enum powerpc_mmu_t {
>      POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
>                               | POWERPC_MMU_64K
>                               | POWERPC_MMU_AMR | 0x00000004,
> +    /* for now , We can add radix later if needed */

I'm guessing this means you're only thinking about the guest-side
presentation of the P9 MMU at this point?  IIUC the host side
presentation is so different that sharing any constants with pre-P9
MMUs probably doesn't make sense.

I'm not immediately sure how we should make this distinction in the
target-ppc code, since these values are supposed to belong to the CPU
regardless of operating mode.


> +    /* POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> +     * | POWERPC_MMU_AMR | 0x00000005,
> +     */
> +
> +    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x00000005,
> +
>      /* Architecture 2.07 "degraded" (no 1T segments)           */
>      POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
>                               | 0x00000004,
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index 485d5b8..6219c4a 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -1935,13 +1935,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
>      case POWERPC_MMU_2_06a:
>      case POWERPC_MMU_2_07:
>      case POWERPC_MMU_2_07a:
> +    case POWERPC_MMU_3_00:
>  #endif /* defined(TARGET_PPC64) */
>          env->tlb_need_flush = 0;
>          tlb_flush(CPU(cpu), 1);
>          break;
>      default:
>          /* XXX: TODO */
> -        cpu_abort(CPU(cpu), "Unknown MMU model\n");
> +        cpu_abort(CPU(cpu), "Unknown MMU model %d\n", env->mmu_model);
>          break;
>      }
>  }
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 8f257fb..51bab23 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7459,7 +7459,8 @@ enum BOOK3S_CPU_TYPE {
>      BOOK3S_CPU_POWER5PLUS,
>      BOOK3S_CPU_POWER6,
>      BOOK3S_CPU_POWER7,
> -    BOOK3S_CPU_POWER8
> +    BOOK3S_CPU_POWER8,
> +    BOOK3S_CPU_POWER9
>  };
>  
>  static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> @@ -8241,6 +8242,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>          break;
>      case BOOK3S_CPU_POWER7:
>      case BOOK3S_CPU_POWER8:
> +    case BOOK3S_CPU_POWER9:
>          gen_spr_book3s_ids(env);
>          gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
>          gen_spr_book3s_purr(env);
> @@ -8293,6 +8295,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>          break;
>      case BOOK3S_CPU_POWER7:
>      case BOOK3S_CPU_POWER8:
> +    case BOOK3S_CPU_POWER9:
>      default:
>          env->slb_nr = 32;
>          break;
> @@ -8310,6 +8313,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>          ppcPOWER7_irq_init(ppc_env_get_cpu(env));
>          break;
>      case BOOK3S_CPU_POWER8:
> +    case BOOK3S_CPU_POWER9:
>          init_excp_POWER8(env);
>          ppcPOWER7_irq_init(ppc_env_get_cpu(env));
>          break;
> @@ -8772,6 +8776,85 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
>  }
> +static void init_proc_POWER9(CPUPPCState *env)
> +{
> +    init_proc_book3s_64(env, BOOK3S_CPU_POWER9);
> +}
> +
> +static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
> +{
> +    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
> +        return true;
> +    }
> +    return false;
> +}
> +
> +POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +
> +    dc->fw_name = "PowerPC,POWER9";
> +    dc->desc = "POWER9";
> +    dc->props = powerpc_servercpu_properties;
> +    pcc->pvr_match = ppc_pvr_match_power9;
> +    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
> +    pcc->init_proc = init_proc_POWER9;
> +    pcc->check_pow = check_pow_nocheck;
> +    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> +                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> +                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> +                       PPC_FLOAT_FRSQRTES |
> +                       PPC_FLOAT_STFIWX |
> +                       PPC_FLOAT_EXT |
> +                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> +                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
> +                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> +                       PPC_64B | PPC_64BX | PPC_ALTIVEC |
> +                       PPC_SEGMENT_64B | PPC_SLBI |
> +                       PPC_POPCNTB | PPC_POPCNTWD |
> +                       PPC_CILDST;
> +    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
> +                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
> +                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
> +                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
> +                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> +                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> +                        PPC2_TM | PPC2_PM_ISA206;
> +    pcc->msr_mask = (1ull << MSR_SF) |
> +                    (1ull << MSR_TM) |
> +                    (1ull << MSR_VR) |
> +                    (1ull << MSR_VSX) |
> +                    (1ull << MSR_EE) |
> +                    (1ull << MSR_PR) |
> +                    (1ull << MSR_FP) |
> +                    (1ull << MSR_ME) |
> +                    (1ull << MSR_FE0) |
> +                    (1ull << MSR_SE) |
> +                    (1ull << MSR_DE) |
> +                    (1ull << MSR_FE1) |
> +                    (1ull << MSR_IR) |
> +                    (1ull << MSR_DR) |
> +                    (1ull << MSR_PMM) |
> +                    (1ull << MSR_RI) |
> +                    (1ull << MSR_LE);
> +    pcc->mmu_model = POWERPC_MMU_3_00;
> +#if defined(CONFIG_SOFTMMU)
> +    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> +    /* segment page size remain the same */
> +    pcc->sps = &POWER7_POWER8_sps;
> +#endif
> +    pcc->excp_model = POWERPC_EXCP_POWER8;
> +    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> +    pcc->bfd_mach = bfd_mach_ppc64;
> +    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> +                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> +                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
> +                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
> +    pcc->l1_dcache_size = 0x8000;
> +    pcc->l1_icache_size = 0x8000;
> +    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +}
>  
>  #if !defined(CONFIG_USER_ONLY)
>  

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [RFC 2/6] target-ppc: Introduce POWER ISA 3.0 flag

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 2496 bytes --]

On Tue, Jul 12, 2016 at 11:33:18PM +0530, Nikunj A Dadhania wrote:
> This flag will be used for POWER9 instructions.
> 
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target-ppc/cpu.h            | 5 ++++-
>  target-ppc/translate_init.c | 2 +-
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 2666a3f..f48ff0f 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -2093,6 +2093,8 @@ enum {
>      PPC2_TM            = 0x0000000000020000ULL,
>      /* Server PM instructgions (ISA 2.06, Book III)                          */
>      PPC2_PM_ISA206     = 0x0000000000040000ULL,
> +    /* POWER ISA 3.0                                                         */
> +    PPC2_ISA300        = 0x0000000000080000ULL,
>  
>  #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
>                          PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
> @@ -2100,7 +2102,8 @@ enum {
>                          PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
>                          PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
>                          PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
> -                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206)
> +                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
> +                        PPC2_ISA300)
>  };
>  
>  /*****************************************************************************/
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 51bab23..9852524 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8820,7 +8820,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
>                          PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
>                          PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
>                          PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> -                        PPC2_TM | PPC2_PM_ISA206;
> +                        PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300;
>      pcc->msr_mask = (1ull << MSR_SF) |
>                      (1ull << MSR_TM) |
>                      (1ull << MSR_VR) |

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [RFC 3/6] target-ppc: adding addpcis instruction

[David Gibson]

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On Tue, Jul 12, 2016 at 11:33:19PM +0530, Nikunj A Dadhania wrote:
> ISA 3.0 instruction for adding immediate value with next instruction
> address and return the result in the target register.
> 
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target-ppc/translate.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 92030b6..93c7c66 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -432,6 +432,20 @@ static inline uint32_t name(uint32_t opcode)                                  \
>      return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |             \
>              ((opcode >> (shift2)) & ((1 << (nb2)) - 1));                      \
>  }
> +
> +#define EXTRACT_HELPER_DXFORM(name,                                           \
> +                              d0_bits, shift_op_d0, shift_d0,                 \
> +                              d1_bits, shift_op_d1, shift_d1,                 \
> +                              d2_bits, shift_op_d2, shift_d2)                 \
> +static inline int16_t name(uint32_t opcode)                                   \
> +{                                                                             \
> +    return                                                                    \
> +        (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
> +        (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
> +        (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2));  \
> +}
> +
> +
>  /* Opcode part 1 */
>  EXTRACT_HELPER(opc1, 26, 6);
>  /* Opcode part 2 */
> @@ -501,6 +515,9 @@ EXTRACT_HELPER(FPL, 25, 1);
>  EXTRACT_HELPER(FPFLM, 17, 8);
>  EXTRACT_HELPER(FPW, 16, 1);
>  
> +/* addpcis */
> +EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
> +
>  /***                            Jump target decoding                       ***/
>  /* Immediate address */
>  static inline target_ulong LI(uint32_t opcode)
> @@ -984,6 +1001,15 @@ static void gen_addis(DisasContext *ctx)
>      }
>  }
>  
> +/* addpcis */
> +static void gen_addpcis(DisasContext *ctx)
> +{
> +    target_long d = DX(ctx->opcode);
> +
> +    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip);
> +    tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], d);
> +}
> +
>  static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
>                                       TCGv arg2, int sign, int compute_ov)
>  {
> @@ -9877,6 +9903,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
>  GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
>  GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
>  GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> +GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
>  GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
>  GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
>  GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [RFC 4/6] target-ppc: add cmprb instruction

[David Gibson]

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On Tue, Jul 12, 2016 at 11:33:20PM +0530, Nikunj A Dadhania wrote:
> ISA 3.0 Compare Ranged Byte instruction useful for
> isupper/islower/isaplha kind of operation.

At least until you have locale-aware versions of those...

> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target-ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 93c7c66..8de217f 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -817,6 +817,45 @@ static void gen_cmpli(DisasContext *ctx)
>      }
>  }
>  
> +/* cmprb - range comparison: isupper, isaplha, islower*/
> +static void gen_cmprb(DisasContext *ctx)
> +{
> +    TCGLabel *lab1 = gen_new_label();
> +    TCGLabel *lab2 = gen_new_label();
> +    TCGv src1 = tcg_temp_local_new();
> +    TCGv src2 = tcg_temp_local_new();
> +    TCGv src2lo = tcg_temp_local_new();
> +    TCGv src2hi = tcg_temp_local_new();
> +
> +    tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
> +    tcg_gen_andi_tl(src2, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF);
> +
> +    tcg_gen_andi_tl(src2lo, src2, 0xFF);
> +    tcg_gen_shri_tl(src2hi, src2, 8);
> +    tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
> +
> +    tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab1);
> +    tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab1);
> +    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
> +    tcg_gen_br(lab2);
> +    gen_set_label(lab1);
> +
> +    if (ctx->opcode & 0x00200000) {
> +        tcg_gen_shri_tl(src2hi, src2, 24);
> +        tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
> +        tcg_gen_shri_tl(src2lo, src2, 16);
> +        tcg_gen_andi_tl(src2lo, src2lo, 0xFF);
> +        tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab2);
> +        tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab2);
> +        tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
> +    }
> +    gen_set_label(lab2);
> +    tcg_temp_free(src1);
> +    tcg_temp_free(src2);
> +    tcg_temp_free(src2lo);
> +    tcg_temp_free(src2hi);
> +}
> +
>  /* isel (PowerPC 2.03 specification) */
>  static void gen_isel(DisasContext *ctx)
>  {
> @@ -9898,6 +9937,7 @@ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
>  GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
>  GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
>  GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
> +GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
>  GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
>  GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
>  GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [RFC 5/6] target-ppc: add modulo word operations

[David Gibson]

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On Tue, Jul 12, 2016 at 11:33:21PM +0530, Nikunj A Dadhania wrote:
> Adding following instructions:
> 
> moduw: Modulo Unsigned Word
> modsw: Modulo Signed Word
> 
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>

Hrm.. any reason you're not using the TCG inbuilt remainder ops
(tcg_gen_rem_i32() etc.)?

> ---
>  target-ppc/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 8de217f..c505684 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -1178,6 +1178,54 @@ GEN_DIVE(divde, divde, 0);
>  GEN_DIVE(divdeo, divde, 1);
>  #endif
>  
> +static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
> +                                     TCGv arg2, int sign)
> +{
> +    TCGLabel *l1 = gen_new_label();
> +    TCGLabel *l2 = gen_new_label();
> +    TCGv_i32 t0 = tcg_temp_local_new_i32();
> +    TCGv_i32 t1 = tcg_temp_local_new_i32();
> +    TCGv_i32 t2 = tcg_temp_local_new_i32();
> +
> +    tcg_gen_trunc_tl_i32(t0, arg1);
> +    tcg_gen_trunc_tl_i32(t1, arg2);
> +    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
> +    if (sign) {
> +        TCGLabel *l3 = gen_new_label();
> +        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
> +        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
> +        gen_set_label(l3);
> +        tcg_gen_div_i32(t2, t0, t1);
> +    } else {
> +        tcg_gen_divu_i32(t2, t0, t1);
> +    }
> +    tcg_gen_mul_i32(t2, t2, t1);
> +    tcg_gen_sub_i32(t2, t0, t2);
> +    tcg_gen_br(l2);
> +    gen_set_label(l1);
> +    if (sign) {
> +        tcg_gen_sari_i32(t2, t0, 31);
> +    } else {
> +        tcg_gen_movi_i32(t2, 0);
> +    }
> +    gen_set_label(l2);
> +    tcg_gen_extu_i32_tl(ret, t2);
> +    tcg_temp_free_i32(t0);
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t2);
> +}
> +
> +#define GEN_INT_ARITH_MODW(name, opc3, sign)                                \
> +static void glue(gen_, name)(DisasContext *ctx)                             \
> +{                                                                           \
> +    gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)],                        \
> +                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
> +                      sign);                                                \
> +}
> +
> +GEN_INT_ARITH_MODW(modsw, 0x18, 1);
> +GEN_INT_ARITH_MODW(moduw, 0x08, 0);
> +
>  /* mulhw  mulhw. */
>  static void gen_mulhw(DisasContext *ctx)
>  {
> @@ -10244,6 +10292,8 @@ GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
>  GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
>  GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
>  GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
> +GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
>  
>  #if defined(TARGET_PPC64)
>  #undef GEN_INT_ARITH_DIVD

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [RFC 5/6] target-ppc: add modulo word operations

[Nikunj A Dadhania]

David Gibson <david@gibson.dropbear.id.au> writes:

> [ Unknown signature status ]
> On Tue, Jul 12, 2016 at 11:33:21PM +0530, Nikunj A Dadhania wrote:
>> Adding following instructions:
>> 
>> moduw: Modulo Unsigned Word
>> modsw: Modulo Signed Word
>> 
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>
> Hrm.. any reason you're not using the TCG inbuilt remainder ops
> (tcg_gen_rem_i32() etc.)?

I have an updated version with me which uses inbuilt ops, i was searching
for modulo expressions, which I didn't find, so wrote. Found later that
it is called tcg_gen_rem. Will send in the next version.

Regards
Nikunj

Re: [Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family

[Nikunj A Dadhania]

David Gibson <david@gibson.dropbear.id.au> writes:

> [ Unknown signature status ]
> On Tue, Jul 12, 2016 at 11:33:17PM +0530, Nikunj A Dadhania wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>> 
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> [ rebased and added POWER9 alias ]
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>>  target-ppc/cpu-models.c     |  5 +++
>>  target-ppc/cpu-models.h     |  2 ++
>>  target-ppc/cpu-qom.h        |  7 ++++
>>  target-ppc/mmu_helper.c     |  3 +-
>>  target-ppc/translate_init.c | 85 ++++++++++++++++++++++++++++++++++++++++++++-
>>  5 files changed, 100 insertions(+), 2 deletions(-)
>> 
>> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
>> index 5209e63..901cf40 100644
>> --- a/target-ppc/cpu-models.c
>> +++ b/target-ppc/cpu-models.c
>> @@ -1147,6 +1147,10 @@
>>                  "POWER8NVL v1.0")
>>      POWERPC_DEF("970_v2.2",      CPU_POWERPC_970_v22,                970,
>>                  "PowerPC 970 v2.2")
>> +
>> +    POWERPC_DEF("POWER9_v1.0",   CPU_POWERPC_POWER9_BASE,            POWER9,
>> +                "POWER9 v1.0")
>> +
>>      POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970,
>>                  "PowerPC 970FX v1.0 (G5)")
>>      POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970,
>> @@ -1395,6 +1399,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
>>      { "POWER8E", "POWER8E_v2.1" },
>>      { "POWER8", "POWER8_v2.0" },
>>      { "POWER8NVL", "POWER8NVL_v1.0" },
>> +    { "POWER9", "POWER9_v1.0" },
>>      { "970", "970_v2.2" },
>>      { "970fx", "970fx_v3.1" },
>>      { "970mp", "970mp_v1.1" },
>> diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
>> index f21a44c..beeaaba 100644
>> --- a/target-ppc/cpu-models.h
>> +++ b/target-ppc/cpu-models.h
>> @@ -562,6 +562,8 @@ enum {
>>      CPU_POWERPC_POWER8_v20         = 0x004D0200,
>>      CPU_POWERPC_POWER8NVL_BASE     = 0x004C0000,
>>      CPU_POWERPC_POWER8NVL_v10      = 0x004C0100,
>> +    CPU_POWERPC_POWER9_BASE        = 0x004E0000,
>> +    CPU_POWERPC_POWER9_MAM         = 0x004E0100,
>>      CPU_POWERPC_970_v22            = 0x00390202,
>>      CPU_POWERPC_970FX_v10          = 0x00391100,
>>      CPU_POWERPC_970FX_v20          = 0x003C0200,
>> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
>> index 2864105..df2fb65 100644
>> --- a/target-ppc/cpu-qom.h
>> +++ b/target-ppc/cpu-qom.h
>> @@ -86,6 +86,13 @@ enum powerpc_mmu_t {
>>      POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
>>                               | POWERPC_MMU_64K
>>                               | POWERPC_MMU_AMR | 0x00000004,
>> +    /* for now , We can add radix later if needed */
>
> I'm guessing this means you're only thinking about the guest-side
> presentation of the P9 MMU at this point?  IIUC the host side
> presentation is so different that sharing any constants with pre-P9
> MMUs probably doesn't make sense.
>
> I'm not immediately sure how we should make this distinction in the
> target-ppc code, since these values are supposed to belong to the CPU
> regardless of operating mode.

Currently, this is just a place holder patch. Not close to committing
yet. For me to add the new instruction needed these family defines.

Regards,
Nikunj

Re: [Qemu-devel] [RFC 3/6] target-ppc: adding addpcis instruction

[Richard Henderson]

On 07/12/2016 11:33 PM, Nikunj A Dadhania wrote:
> +static void gen_addpcis(DisasContext *ctx)
> +{
> +    target_long d = DX(ctx->opcode);
> +
> +    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip);
> +    tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], d);
> +}

(1) You appear to have forgotten the "shift" part of "addpcis".
(2) Both of these are translate-time constants, so...

    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));


r~

Re: [Qemu-devel] [RFC 4/6] target-ppc: add cmprb instruction

[Richard Henderson]

On 07/12/2016 11:33 PM, Nikunj A Dadhania wrote:
> +/* cmprb - range comparison: isupper, isaplha, islower*/
> +static void gen_cmprb(DisasContext *ctx)
> +{
> +    TCGLabel *lab1 = gen_new_label();
> +    TCGLabel *lab2 = gen_new_label();
> +    TCGv src1 = tcg_temp_local_new();
> +    TCGv src2 = tcg_temp_local_new();
> +    TCGv src2lo = tcg_temp_local_new();
> +    TCGv src2hi = tcg_temp_local_new();
> +
> +    tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
> +    tcg_gen_andi_tl(src2, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF);

There's no point in this mask, since it's covered by

> +
> +    tcg_gen_andi_tl(src2lo, src2, 0xFF);
> +    tcg_gen_shri_tl(src2hi, src2, 8);
> +    tcg_gen_andi_tl(src2hi, src2hi, 0xFF);

these ones.

> +
> +    tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab1);
> +    tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab1);
> +    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
> +    tcg_gen_br(lab2);
> +    gen_set_label(lab1);
> +
> +    if (ctx->opcode & 0x00200000) {
> +        tcg_gen_shri_tl(src2hi, src2, 24);
> +        tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
> +        tcg_gen_shri_tl(src2lo, src2, 16);
> +        tcg_gen_andi_tl(src2lo, src2lo, 0xFF);
> +        tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab2);
> +        tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab2);
> +        tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
> +    }
> +    gen_set_label(lab2);
> +    tcg_temp_free(src1);
> +    tcg_temp_free(src2);
> +    tcg_temp_free(src2lo);
> +    tcg_temp_free(src2hi);
> +}

You've forgotten to clear crf in the false case.

This is better implemented without branches, like

   TCGv_i32 src1, src2, src2lo, src2hi;
   TCGv_i32 crf = cpu_crf[cdfD(ctx->opcode)];

   // allocate all 4 "src" temps

   tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
   tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);

   tcg_gen_ext8u_i32(src2lo, src2);
   tcg_gen_shri_i32(src2, src2, 8);
   tcg_gen_extu8_i32(src2hi, src2hi);

   tcg_gen_setcond_tl(TCG_COND_LEU, src2lo, src2lo, src1);
   tcg_gen_setcond_tl(TCG_COND_LEU, src2hi, src1, src2hi);
   tcg_gen_and_tl(crf, src2lo, src2hi);

   if (ctx->opcode & 0x00200000) {
     tcg_gen_shri_i32(src2, src2, 8);
     tcg_gen_ext8u_i32(src2lo, src2);
     tcg_gen_shri_i32(src2, src2, 8);
     tcg_gen_ext8u_i32(src2hi, src2);
     tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
     tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
     tcg_gen_and_i32(src2lo, src2lo, src2hi);
     tcg_gen_or_i32(crf, crf, src2lo);
   }

   tcg_gen_shli_i32(crf, crf, CRF_GT);

   // free all 4 "src" temps


r~

Re: [Qemu-devel] [RFC 5/6] target-ppc: add modulo word operations

[Richard Henderson]

On 07/18/2016 10:38 AM, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
>> [ Unknown signature status ]
>> On Tue, Jul 12, 2016 at 11:33:21PM +0530, Nikunj A Dadhania wrote:
>>> Adding following instructions:
>>>
>>> moduw: Modulo Unsigned Word
>>> modsw: Modulo Signed Word
>>>
>>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>>
>> Hrm.. any reason you're not using the TCG inbuilt remainder ops
>> (tcg_gen_rem_i32() etc.)?
>
> I have an updated version with me which uses inbuilt ops, i was searching
> for modulo expressions, which I didn't find, so wrote. Found later that
> it is called tcg_gen_rem. Will send in the next version.

It would probably be better to use helper functions for both div and mod, 
because of the branches required.

C.f. target-arm/helper-a64.c, helper_sdiv64 et al.


r~

Re: [Qemu-devel] [RFC 3/6] target-ppc: adding addpcis instruction

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> On 07/12/2016 11:33 PM, Nikunj A Dadhania wrote:
>> +static void gen_addpcis(DisasContext *ctx)
>> +{
>> +    target_long d = DX(ctx->opcode);
>> +
>> +    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip);
>> +    tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], d);
>> +}
>
> (1) You appear to have forgotten the "shift" part of "addpcis".

Yes, i had not seen this reply.

> (2) Both of these are translate-time constants, so...
>
>     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));

Sure

Regards
Nikunj

Re: [Qemu-devel] [RFC 4/6] target-ppc: add cmprb instruction

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> On 07/12/2016 11:33 PM, Nikunj A Dadhania wrote:
>> +/* cmprb - range comparison: isupper, isaplha, islower*/
>> +static void gen_cmprb(DisasContext *ctx)
>> +{
>> +    TCGLabel *lab1 = gen_new_label();
>> +    TCGLabel *lab2 = gen_new_label();
>> +    TCGv src1 = tcg_temp_local_new();
>> +    TCGv src2 = tcg_temp_local_new();
>> +    TCGv src2lo = tcg_temp_local_new();
>> +    TCGv src2hi = tcg_temp_local_new();
>> +
>> +    tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
>> +    tcg_gen_andi_tl(src2, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF);
>
> There's no point in this mask, since it's covered by
>
>> +
>> +    tcg_gen_andi_tl(src2lo, src2, 0xFF);
>> +    tcg_gen_shri_tl(src2hi, src2, 8);
>> +    tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
>
> these ones.

Right.


>> +
>> +    tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab1);
>> +    tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab1);
>> +    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
>> +    tcg_gen_br(lab2);
>> +    gen_set_label(lab1);
>> +
>> +    if (ctx->opcode & 0x00200000) {
>> +        tcg_gen_shri_tl(src2hi, src2, 24);
>> +        tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
>> +        tcg_gen_shri_tl(src2lo, src2, 16);
>> +        tcg_gen_andi_tl(src2lo, src2lo, 0xFF);
>> +        tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab2);
>> +        tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab2);
>> +        tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
>> +    }
>> +    gen_set_label(lab2);
>> +    tcg_temp_free(src1);
>> +    tcg_temp_free(src2);
>> +    tcg_temp_free(src2lo);
>> +    tcg_temp_free(src2hi);
>> +}
>
> You've forgotten to clear crf in the false case.

Yes, next version has the fix.

> This is better implemented without branches, like
>
>    TCGv_i32 src1, src2, src2lo, src2hi;
>    TCGv_i32 crf = cpu_crf[cdfD(ctx->opcode)];
>
>    // allocate all 4 "src" temps
>
>    tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
>    tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
>
>    tcg_gen_ext8u_i32(src2lo, src2);
>    tcg_gen_shri_i32(src2, src2, 8);
>    tcg_gen_extu8_i32(src2hi, src2hi);
>
>    tcg_gen_setcond_tl(TCG_COND_LEU, src2lo, src2lo, src1);
>    tcg_gen_setcond_tl(TCG_COND_LEU, src2hi, src1, src2hi);
>    tcg_gen_and_tl(crf, src2lo, src2hi);
>
>    if (ctx->opcode & 0x00200000) {
>      tcg_gen_shri_i32(src2, src2, 8);
>      tcg_gen_ext8u_i32(src2lo, src2);
>      tcg_gen_shri_i32(src2, src2, 8);
>      tcg_gen_ext8u_i32(src2hi, src2);
>      tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
>      tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
>      tcg_gen_and_i32(src2lo, src2lo, src2hi);
>      tcg_gen_or_i32(crf, crf, src2lo);
>    }
>
>    tcg_gen_shli_i32(crf, crf, CRF_GT);
>
>    // free all 4 "src" temps

Sure.

Regards
Nikunj

Re: [Qemu-devel] [RFC 5/6] target-ppc: add modulo word operations

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> On 07/18/2016 10:38 AM, Nikunj A Dadhania wrote:
>> David Gibson <david@gibson.dropbear.id.au> writes:
>>
>>> [ Unknown signature status ]
>>> On Tue, Jul 12, 2016 at 11:33:21PM +0530, Nikunj A Dadhania wrote:
>>>> Adding following instructions:
>>>>
>>>> moduw: Modulo Unsigned Word
>>>> modsw: Modulo Signed Word
>>>>
>>>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>>>
>>> Hrm.. any reason you're not using the TCG inbuilt remainder ops
>>> (tcg_gen_rem_i32() etc.)?
>>
>> I have an updated version with me which uses inbuilt ops, i was searching
>> for modulo expressions, which I didn't find, so wrote. Found later that
>> it is called tcg_gen_rem. Will send in the next version.
>
> It would probably be better to use helper functions for both div and mod, 
> because of the branches required.
>
> C.f. target-arm/helper-a64.c, helper_sdiv64 et al.

What is the thumb rule to implement it has helper?
As I am implementing other instructions as well.

One as you suggested many branches.

Regards
Nikunj

Re: [Qemu-devel] [RFC 5/6] target-ppc: add modulo word operations

[Richard Henderson]

On 07/21/2016 01:41 PM, Nikunj A Dadhania wrote:
>> It would probably be better to use helper functions for both div and mod,
>> because of the branches required.
>>
>> C.f. target-arm/helper-a64.c, helper_sdiv64 et al.
>
> What is the thumb rule to implement it has helper?
> As I am implementing other instructions as well.
>
> One as you suggested many branches.

Branches, or more than, say, 15 tcg instructions.

The former rule is primarily because branches inhibit all tcg optimization.

The latter rule is more flexible, depending on how many of them you expect may 
be able to optimize away.  For ppc, I would expect few dead code opportunities; 
those are more for cisc targets that compute flags with every instruction.


r~

Re: [Qemu-devel] [RFC 4/6] target-ppc: add cmprb instruction

[Nikunj A Dadhania]

Richard Henderson <rth@twiddle.net> writes:

> This is better implemented without branches, like
>
>    TCGv_i32 src1, src2, src2lo, src2hi;
>    TCGv_i32 crf = cpu_crf[cdfD(ctx->opcode)];
>
>    // allocate all 4 "src" temps
>
>    tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
>    tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
>

As the user input can pass something more than 0xFF, we need only the
RA(56:63). Anton's fuzzer test hit this bug. :-)

GPR06 0x0706050403021101
cmprb   cr5,1,r6,r6

Should be a match (RA = 0x01, RB=0x03021101), but fails

     tcg_gen_andi_i32(src1, src1, 0xFF);

Will send an fix patch, we can probably squash with the original one.

>    tcg_gen_ext8u_i32(src2lo, src2);
>    tcg_gen_shri_i32(src2, src2, 8);
>    tcg_gen_extu8_i32(src2hi, src2hi);
>
>    tcg_gen_setcond_tl(TCG_COND_LEU, src2lo, src2lo, src1);
>    tcg_gen_setcond_tl(TCG_COND_LEU, src2hi, src1, src2hi);
>    tcg_gen_and_tl(crf, src2lo, src2hi);
>
>    if (ctx->opcode & 0x00200000) {
>      tcg_gen_shri_i32(src2, src2, 8);
>      tcg_gen_ext8u_i32(src2lo, src2);
>      tcg_gen_shri_i32(src2, src2, 8);
>      tcg_gen_ext8u_i32(src2hi, src2);
>      tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
>      tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
>      tcg_gen_and_i32(src2lo, src2lo, src2hi);
>      tcg_gen_or_i32(crf, crf, src2lo);
>    }
>
>    tcg_gen_shli_i32(crf, crf, CRF_GT);
>
>    // free all 4 "src" temps

Regards
Nikunj