* [PATCH 1/2] drm/dp: Add defines for latency in sink
@ 2017-09-20 14:32 vathsala nagaraju
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
` (4 more replies)
0 siblings, 5 replies; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-20 14:32 UTC (permalink / raw)
To: rodrigo.vivi, dri-devel, intel-gfx
Cc: Puthikorn Voravootivat, vathsala nagaraju
Add defines for dpcd register 2009 (synchronization latency
in sink).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
include/drm/drm_dp_helper.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11c39f1..846004e6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -735,6 +735,9 @@
# define DP_PSR_SINK_INTERNAL_ERROR 7
# define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
+# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
+
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
--
1.9.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
@ 2017-09-20 14:32 ` vathsala nagaraju
2017-09-20 14:44 ` Ville Syrjälä
2017-09-20 15:19 ` Vivi, Rodrigo
2017-09-20 14:58 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink Patchwork
` (3 subsequent siblings)
4 siblings, 2 replies; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-20 14:32 UTC (permalink / raw)
To: rodrigo.vivi, dri-devel, intel-gfx
Cc: Puthikorn Voravootivat, vathsala nagaraju
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index acb5094..04b253f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+ &sink_latency)) {
+ sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
+ val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
+ } else {
+ val |= EDP_FRAMES_BEFORE_SU_ENTRY;
+ }
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
1.9.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
@ 2017-09-20 14:44 ` Ville Syrjälä
2017-09-20 15:19 ` Vivi, Rodrigo
1 sibling, 0 replies; 19+ messages in thread
From: Ville Syrjälä @ 2017-09-20 14:44 UTC (permalink / raw)
To: vathsala nagaraju
Cc: Puthikorn Voravootivat, intel-gfx, dri-devel, rodrigo.vivi
On Wed, Sep 20, 2017 at 08:02:35PM +0530, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency)) {
== 1
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> + val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
> + } else {
> + val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> + }
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-20 14:44 ` Ville Syrjälä
@ 2017-09-20 15:19 ` Vivi, Rodrigo
2017-09-22 15:58 ` vathsala nagaraju
1 sibling, 1 reply; 19+ messages in thread
From: Vivi, Rodrigo @ 2017-09-20 15:19 UTC (permalink / raw)
To: Nagaraju, Vathsala; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
> On Sep 20, 2017, at 7:33 AM, Nagaraju, Vathsala <vathsala.nagaraju@intel.com> wrote:
>
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
Please also remove the definition of this su_entry since it was not following the new standards anyway...
Probably good to replace with function macro style for better use below...
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency)) {
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> + val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
... so you could use
val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency +1);
> + } else {
> + val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> + }
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-20 15:19 ` Vivi, Rodrigo
@ 2017-09-22 15:58 ` vathsala nagaraju
2017-09-22 23:54 ` Rodrigo Vivi
2017-09-28 16:54 ` Rodrigo Vivi
0 siblings, 2 replies; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-22 15:58 UTC (permalink / raw)
To: rodrigo.vivi; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..89c5249 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
(mask) << 16 | (value); })
#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
/* Engine ID */
@@ -4047,7 +4048,6 @@ enum {
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
#define EDP_PSR2_IDLE_MASK 0xf
-#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..e505fa6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+ &sink_latency) == 1) {
+ sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
+ } else {
+ sink_latency = 0;
+ }
+ val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
1.9.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-22 15:58 ` vathsala nagaraju
@ 2017-09-22 23:54 ` Rodrigo Vivi
2017-09-28 16:54 ` Rodrigo Vivi
1 sibling, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2017-09-22 23:54 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
> - add check ==1 for dpcd_read call (ville)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..89c5249 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> (mask) << 16 | (value); })
> #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
> #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
not here
>
> /* Engine ID */
>
> @@ -4047,7 +4048,6 @@ enum {
> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
> #define EDP_PSR2_IDLE_MASK 0xf
> -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
move here
>
> #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..e505fa6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency) == 1) {
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
with those changes
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> + } else {
> + sink_latency = 0;
> + }
> + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-22 15:58 ` vathsala nagaraju
2017-09-22 23:54 ` Rodrigo Vivi
@ 2017-09-28 16:54 ` Rodrigo Vivi
2017-09-29 11:36 ` Jani Nikula
1 sibling, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2017-09-28 16:54 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
> - add check ==1 for dpcd_read call (ville)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Merged both patches to dinq. Thanks for the patches.
I'm anxiously waiting the PSR2 related workaroud(s)! ;)
Thanks,
Rodrigo.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..89c5249 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> (mask) << 16 | (value); })
> #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
> #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
>
> /* Engine ID */
>
> @@ -4047,7 +4048,6 @@ enum {
> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
> #define EDP_PSR2_IDLE_MASK 0xf
> -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
>
> #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..e505fa6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency) == 1) {
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> + } else {
> + sink_latency = 0;
> + }
> + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-28 16:54 ` Rodrigo Vivi
@ 2017-09-29 11:36 ` Jani Nikula
0 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2017-09-29 11:36 UTC (permalink / raw)
To: Rodrigo Vivi, vathsala nagaraju
Cc: Puthikorn Voravootivat, intel-gfx, Sean Paul, dri-devel
On Thu, 28 Sep 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Merged both patches to dinq. Thanks for the patches.
While patch 1 was a simple addition of a few DP macros, we need to get
ack from Dave or (preferrably non-Intel) drm-misc maintainers before
queuing non-i915 patches through drm-intel.
Dave, Sean, ack after the fact...?
The patch is [1].
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/1506419953-32605-1-git-send-email-vathsala.nagaraju@intel.com
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 19+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
@ 2017-09-20 14:58 ` Patchwork
2017-09-20 15:51 ` ✗ Fi.CI.IGT: warning " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2017-09-20 14:58 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/dp: Add defines for latency in sink
URL : https://patchwork.freedesktop.org/series/30658/
State : success
== Summary ==
Series 30658v1 series starting with [1/2] drm/dp: Add defines for latency in sink
https://patchwork.freedesktop.org/api/1.0/series/30658/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS (fi-kbl-7500u) fdo#102850
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail -> PASS (fi-snb-2600) fdo#100215
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip -> PASS (fi-ivb-3520m)
Subgroup force-edid:
skip -> PASS (fi-ivb-3520m)
Subgroup force-load-detect:
skip -> PASS (fi-ivb-3520m)
Subgroup prune-stale-modes:
skip -> PASS (fi-ivb-3520m)
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (fi-cfl-s) fdo#102294
fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:469s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:420s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:515s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:277s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:502s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:488s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:493s
fi-cfl-s total:289 pass:223 dwarn:34 dfail:0 fail:0 skip:32 time:548s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:425s
fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:568s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:423s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:405s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:484s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:467s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:475s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:568s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:540s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:441s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:749s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:567s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:411s
ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest
8dc01494eee9 drm/i915/psr: Set frames before SU entry for psr2
568cf132cf88 drm/dp: Add defines for latency in sink
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5765/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/dp: Add defines for latency in sink
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-20 14:58 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink Patchwork
@ 2017-09-20 15:51 ` Patchwork
2017-09-20 22:07 ` [PATCH 1/2] " Rodrigo Vivi
2017-09-21 14:42 ` Rodrigo Vivi
4 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2017-09-20 15:51 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/dp: Add defines for latency in sink
URL : https://patchwork.freedesktop.org/series/30658/
State : warning
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hsw) fdo#102252 +1
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-A-planes:
pass -> DMESG-WARN (shard-hsw)
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2317 pass:1244 dwarn:3 dfail:0 fail:13 skip:1057 time:9583s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5765/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 1/2] drm/dp: Add defines for latency in sink
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
` (2 preceding siblings ...)
2017-09-20 15:51 ` ✗ Fi.CI.IGT: warning " Patchwork
@ 2017-09-20 22:07 ` Rodrigo Vivi
2017-09-21 14:42 ` Rodrigo Vivi
4 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2017-09-20 22:07 UTC (permalink / raw)
To: vathsala nagaraju, g; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> include/drm/drm_dp_helper.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 11c39f1..846004e6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -735,6 +735,9 @@
> # define DP_PSR_SINK_INTERNAL_ERROR 7
> # define DP_PSR_SINK_STATE_MASK 0x07
>
> +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
> +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
where did you get that?
eDP 1.4 teels 2009h is a debug register.
> +
> #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
>
> --
> 1.9.1
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 1/2] drm/dp: Add defines for latency in sink
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
` (3 preceding siblings ...)
2017-09-20 22:07 ` [PATCH 1/2] " Rodrigo Vivi
@ 2017-09-21 14:42 ` Rodrigo Vivi
2017-09-26 5:11 ` Daniel Vetter
4 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2017-09-21 14:42 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
I keep forgetting to update my eDP spec 1.4 to this 1.4b...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> include/drm/drm_dp_helper.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 11c39f1..846004e6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -735,6 +735,9 @@
> # define DP_PSR_SINK_INTERNAL_ERROR 7
> # define DP_PSR_SINK_STATE_MASK 0x07
>
> +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
> +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
> +
> #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
>
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 1/2] drm/dp: Add defines for latency in sink
2017-09-21 14:42 ` Rodrigo Vivi
@ 2017-09-26 5:11 ` Daniel Vetter
2017-09-26 17:37 ` Puthikorn Voravootivat
0 siblings, 1 reply; 19+ messages in thread
From: Daniel Vetter @ 2017-09-26 5:11 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
> On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> > Add defines for dpcd register 2009 (synchronization latency
> > in sink).
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Puthikorn Voravootivat <puthik@chromium.org>
> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>
> I keep forgetting to update my eDP spec 1.4 to this 1.4b...
Maybe the patch should then make this clear, by annotating it with
/* eDP 1.4b */ That's missing, which isn't all that great really, since it
makes specs hunts like yours necessary.
Please fix up before applying.
-Daniel
>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>
>
> > ---
> > include/drm/drm_dp_helper.h | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 11c39f1..846004e6 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -735,6 +735,9 @@
> > # define DP_PSR_SINK_INTERNAL_ERROR 7
> > # define DP_PSR_SINK_STATE_MASK 0x07
> >
> > +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
> > +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
> > +
> > #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> > # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
> >
> > --
> > 1.9.1
> >
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] drm/dp: Add defines for latency in sink
2017-09-26 5:11 ` Daniel Vetter
@ 2017-09-26 17:37 ` Puthikorn Voravootivat
2017-09-26 20:37 ` Puthikorn Voravootivat
0 siblings, 1 reply; 19+ messages in thread
From: Puthikorn Voravootivat @ 2017-09-26 17:37 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel, Rodrigo Vivi
[-- Attachment #1.1: Type: text/plain, Size: 1895 bytes --]
On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
> > On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> > > Add defines for dpcd register 2009 (synchronization latency
> > > in sink).
> > >
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > CC: Puthikorn Voravootivat <puthik@chromium.org>
> > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> >
> > I keep forgetting to update my eDP spec 1.4 to this 1.4b...
>
> Maybe the patch should then make this clear, by annotating it with
> /* eDP 1.4b */ That's missing, which isn't all that great really, since it
> makes specs hunts like yours necessary.
>
> It's actually in eDP 1.4 spec, table 5-6 page 86
> Please fix up before applying.
> -Daniel
> >
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> >
> >
> > > ---
> > > include/drm/drm_dp_helper.h | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > > index 11c39f1..846004e6 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -735,6 +735,9 @@
> > > # define DP_PSR_SINK_INTERNAL_ERROR 7
> > > # define DP_PSR_SINK_STATE_MASK 0x07
> > >
> > > +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
> > > +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
> > > +
> > > #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
> > > # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
> > >
> > > --
> > > 1.9.1
> > >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
>
[-- Attachment #1.2: Type: text/html, Size: 3414 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] drm/dp: Add defines for latency in sink
2017-09-26 17:37 ` Puthikorn Voravootivat
@ 2017-09-26 20:37 ` Puthikorn Voravootivat
2017-09-26 20:53 ` [Intel-gfx] " Rodrigo Vivi
0 siblings, 1 reply; 19+ messages in thread
From: Puthikorn Voravootivat @ 2017-09-26 20:37 UTC (permalink / raw)
To: Puthikorn Voravootivat; +Cc: intel-gfx, dri-devel, Rodrigo Vivi
[-- Attachment #1.1: Type: text/plain, Size: 2251 bytes --]
On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat <
puthik@chromium.org> wrote:
>
>
> On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
>
>> On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
>> > On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
>> > > Add defines for dpcd register 2009 (synchronization latency
>> > > in sink).
>> > >
>> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > > CC: Puthikorn Voravootivat <puthik@chromium.org>
>> > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> >
>> > I keep forgetting to update my eDP spec 1.4 to this 1.4b...
>>
>> Maybe the patch should then make this clear, by annotating it with
>> /* eDP 1.4b */ That's missing, which isn't all that great really, since it
>> makes specs hunts like yours necessary.
>>
>> It's actually in eDP 1.4 spec, table 5-6 page 86
>
Copy and paste the wrong one.
0x2009 is actually in eDP 1.4 spec, Table 6-7: DPCD – Sink Device PSR
Status Field page 124
>
>
>> Please fix up before applying.
>> -Daniel
>> >
>> >
>> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> >
>> >
>> >
>> > > ---
>> > > include/drm/drm_dp_helper.h | 3 +++
>> > > 1 file changed, 3 insertions(+)
>> > >
>> > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> > > index 11c39f1..846004e6 100644
>> > > --- a/include/drm/drm_dp_helper.h
>> > > +++ b/include/drm/drm_dp_helper.h
>> > > @@ -735,6 +735,9 @@
>> > > # define DP_PSR_SINK_INTERNAL_ERROR 7
>> > > # define DP_PSR_SINK_STATE_MASK 0x07
>> > >
>> > > +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
>> > > +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
>> > > +
>> > > #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
>> > > # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
>> > >
>> > > --
>> > > 1.9.1
>> > >
>> > _______________________________________________
>> > dri-devel mailing list
>> > dri-devel@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch
>>
>
>
[-- Attachment #1.2: Type: text/html, Size: 4910 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink
2017-09-26 20:37 ` Puthikorn Voravootivat
@ 2017-09-26 20:53 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2017-09-26 20:53 UTC (permalink / raw)
To: Puthikorn Voravootivat; +Cc: intel-gfx, DRI mailing list, Rodrigo Vivi
On Tue, Sep 26, 2017 at 1:37 PM, Puthikorn Voravootivat
<puthik@chromium.org> wrote:
>
>
> On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat
> <puthik@chromium.org> wrote:
>>
>>
>>
>> On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
>>>
>>> On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
>>> > On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
>>> > > Add defines for dpcd register 2009 (synchronization latency
>>> > > in sink).
>>> > >
>>> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> > > CC: Puthikorn Voravootivat <puthik@chromium.org>
>>> > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>> >
>>> > I keep forgetting to update my eDP spec 1.4 to this 1.4b...
>>>
>>> Maybe the patch should then make this clear, by annotating it with
>>> /* eDP 1.4b */ That's missing, which isn't all that great really, since
>>> it
>>> makes specs hunts like yours necessary.
>>>
>> It's actually in eDP 1.4 spec, table 5-6 page 86
>
> Copy and paste the wrong one.
> 0x2009 is actually in eDP 1.4 spec, Table 6-7: DPCD – Sink Device PSR Status
> Field page 124
you are absolutely right! eDP 1.4 has it. even the eDP 1.4a had...
I definitely had a strange version here... All updated locally here.
For the patch I will update when merging. No need to send a newer version.
I intend to merge patches tomorrow if no one has any other comment or
concern on those.
>
>>
>>
>>>
>>> Please fix up before applying.
>>> -Daniel
>>> >
>>> >
>>> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> >
>>> >
>>> >
>>> > > ---
>>> > > include/drm/drm_dp_helper.h | 3 +++
>>> > > 1 file changed, 3 insertions(+)
>>> > >
>>> > > diff --git a/include/drm/drm_dp_helper.h
>>> > > b/include/drm/drm_dp_helper.h
>>> > > index 11c39f1..846004e6 100644
>>> > > --- a/include/drm/drm_dp_helper.h
>>> > > +++ b/include/drm/drm_dp_helper.h
>>> > > @@ -735,6 +735,9 @@
>>> > > # define DP_PSR_SINK_INTERNAL_ERROR 7
>>> > > # define DP_PSR_SINK_STATE_MASK 0x07
>>> > >
>>> > > +#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
>>> > > +# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
>>> > > +
>>> > > #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
>>> > > # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
>>> > >
>>> > > --
>>> > > 1.9.1
>>> > >
>>> > _______________________________________________
>>> > dri-devel mailing list
>>> > dri-devel@lists.freedesktop.org
>>> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>>
>>> --
>>> Daniel Vetter
>>> Software Engineer, Intel Corporation
>>> http://blog.ffwll.ch
>>
>>
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/2] drm/dp: Add defines for latency in sink
@ 2017-09-23 0:34 vathsala nagaraju
2017-09-23 0:34 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
0 siblings, 1 reply; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-23 0:34 UTC (permalink / raw)
To: rodrigo.vivi, dri-devel, intel-gfx
Cc: Puthikorn Voravootivat, vathsala nagaraju
Add defines for dpcd register 2009 (synchronization latency
in sink).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
include/drm/drm_dp_helper.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11c39f1..846004e6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -735,6 +735,9 @@
# define DP_PSR_SINK_INTERNAL_ERROR 7
# define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SINK_SYNCHRONIZATION_LATENCY 0x2009
+# define DP_MAX_RESYNC_FRAME_CNT_MASK 0xf
+
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
--
1.9.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-23 0:34 vathsala nagaraju
@ 2017-09-23 0:34 ` vathsala nagaraju
2017-09-25 8:30 ` [Intel-gfx] " Jani Nikula
0 siblings, 1 reply; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-23 0:34 UTC (permalink / raw)
To: rodrigo.vivi, dri-devel, intel-gfx
Cc: Puthikorn Voravootivat, vathsala nagaraju
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
v3 : (Rodrigo)
- move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
- replace with &=
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..b880c84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4047,7 +4047,7 @@ enum {
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
#define EDP_PSR2_IDLE_MASK 0xf
-#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..adf7abc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+ &sink_latency) == 1) {
+ sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
+ } else {
+ sink_latency = 0;
+ }
+ val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
1.9.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-23 0:34 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
@ 2017-09-25 8:30 ` Jani Nikula
2017-09-25 9:10 ` vathsala nagaraju
0 siblings, 1 reply; 19+ messages in thread
From: Jani Nikula @ 2017-09-25 8:30 UTC (permalink / raw)
To: vathsala nagaraju, rodrigo.vivi, dri-devel, intel-gfx
Cc: Puthikorn Voravootivat
On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
> - add check ==1 for dpcd_read call (ville)
>
> v3 : (Rodrigo)
> - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
> - replace with &=
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..b880c84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4047,7 +4047,7 @@ enum {
> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
> #define EDP_PSR2_IDLE_MASK 0xf
> -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
In the register definitions we use the shift values directly, not the
macro. That's the style we've adopted. Please stick to it.
Ditto for the indent, why do you remove it?
BR,
Jani.
>
> #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..adf7abc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency) == 1) {
> + sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
> + } else {
> + sink_latency = 0;
> + }
> + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-25 8:30 ` [Intel-gfx] " Jani Nikula
@ 2017-09-25 9:10 ` vathsala nagaraju
2017-09-25 16:57 ` Rodrigo Vivi
0 siblings, 1 reply; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-25 9:10 UTC (permalink / raw)
To: Jani Nikula, rodrigo.vivi, dri-devel, intel-gfx; +Cc: Puthikorn Voravootivat
[-- Attachment #1.1: Type: text/plain, Size: 2884 bytes --]
On Monday 25 September 2017 02:00 PM, Jani Nikula wrote:
> On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> Set frames before SU entry value for max resync frame count of
>> dpcd register 2009, bit field 0:3.
>>
>> v2 :
>> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
>> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
>> - add check ==1 for dpcd_read call (ville)
>>
>> v3 : (Rodrigo)
>> - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
>> - replace with &=
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>> 2 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 82f36dd..b880c84 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4047,7 +4047,7 @@ enum {
>> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
>> #define EDP_PSR2_IDLE_MASK 0xf
>> -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
>> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
> In the register definitions we use the shift values directly, not the
> macro. That's the style we've adopted. Please stick to it.
Macro was suggested by Rodrigo.
>
> Ditto for the indent, why do you remove it?
BR, Jani.
>>
>> #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
>> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 0a17d1f..adf7abc 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>> */
>> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>> uint32_t val;
>> + uint8_t sink_latency;
>>
>> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>>
>> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>> * mesh at all with our frontbuffer tracking. And the hw alone isn't
>> * good enough. */
>> val |= EDP_PSR2_ENABLE |
>> - EDP_SU_TRACK_ENABLE |
>> - EDP_FRAMES_BEFORE_SU_ENTRY;
>> + EDP_SU_TRACK_ENABLE;
>> +
>> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
>> + &sink_latency) == 1) {
>> + sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
>> + } else {
>> + sink_latency = 0;
>> + }
>> + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>>
>> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> val |= EDP_PSR2_TP2_TIME_2500;
[-- Attachment #1.2: Type: text/html, Size: 3906 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-25 9:10 ` vathsala nagaraju
@ 2017-09-25 16:57 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2017-09-25 16:57 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: Puthikorn Voravootivat, intel-gfx, dri-devel
On Mon, Sep 25, 2017 at 09:10:28AM +0000, vathsala nagaraju wrote:
> On Monday 25 September 2017 02:00 PM, Jani Nikula wrote:
>
> On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> v2 :
> - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
> - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
> - add check ==1 for dpcd_read call (ville)
>
> v3 : (Rodrigo)
> - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
> - replace with &=
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..b880c84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4047,7 +4047,7 @@ enum {
> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
> #define EDP_PSR2_IDLE_MASK 0xf
> -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
>
> In the register definitions we use the shift values directly, not the
> macro. That's the style we've adopted. Please stick to it.
>
> Macro was suggested by Rodrigo.
Well, one bad review is not an excuse to ignore a good review ;)
But what Jani mentioned and he is absolutelly right is to use the shift value
directly instead the SHIFT macro, not to avoid the function-like macro that I
suggested.
In other words:
#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
Please also note his request on the spaces required for proper identation.
And also please address his comments on the first patch to make the defines
in total sync with DP Spec.
Thanks,
Rodrigo.
>
>
> Ditto for the indent, why do you remove it?
>
> BR, Jani.
>
>
> #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..adf7abc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency) == 1) {
> + sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;
> + } else {
> + sink_latency = 0;
> + }
> + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
>
>
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/2] drm/dp: Add defines for latency in sink
@ 2017-09-26 9:59 vathsala nagaraju
2017-09-26 9:59 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
0 siblings, 1 reply; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-26 9:59 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: Puthikorn Voravootivat, vathsala nagaraju, Rodrigo Vivi
Add defines for dpcd register 2009 (synchronization latency
in sink).
v2:
- add spec version (Daniel)
- use register name as is in spec,only drop excess
from end (jani)
- add the full register contents (jani)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
include/drm/drm_dp_helper.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11c39f1..f58dcb9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -735,6 +735,12 @@
# define DP_PSR_SINK_INTERNAL_ERROR 7
# define DP_PSR_SINK_STATE_MASK 0x07
+#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4b */
+# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
+# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
+
#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
--
1.9.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
2017-09-26 9:59 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
@ 2017-09-26 9:59 ` vathsala nagaraju
0 siblings, 0 replies; 19+ messages in thread
From: vathsala nagaraju @ 2017-09-26 9:59 UTC (permalink / raw)
To: dri-devel, intel-gfx
Cc: Puthikorn Voravootivat, vathsala nagaraju, Rodrigo Vivi
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
v3 : (Rodrigo)
- move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
- replace with &=
v4 :
- change the macro to shift value (jani)
- updated register names
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_psr.c | 13 +++++++++++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..7e7aa60 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4047,7 +4047,7 @@ enum {
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
#define EDP_PSR2_IDLE_MASK 0xf
-#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4)
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
#define EDP_PSR2_STATUS_CTL _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..5419cda 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val;
+ uint8_t sink_latency;
val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -334,8 +335,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* mesh at all with our frontbuffer tracking. And the hw alone isn't
* good enough. */
val |= EDP_PSR2_ENABLE |
- EDP_SU_TRACK_ENABLE |
- EDP_FRAMES_BEFORE_SU_ENTRY;
+ EDP_SU_TRACK_ENABLE;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_SYNCHRONIZATION_LATENCY_IN_SINK,
+ &sink_latency) == 1) {
+ sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
+ } else {
+ sink_latency = 0;
+ }
+ val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
--
1.9.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread
end of thread, other threads:[~2017-09-29 11:36 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-20 14:44 ` Ville Syrjälä
2017-09-20 15:19 ` Vivi, Rodrigo
2017-09-22 15:58 ` vathsala nagaraju
2017-09-22 23:54 ` Rodrigo Vivi
2017-09-28 16:54 ` Rodrigo Vivi
2017-09-29 11:36 ` Jani Nikula
2017-09-20 14:58 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink Patchwork
2017-09-20 15:51 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-09-20 22:07 ` [PATCH 1/2] " Rodrigo Vivi
2017-09-21 14:42 ` Rodrigo Vivi
2017-09-26 5:11 ` Daniel Vetter
2017-09-26 17:37 ` Puthikorn Voravootivat
2017-09-26 20:37 ` Puthikorn Voravootivat
2017-09-26 20:53 ` [Intel-gfx] " Rodrigo Vivi
2017-09-23 0:34 vathsala nagaraju
2017-09-23 0:34 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-25 8:30 ` [Intel-gfx] " Jani Nikula
2017-09-25 9:10 ` vathsala nagaraju
2017-09-25 16:57 ` Rodrigo Vivi
2017-09-26 9:59 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-26 9:59 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
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