[PATCH 1/2] drm/dp: Add defines for latency in sink

[PATCH 1/2] drm/dp: Add defines for latency in sink

[vathsala nagaraju]

Add defines for dpcd register 2009 (synchronization latency
in sink).

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 include/drm/drm_dp_helper.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11c39f1..846004e6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -735,6 +735,9 @@
 # define DP_PSR_SINK_INTERNAL_ERROR         7
 # define DP_PSR_SINK_STATE_MASK             0x07
 
+#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
+# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
+
 #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
 # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
 
-- 
1.9.1

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[PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[vathsala nagaraju]

Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index acb5094..04b253f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 */
 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 	uint32_t val;
+	uint8_t sink_latency;
 
 	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
 	val |= EDP_PSR2_ENABLE |
-		EDP_SU_TRACK_ENABLE |
-		EDP_FRAMES_BEFORE_SU_ENTRY;
+		EDP_SU_TRACK_ENABLE;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+				&sink_latency)) {
+		sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
+		val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
+	} else {
+		val |= EDP_FRAMES_BEFORE_SU_ENTRY;
+	}
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
-- 
1.9.1

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Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Ville Syrjälä]

On Wed, Sep 20, 2017 at 08:02:35PM +0530, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	uint32_t val;
> +	uint8_t sink_latency;
>  
>  	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
>  	val |= EDP_PSR2_ENABLE |
> -		EDP_SU_TRACK_ENABLE |
> -		EDP_FRAMES_BEFORE_SU_ENTRY;
> +		EDP_SU_TRACK_ENABLE;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> +				&sink_latency)) {

== 1

> +		sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> +		val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
> +	} else {
> +		val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> +	}
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/dp: Add defines for latency in sink
URL   : https://patchwork.freedesktop.org/series/30658/
State : success

== Summary ==

Series 30658v1 series starting with [1/2] drm/dp: Add defines for latency in sink
https://patchwork.freedesktop.org/api/1.0/series/30658/revisions/1/mbox/

Test gem_exec_suspend:
        Subgroup basic-s3:
                incomplete -> PASS       (fi-kbl-7500u) fdo#102850
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                fail       -> PASS       (fi-snb-2600) fdo#100215
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                skip       -> PASS       (fi-ivb-3520m)
        Subgroup force-edid:
                skip       -> PASS       (fi-ivb-3520m)
        Subgroup force-load-detect:
                skip       -> PASS       (fi-ivb-3520m)
        Subgroup prune-stale-modes:
                skip       -> PASS       (fi-ivb-3520m)
Test pm_rpm:
        Subgroup basic-rte:
                dmesg-warn -> PASS       (fi-cfl-s) fdo#102294

fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:440s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:469s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:420s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:515s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:277s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:502s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:488s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:493s
fi-cfl-s         total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  time:548s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:425s
fi-glk-1         total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:568s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:423s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:405s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:434s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:484s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:467s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:475s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:568s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:590s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:540s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:441s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:749s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:491s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:470s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:567s
fi-snb-2600      total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:411s

ed7a99bf23cea2276e77ba26d219e58e069d1e32 drm-tip: 2017y-09m-20d-11h-03m-37s UTC integration manifest
8dc01494eee9 drm/i915/psr: Set frames before SU entry for psr2
568cf132cf88 drm/dp: Add defines for latency in sink

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5765/
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Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Vivi, Rodrigo]

> On Sep 20, 2017, at 7:33 AM, Nagaraju, Vathsala <vathsala.nagaraju@intel.com> wrote:
> 
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>     */
>    uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>    uint32_t val;
> +    uint8_t sink_latency;
> 
>    val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> 
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>     * mesh at all with our frontbuffer tracking. And the hw alone isn't
>     * good enough. */
>    val |= EDP_PSR2_ENABLE |
> -        EDP_SU_TRACK_ENABLE |
> -        EDP_FRAMES_BEFORE_SU_ENTRY;

Please also remove the definition of this su_entry since it was not following the new standards anyway...
Probably good to replace with function macro style for better use below...

> +        EDP_SU_TRACK_ENABLE;
> +
> +    if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> +                &sink_latency)) {
> +        sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> +        val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;

... so you could use
val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency +1);


> +    } else {
> +        val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> +    }
> 
>    if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>        val |= EDP_PSR2_TP2_TIME_2500;
> -- 
> 1.9.1
> 
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✗ Fi.CI.IGT: warning for series starting with [1/2] drm/dp: Add defines for latency in sink

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/dp: Add defines for latency in sink
URL   : https://patchwork.freedesktop.org/series/30658/
State : warning

== Summary ==

Test perf:
        Subgroup polling:
                fail       -> PASS       (shard-hsw) fdo#102252 +1
Test kms_plane:
        Subgroup plane-panning-bottom-right-suspend-pipe-A-planes:
                pass       -> DMESG-WARN (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hsw        total:2317 pass:1244 dwarn:3   dfail:0   fail:13  skip:1057 time:9583s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5765/shards.html
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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Rodrigo Vivi]

On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 11c39f1..846004e6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -735,6 +735,9 @@
>  # define DP_PSR_SINK_INTERNAL_ERROR         7
>  # define DP_PSR_SINK_STATE_MASK             0x07
>  
> +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
> +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf

where did you get that?
eDP 1.4 teels 2009h is a debug register.

> +
>  #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
>  # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
>  
> -- 
> 1.9.1
> 
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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Rodrigo Vivi]

On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

I keep forgetting to update my eDP spec 1.4 to this 1.4b...


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> ---
>  include/drm/drm_dp_helper.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 11c39f1..846004e6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -735,6 +735,9 @@
>  # define DP_PSR_SINK_INTERNAL_ERROR         7
>  # define DP_PSR_SINK_STATE_MASK             0x07
>  
> +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
> +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
> +
>  #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
>  # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
>  
> -- 
> 1.9.1
> 
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[PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[vathsala nagaraju]

Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.

v2 :
 - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
 - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
 - add check ==1 for dpcd_read call (ville)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 +-
 drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82f36dd..89c5249 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 	(mask) << 16 | (value); })
 #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
 
 /* Engine ID */
 
@@ -4047,7 +4048,6 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
-#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 0a17d1f..e505fa6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 */
 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 	uint32_t val;
+	uint8_t sink_latency;
 
 	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
@@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
 	val |= EDP_PSR2_ENABLE |
-		EDP_SU_TRACK_ENABLE |
-		EDP_FRAMES_BEFORE_SU_ENTRY;
+		EDP_SU_TRACK_ENABLE;
+
+	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
+				&sink_latency) == 1) {
+		sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
+	} else {
+		sink_latency = 0;
+	}
+	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
-- 
1.9.1

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Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Rodrigo Vivi]

On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
> 
> v2 :
>  - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
>  - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
>  - add check ==1 for dpcd_read call (ville)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..89c5249 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  	(mask) << 16 | (value); })
>  #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
>  #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)

not here

>  
>  /* Engine ID */
>  
> @@ -4047,7 +4048,6 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK		0xf
> -#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)

move here

>  
>  #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..e505fa6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	uint32_t val;
> +	uint8_t sink_latency;
>  
>  	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
>  	val |= EDP_PSR2_ENABLE |
> -		EDP_SU_TRACK_ENABLE |
> -		EDP_FRAMES_BEFORE_SU_ENTRY;
> +		EDP_SU_TRACK_ENABLE;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> +				&sink_latency) == 1) {
> +		sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;

		sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK;

with those changes

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> +	} else {
> +		sink_latency = 0;
> +	}
> +	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;
> -- 
> 1.9.1
> 
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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Daniel Vetter]

On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
> On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> > Add defines for dpcd register 2009 (synchronization latency
> > in sink).
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Puthikorn Voravootivat <puthik@chromium.org>
> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> 
> I keep forgetting to update my eDP spec 1.4 to this 1.4b...

Maybe the patch should then make this clear, by annotating it with
/* eDP 1.4b */ That's missing, which isn't all that great really, since it
makes specs hunts like yours necessary.

Please fix up before applying.
-Daniel
> 
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> 
> 
> > ---
> >  include/drm/drm_dp_helper.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 11c39f1..846004e6 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -735,6 +735,9 @@
> >  # define DP_PSR_SINK_INTERNAL_ERROR         7
> >  # define DP_PSR_SINK_STATE_MASK             0x07
> >  
> > +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
> > +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
> > +
> >  #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
> >  # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
> >  
> > -- 
> > 1.9.1
> > 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Puthikorn Voravootivat]

[-- Attachment #1.1: Type: text/plain, Size: 1895 bytes --]

On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter <daniel@ffwll.ch> wrote:

> On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
> > On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
> > > Add defines for dpcd register 2009 (synchronization latency
> > > in sink).
> > >
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > CC: Puthikorn Voravootivat <puthik@chromium.org>
> > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> >
> > I keep forgetting to update my eDP spec 1.4 to this 1.4b...
>
> Maybe the patch should then make this clear, by annotating it with
> /* eDP 1.4b */ That's missing, which isn't all that great really, since it
> makes specs hunts like yours necessary.
>
> It's actually in eDP 1.4 spec, table 5-6 page 86


> Please fix up before applying.
> -Daniel
> >
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> >
> >
> > > ---
> > >  include/drm/drm_dp_helper.h | 3 +++
> > >  1 file changed, 3 insertions(+)
> > >
> > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > > index 11c39f1..846004e6 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -735,6 +735,9 @@
> > >  # define DP_PSR_SINK_INTERNAL_ERROR         7
> > >  # define DP_PSR_SINK_STATE_MASK             0x07
> > >
> > > +#define DP_SINK_SYNCHRONIZATION_LATENCY        0x2009
> > > +# define DP_MAX_RESYNC_FRAME_CNT_MASK          0xf
> > > +
> > >  #define DP_RECEIVER_ALPM_STATUS                0x200b  /* eDP 1.4 */
> > >  # define DP_ALPM_LOCK_TIMEOUT_ERROR            (1 << 0)
> > >
> > > --
> > > 1.9.1
> > >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
>

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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Puthikorn Voravootivat]

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On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat <
puthik@chromium.org> wrote:

>
>
> On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
>
>> On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
>> > On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
>> > > Add defines for dpcd register 2009 (synchronization latency
>> > > in sink).
>> > >
>> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > > CC: Puthikorn Voravootivat <puthik@chromium.org>
>> > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> >
>> > I keep forgetting to update my eDP spec 1.4 to this 1.4b...
>>
>> Maybe the patch should then make this clear, by annotating it with
>> /* eDP 1.4b */ That's missing, which isn't all that great really, since it
>> makes specs hunts like yours necessary.
>>
>> It's actually in eDP 1.4 spec, table 5-6 page 86
>
Copy and paste the wrong one.
0x2009 is actually in eDP 1.4 spec, Table 6-7: DPCD – Sink Device PSR
Status Field page 124


>
>
>> Please fix up before applying.
>> -Daniel
>> >
>> >
>> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> >
>> >
>> >
>> > > ---
>> > >  include/drm/drm_dp_helper.h | 3 +++
>> > >  1 file changed, 3 insertions(+)
>> > >
>> > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> > > index 11c39f1..846004e6 100644
>> > > --- a/include/drm/drm_dp_helper.h
>> > > +++ b/include/drm/drm_dp_helper.h
>> > > @@ -735,6 +735,9 @@
>> > >  # define DP_PSR_SINK_INTERNAL_ERROR         7
>> > >  # define DP_PSR_SINK_STATE_MASK             0x07
>> > >
>> > > +#define DP_SINK_SYNCHRONIZATION_LATENCY        0x2009
>> > > +# define DP_MAX_RESYNC_FRAME_CNT_MASK          0xf
>> > > +
>> > >  #define DP_RECEIVER_ALPM_STATUS                0x200b  /* eDP 1.4 */
>> > >  # define DP_ALPM_LOCK_TIMEOUT_ERROR            (1 << 0)
>> > >
>> > > --
>> > > 1.9.1
>> > >
>> > _______________________________________________
>> > dri-devel mailing list
>> > dri-devel@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch
>>
>
>

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Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

[Rodrigo Vivi]

On Tue, Sep 26, 2017 at 1:37 PM, Puthikorn Voravootivat
<puthik@chromium.org> wrote:
>
>
> On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat
> <puthik@chromium.org> wrote:
>>
>>
>>
>> On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
>>>
>>> On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
>>> > On Wed, Sep 20, 2017 at 02:32:34PM +0000, vathsala nagaraju wrote:
>>> > > Add defines for dpcd register 2009 (synchronization latency
>>> > > in sink).
>>> > >
>>> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> > > CC: Puthikorn Voravootivat <puthik@chromium.org>
>>> > > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>>> >
>>> > I keep forgetting to update my eDP spec 1.4 to this 1.4b...
>>>
>>> Maybe the patch should then make this clear, by annotating it with
>>> /* eDP 1.4b */ That's missing, which isn't all that great really, since
>>> it
>>> makes specs hunts like yours necessary.
>>>
>> It's actually in eDP 1.4 spec, table 5-6 page 86
>
> Copy and paste the wrong one.
> 0x2009 is actually in eDP 1.4 spec, Table 6-7: DPCD – Sink Device PSR Status
> Field page 124

you are absolutely right! eDP 1.4 has it. even the eDP 1.4a had...
I definitely had a strange version here... All updated locally here.

For the patch I will update when merging. No need to send a newer version.
I intend to merge patches tomorrow if no one has any other comment or
concern on those.

>
>>
>>
>>>
>>> Please fix up before applying.
>>> -Daniel
>>> >
>>> >
>>> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> >
>>> >
>>> >
>>> > > ---
>>> > >  include/drm/drm_dp_helper.h | 3 +++
>>> > >  1 file changed, 3 insertions(+)
>>> > >
>>> > > diff --git a/include/drm/drm_dp_helper.h
>>> > > b/include/drm/drm_dp_helper.h
>>> > > index 11c39f1..846004e6 100644
>>> > > --- a/include/drm/drm_dp_helper.h
>>> > > +++ b/include/drm/drm_dp_helper.h
>>> > > @@ -735,6 +735,9 @@
>>> > >  # define DP_PSR_SINK_INTERNAL_ERROR         7
>>> > >  # define DP_PSR_SINK_STATE_MASK             0x07
>>> > >
>>> > > +#define DP_SINK_SYNCHRONIZATION_LATENCY        0x2009
>>> > > +# define DP_MAX_RESYNC_FRAME_CNT_MASK          0xf
>>> > > +
>>> > >  #define DP_RECEIVER_ALPM_STATUS                0x200b  /* eDP 1.4 */
>>> > >  # define DP_ALPM_LOCK_TIMEOUT_ERROR            (1 << 0)
>>> > >
>>> > > --
>>> > > 1.9.1
>>> > >
>>> > _______________________________________________
>>> > dri-devel mailing list
>>> > dri-devel@lists.freedesktop.org
>>> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>>
>>> --
>>> Daniel Vetter
>>> Software Engineer, Intel Corporation
>>> http://blog.ffwll.ch
>>
>>
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>



-- 
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Blog: http://blog.vivi.eng.br
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Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Rodrigo Vivi]

On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
> 
> v2 :
>  - add macro  EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
>  - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
>  - add check ==1 for dpcd_read call (ville)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>

Merged both patches to dinq. Thanks for the patches.

I'm anxiously waiting the PSR2 related workaroud(s)! ;)

Thanks,
Rodrigo.

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  2 +-
>  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82f36dd..89c5249 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  	(mask) << 16 | (value); })
>  #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
>  #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
> +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT)
>  
>  /* Engine ID */
>  
> @@ -4047,7 +4048,6 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK		0xf
> -#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
>  
>  #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0a17d1f..e505fa6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	uint32_t val;
> +	uint8_t sink_latency;
>  
>  	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
>  	val |= EDP_PSR2_ENABLE |
> -		EDP_SU_TRACK_ENABLE |
> -		EDP_FRAMES_BEFORE_SU_ENTRY;
> +		EDP_SU_TRACK_ENABLE;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> +				&sink_latency) == 1) {
> +		sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> +	} else {
> +		sink_latency = 0;
> +	}
> +	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;
> -- 
> 1.9.1
> 
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Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Jani Nikula]

On Thu, 28 Sep 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Merged both patches to dinq. Thanks for the patches.

While patch 1 was a simple addition of a few DP macros, we need to get
ack from Dave or (preferrably non-Intel) drm-misc maintainers before
queuing non-i915 patches through drm-intel.

Dave, Sean, ack after the fact...?

The patch is [1].


BR,
Jani.


[1] http://patchwork.freedesktop.org/patch/msgid/1506419953-32605-1-git-send-email-vathsala.nagaraju@intel.com

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[PATCH 1/2] drm/dp: Add defines for latency in sink

[vathsala nagaraju]

Add defines for dpcd register 2009 (synchronization latency
in sink).

v2:
 - add spec version (Daniel)
 - use register name as is in spec,only drop excess
   from end (jani)
 - add the full register contents (jani)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 include/drm/drm_dp_helper.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11c39f1..f58dcb9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -735,6 +735,12 @@
 # define DP_PSR_SINK_INTERNAL_ERROR         7
 # define DP_PSR_SINK_STATE_MASK             0x07
 
+#define DP_SYNCHRONIZATION_LATENCY_IN_SINK	0x2009 /* edp 1.4b */
+# define DP_MAX_RESYNC_FRAME_COUNT_MASK			(0xf << 0)
+# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT		0
+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK	(0xf << 4)
+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT	4
+
 #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
 # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
 
-- 
1.9.1

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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Rodrigo Vivi]

On Mon, Sep 25, 2017 at 09:01:38AM +0000, vathsala nagaraju wrote:
> On Monday 25 September 2017 01:53 PM, Jani Nikula wrote:
> 
>     On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> 
>         Add defines for dpcd register 2009 (synchronization latency
>         in sink).
> 
>         Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>         CC: Puthikorn Voravootivat <puthik@chromium.org>
>         Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>         Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>         ---
>          include/drm/drm_dp_helper.h | 3 +++
>          1 file changed, 3 insertions(+)
> 
>         diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>         index 11c39f1..846004e6 100644
>         --- a/include/drm/drm_dp_helper.h
>         +++ b/include/drm/drm_dp_helper.h
>         @@ -735,6 +735,9 @@
>          # define DP_PSR_SINK_INTERNAL_ERROR         7
>          # define DP_PSR_SINK_STATE_MASK             0x07
> 
>         +#define DP_SINK_SYNCHRONIZATION_LATENCY            0x2009
>         +# define DP_MAX_RESYNC_FRAME_CNT_MASK      0xf
> 
>     For the DP spec, please don't invent the names, use the ones from the
>     spec. At most drop excess stuff from the end.
> 
> In edp 1.4b spec , the register name 2009 is "DEBUG 0 SYNCHRONIZATION LATENCY SINK "  and
> bit 0:3 "MAX RE-SYNC FRAME COUNT"

probably he meant something like:

# define DP_SYNCHRONIZATION_LATENCY_IN_SINK            0x2009
# define DP_MAX_RESYNC_FRAME_COUNT_MASK      0xf

but he is the best one to confirm that...

> 
> 
>     #define DP_SYNCHRONIZATION_LATENCY_IN_SINK
>     # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
>     # define DP_MAX_RESYNC_FRAME_COUNT_MASK
> 
>     And while at it, please add the full register contents.
> 
>     BR,
>     Jani.
> 
> 
>         +
>          #define DP_RECEIVER_ALPM_STATUS                    0x200b  /* eDP 1.4 */
>          # define DP_ALPM_LOCK_TIMEOUT_ERROR        (1 << 0)
> 
> 
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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[vathsala nagaraju]

[-- Attachment #1.1: Type: text/plain, Size: 1519 bytes --]

On Monday 25 September 2017 01:53 PM, Jani Nikula wrote:
> On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
>> Add defines for dpcd register 2009 (synchronization latency
>> in sink).
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>   include/drm/drm_dp_helper.h | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index 11c39f1..846004e6 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -735,6 +735,9 @@
>>   # define DP_PSR_SINK_INTERNAL_ERROR         7
>>   # define DP_PSR_SINK_STATE_MASK             0x07
>>   
>> +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
>> +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
> For the DP spec, please don't invent the names, use the ones from the
> spec. At most drop excess stuff from the end.
In edp 1.4b spec , the register name 2009 is "DEBUG 0 SYNCHRONIZATION 
LATENCY SINK "  and bit 0:3 "MAX RE-SYNC FRAME COUNT"
>
> #define DP_SYNCHRONIZATION_LATENCY_IN_SINK
> # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
> # define DP_MAX_RESYNC_FRAME_COUNT_MASK
>
> And while at it, please add the full register contents.
>
> BR,
> Jani.
>
>> +
>>   #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
>>   # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)


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Re: [PATCH 1/2] drm/dp: Add defines for latency in sink

[Jani Nikula]

On Sat, 23 Sep 2017, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote:
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 11c39f1..846004e6 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -735,6 +735,9 @@
>  # define DP_PSR_SINK_INTERNAL_ERROR         7
>  # define DP_PSR_SINK_STATE_MASK             0x07
>  
> +#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
> +# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf

For the DP spec, please don't invent the names, use the ones from the
spec. At most drop excess stuff from the end.

#define DP_SYNCHRONIZATION_LATENCY_IN_SINK
# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT
# define DP_MAX_RESYNC_FRAME_COUNT_MASK

And while at it, please add the full register contents.

BR,
Jani.

> +
>  #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
>  # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 1/2] drm/dp: Add defines for latency in sink

[vathsala nagaraju]

Add defines for dpcd register 2009 (synchronization latency
in sink).

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 include/drm/drm_dp_helper.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11c39f1..846004e6 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -735,6 +735,9 @@
 # define DP_PSR_SINK_INTERNAL_ERROR         7
 # define DP_PSR_SINK_STATE_MASK             0x07
 
+#define DP_SINK_SYNCHRONIZATION_LATENCY	    0x2009
+# define DP_MAX_RESYNC_FRAME_CNT_MASK	    0xf
+
 #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
 # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
 
-- 
1.9.1

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